基于双面TSV互连技术的超厚硅转接板制备
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摘要
为了满足异质集成应用中对转接板机械性能方面的需求,提出了一种基于双面硅通孔(TSV)互连技术的超厚硅转接板的制备工艺方案。该方案采用Bosch工艺在转接板正面形成300μm深的TSV,通过结合保型性电镀工艺和底部填充电镀工艺进行TSV填充。在转接板背面工艺中首先通过光刻将双面TSV的重叠部分控制在一个理想的范围内,然后经深反应离子刻蚀(DRIE)工艺形成深度为20μm的TSV并完成绝缘层开窗,最后使用保型性电镀完成TSV互连。通过解决TSV刻蚀中侧壁形貌粗糙、TSV底部金属层过薄和光刻胶显影不洁等关键问题,最终得到了双面互连电阻约为20Ω、厚度约为323μm的硅转接板。
In order to meet the mechanical performance requirements of interposers in heterogeneous integration applications,the fabrication process of the ultra-thick interposer based on double-sided through silicon via(TSV)interconnection technology was proposed.The Bosch process was used to form TSV with a depth of 300μm on the front of the interposer,the TSV was filled by combining the conformal electroplating process and bottom-up electroplating process.In the back process of the interposer,the overlap of the double-sided TSV was controlled within a desired range by the lithography firstly.Then,the TSV with a depth of 20μm was formed by deep reactive ion etching(DRIE)process and the opening window of the insulating layer was completed.Finally,the TSV interconnection was completed using the conformal electroplating.By solving the key problems of rough sidewall morphology,over-thin metal layer at the TSV bottom and unclean photoresist development during the TSV etching,a silicon interposer with a doublesided interconnect resis-tance of about 20Ωand a thickness of about 323μm was finally obtained.
In order to meet the mechanical performance requirements of interposers in heterogeneous integration applications,the fabrication process of the ultra-thick interposer based on double-sided through silicon via(TSV)interconnection technology was proposed.The Bosch process was used to form TSV with a depth of 300μm on the front of the interposer,the TSV was filled by combining the conformal electroplating process and bottom-up electroplating process.In the back process of the interposer,the overlap of the double-sided TSV was controlled within a desired range by the lithography firstly.Then,the TSV with a depth of 20μm was formed by deep reactive ion etching(DRIE)process and the opening window of the insulating layer was completed.Finally,the TSV interconnection was completed using the conformal electroplating.By solving the key problems of rough sidewall morphology,over-thin metal layer at the TSV bottom and unclean photoresist development during the TSV etching,a silicon interposer with a doublesided interconnect resis-tance of about 20Ωand a thickness of about 323μm was finally obtained.
引文
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[12] XU T T,TAO Z,LI H Q,et al.Effects of deep reactiveion etching parameters on etching rate and surface morphology in extremely deep silicon etch process with high aspect ratio[J].Advances in Mechanical Engineering,2017,9(12):1-19.
[13] CHANG C L,WANG Y F,KANAMORI Y,et al.Etching submicrometer trenches by using the Bosch process and its application to the fabrication of antireflection structures[J].Journal of Micromechanics and Micro-engineering,2005,15(3):580-585.
[14]窦维平.利用电镀铜填充微米盲孔与通孔之应用[J].复旦学报(自然科学版),2012,51(2):131-138,259-260.
[15]程万.高深宽比的TSV电镀铜填充技术研究[D].北京:中国科学院大学,2017.
[16]吴鹏.优化铜种子层对电镀铜孔洞缺陷的改善[D].上海:复旦大学,2011.
[2] EMMA P G,KURSUN E.Is 3D chip technology the next growth engine for performance improvement?[J].IBM Journal of Research and Development,2008,52(6):541-552.
[3] KNICKERBOCKER J U,ANDRY P S,DANG B,et al.Threedimensional silicon integration[J].IBM Journal of Research and Development,2008,52(6):553-569.
[4] GAO N Y,CAO Y Y,ZHU Y,et al.Imitation chip design based on TSV2.5D package[C]//Proceedings of the 16thInternational Conference on Electronic Packaging Technology(ICEPT).Changsha,China,2015:122-124.
[5] PARES G,KAROUI C,ZAID A,et al.Full integration of a3D demonstrator with TSV first interposer,ultra-thin die stacking and wafer level packaging[C]//Proceedings of the 63rd Electronic Components and Technology Conference.Las Vegas,NV,USA,2013:305-306.
[6] LI Z,SHI H,XIE J,et al.Development of an optimized power delivery system for 3D IC integration with TSV silicon interposer[C]//Proceedings of the 62nd Electronic Components and Technology Conference.San Diego,California,USA,2012:678-682.
[7] ZOSCHKE K,WOLF J,LOPPER C,et al.TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules[C]//Proceedings of the 61st Electronic Components and Technology Conference(ECTC).Lake Buena Vista,Florida,USA,2011:836-843.
[8] KUMAR N,RAMASWAMI S,DUKOVIC J,et al.Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation[C]//Proceedings of the 62nd Electronic Components and Technology Conference.San Diego,CA,USA,2012:787-793.
[9] SONG C S,WANG L,WANG Z,et al.TSV reveal process developments for 2.5D integration[C]//Proceedings of the15th Electronics Packaging Technology Conference.Singapore,Singapore,2013:714-727.
[10]蔡长龙,马睿,刘卫国,等.硅深刻蚀中掩蔽层材料刻蚀选择比的研究[J].半导体光电,2009,30(2):211-214.
[11]迈克尔·夸克,朱利安·瑟达.半导体制备技术[M].韩生,译.北京:电子工业出版社,2015:409-410.
[12] XU T T,TAO Z,LI H Q,et al.Effects of deep reactiveion etching parameters on etching rate and surface morphology in extremely deep silicon etch process with high aspect ratio[J].Advances in Mechanical Engineering,2017,9(12):1-19.
[13] CHANG C L,WANG Y F,KANAMORI Y,et al.Etching submicrometer trenches by using the Bosch process and its application to the fabrication of antireflection structures[J].Journal of Micromechanics and Micro-engineering,2005,15(3):580-585.
[14]窦维平.利用电镀铜填充微米盲孔与通孔之应用[J].复旦学报(自然科学版),2012,51(2):131-138,259-260.
[15]程万.高深宽比的TSV电镀铜填充技术研究[D].北京:中国科学院大学,2017.
[16]吴鹏.优化铜种子层对电镀铜孔洞缺陷的改善[D].上海:复旦大学,2011.