Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer
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摘要
A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.
A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.
A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.
引文
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[34]Dubey P K and Kaushik B K 2017 IEEE Transactions on Electron Devices 64 3120
[35]Ding L,Gnani E,Gerardin S,Bagatin M,Driussi F,Palestri P,Selmi L,Royer C L and Paccagnella A 2015 IEEE Transactions on Device and Materials Reliability 15 236
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[37]Kwon D W,Kim H W,Kim J H,Park E,Lee J,Kim W,Kim S,Lee JH and Park B G 2017 IEEE Transactions on Electron Devices 64 1799
[2]Frank D J,Dennard R H,Nowak E,Solomon P M,Taur Y and Wong H S P 2001 Proceedings of the IEEE 89 259
[3]Colinge J P 2004 Solid-State Electronics 48 897
[4]Wang P F,Hilsenbeck K,Nirschl T,Oswald M,Stepper C,Weis M,Schmitt-Landsiedel D and Hansch W 2004 Solid-State Electronics 482281
[5]Frank D J 2002 IBM Journal of Research and Development 46 235
[6]Iwai H 2009 Microelectronic Engineering 86 1520
[7]Zhang Q,Zhao W and Seabaugh A 2006 IEEE Electron Device Letters27 297
[8]Choi W Y,Park B G,Lee J D and Liu T J K 2007 IEEE Electron Device Letters 28 743
[9]Boucart K and Ionescu A M 2007 IEEE Transactions on Electron Devices 54 1725
[10]Mayer F,Royer C L,Damlencourt J F,Romanjek K,Andrieu F,Tabone C,Previtali B and Deleonibus S 2008 IEEE International Electron Devices Meeting 2008 1
[11]Verhulst A S,Vandenberghe W G,Maex K and Groeseneken G 2008 J.Appl.Phys.104 064514
[12]Seabaugh A C and Zhang Q 2010 Proceedings of the IEEE 98 2095
[13]Ionescu A M and Riel H 2011 Nature 479 329
[14]Guan Y H,Li Z C,Luo D X,Meng Q Z and Zhang Y F 2016 Chin.Phys.B 25 108502
[15]Kang H Y,Hu H Y and Wang B 2016 Chin.Phys.B 25 118501
[16]Toh E H,Wang G H,Chan L,Samudra G and Yeo Y C 2007 Appl.Phys.Lett.91 243505
[17]Kao K H,Verhulst A S,Vandenberghe W G,Soree B,Groeseneken Gand De Meyer K 2012 IEEE Transactions on Electron Devices 59 292
[18]Vandooren A,Leonelli D,Rooyackers R,Arstila K,Groeseneken Gand Huyghebaert C 2012 Solid-State Electronics 72 82
[19]Raad B,Nigam K,Sharma D and Kondekar P 2016 Electronics Letters52 770
[20]Jiang Z,Zhuang Y Q,Li C,Wang P and Liu Y Q 2016 Chinese Physics B 25 027701
[21]Feng S,Zhang Q,Yang J,Lei M and Quhe R 2017 Chin.Phys.B 26097401
[22]Low K L,Zhan C,Han G,Yang Y,Goh K H,Guo P,Toh E H and Yeo Y C 2012 Jpn J.Appl.Phys.51 02BC04
[23]Kim S W,Choi W Y,Sun M C,Kim H W and Park B G 2012 Jpn J.Appl.Phys.51 06FE09
[24]Kim J H,Kim S W,Kim H W and Park B G 2015 Electronics Letters51 718
[25]Yang Z 2016 IEEE Electron Device Letters 37 839
[26]Li W,Liu H,Wang S and Chen S 2016 Superlattices and Microstructures 100 1238
[27]Li W,Liu H,Wang S,Chen S and Yang Z 2017 Nanoscale Research Letters 12 198
[28]Imenabadi R M,Saremi M and Vandenberghe W G 2017 IEEE Transactions on Electron Devices 64 4752
[29]Yang Z,Zhang Y,Yang Y and Yu N 2017 Superlattices and Microstructures 111 1226
[30]Zhang W H,Li Z C,Guan Y H and Zhang Y F 2017 Chin.Phys.B 26018504
[31]Li C,Yan Z R,Zhuang Y Q,Zhao X L and Guo J M 2018 Chin.Phys.B 27 078502
[32]Li C,Zhao X,Zhuang Y,Yan Z,Guo J and Han R 2018 Superlattices and Microstructures 115 154
[33]Kim S W,Kim J H,Liu T J K,Choi W Y and Park B G 2016 IEEETransactions on Electron Devices 63 1774
[34]Dubey P K and Kaushik B K 2017 IEEE Transactions on Electron Devices 64 3120
[35]Ding L,Gnani E,Gerardin S,Bagatin M,Driussi F,Palestri P,Selmi L,Royer C L and Paccagnella A 2015 IEEE Transactions on Device and Materials Reliability 15 236
[36]Ghosh S,Koley K and Sarkar C K 2015 Microelectronics Reliability55 326
[37]Kwon D W,Kim H W,Kim J H,Park E,Lee J,Kim W,Kim S,Lee JH and Park B G 2017 IEEE Transactions on Electron Devices 64 1799