摘要
随着计算机、信息技术的飞速发展,手机移动支付在日常生活中已经变得十分普遍。借助于强大的互联网,移动支付避免携带大量现金所带来的风险,也省去找零和假币所带来的困扰,更加快捷、安全。本设计基于EDA技术,用FPGA(Field Programmable Gate Array)芯片,使用Verilog HDL语言,进行购物支付系统的设计。将支付过程用有限状态机来设计,用Verilog HDL语言建模和编程,与常用的应用单片机的设计相比,FPGA更为简单,且运行速度更快。
With the rapid development of computer and information technology,mobile payment has become very common in our daily life.With the help of the powerful Internet,mobile payment avoids the risk of carrying a large amount of cash,and also eliminates the trouble of finding change and counterfeit money.It is faster and safer.This design is based on EDA technology,using Field Programmable Gate Array chip and Verilog HDL language to design the shopping payment system.The payment process is designed by finite state machine and modeled and programmed by Verilog HDL language.Compared with the design of commonly used single-chip computer,the FPGA is simpler and faster.
引文
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