DDR器件关键测试向量的设计
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摘要
双倍数据速率(Double Data Rate,DDR)DRAM由于其速度快、容量大,而且价格便宜,在各种需求大量数据缓存的场合得到了广泛使用。论文介绍了DDR器件的基本工作原理及需重点关注的操作过程,通过建立合适的时序关系,基于ATE设计测试向量,实现DDR器件的功能测试。
Compared with other memory technologies,DDR(Double Data Rate)has the faster processing speed,the larger storage potential and the more affordable price. And for those reasons,more and more major manufacturers are used on the way topurchase this storage memory. In this paper,the operating principle and using process of DDR DRAM(Dynamic Random AccessMemory)are recommended. After that,a test method about DDR DRAM is presented. This test technology focuses on the reason-able sequence,based on the ATE(Automatic Test Equipment)test vectors designing,and displays a useful,simple and universal test method.
Compared with other memory technologies,DDR(Double Data Rate)has the faster processing speed,the larger storage potential and the more affordable price. And for those reasons,more and more major manufacturers are used on the way topurchase this storage memory. In this paper,the operating principle and using process of DDR DRAM(Dynamic Random AccessMemory)are recommended. After that,a test method about DDR DRAM is presented. This test technology focuses on the reason-able sequence,based on the ATE(Automatic Test Equipment)test vectors designing,and displays a useful,simple and universal test method.
引文
[1] CC Chung,PL Chen,CY Lee. An All-Digital De-lay-Locked Loop for DDR SDRAM Controller Applications[J]. International Symposium on Vlsi Design,2006:1-4.
[2]T Kirihata,G Mueller,B Ji,G Frankowsky. A 390-mm 2,16-bank,1-Gb DDR SDRAM with hybrid bitline architec-ture[J].IEEE Journal of Solid-State Circuits,1999,34(11):1580-1588.
[3]Lu N. Advanced cell structures for dynamic RAMs[J].IEEECircuits and Devices Magazine Jan,1989:27-36.
[4] MICRON Double Data Rate(DDR)SDRAM MT46V32M16-8Meg*16*4 banks.
[5] Verigy Corporation. Verigy V93000 SOC Series TestingMemories[M]. Verigy Germany GmbH,Germany,April2007.
[6]DDR SDRAM JEDEC79R2,JEDEC Solid State Technolo-gy Association,2003.
[7]Goh Ban Hok. Heavy-Ion SEE Test Concept and Resultsfor DDR-II Memories[J]. IEEE Transactions on NuclearScience,2007,54(6).
[8] Changsik Yoo,etc. A 1.8-V 700-Mb/s/pin 512-MbDDR-II SDRAM With On-Die Termination and Off-ChipDriver Calibration[J]. IEEE Journal of Solid-State Cir-cuits,2004,39(6).
[9]Shuanghua Bai,David D.McLean,Jules Thibault. Impactof model structure on the performance of dynamic data rec-onciliation[J]. Computers&Chemical Engineering,2007,31(3):127-135.
[10]MJ Leibman,etc. Efficient data reconciliation and estima-tion for dynamic processes using nonlinear programming techniques[J]. Computers&Chemical Engineering,1992,16(10-11):963-986.
[11] JS Albuquerque,LT Biegler. Data reconciliation andgross-error detection for dynamic systems[J]. AicheJournal,1996,42(10):2841-2856.
[12]D MJ Bagajewicz. Design and retrofit of sensor networksin process plants[J]. Aiche Journal,1997,43(9):2300-2306.
[13]Kuge,S. etc. A 0.18-μm 256-Mb DDR-SDRAMwith low-cost post-mold tuning methodfor DLL replica[J]. IEEE Journal of Solid-State Circuits,2000,35(11).
[14]M Meyer,etc.Optimal selection of sensor location on acomplex plant, using a graph oriented approach[J].Computers&Chemical Engineering,1994,18(18):S535-S540.
[15]D Maquin,etc. Observability Analysis and Sensor Place-ment[J]. Ifac/imacs Symposium on Fault Detection,1994:13-15.
[2]T Kirihata,G Mueller,B Ji,G Frankowsky. A 390-mm 2,16-bank,1-Gb DDR SDRAM with hybrid bitline architec-ture[J].IEEE Journal of Solid-State Circuits,1999,34(11):1580-1588.
[3]Lu N. Advanced cell structures for dynamic RAMs[J].IEEECircuits and Devices Magazine Jan,1989:27-36.
[4] MICRON Double Data Rate(DDR)SDRAM MT46V32M16-8Meg*16*4 banks.
[5] Verigy Corporation. Verigy V93000 SOC Series TestingMemories[M]. Verigy Germany GmbH,Germany,April2007.
[6]DDR SDRAM JEDEC79R2,JEDEC Solid State Technolo-gy Association,2003.
[7]Goh Ban Hok. Heavy-Ion SEE Test Concept and Resultsfor DDR-II Memories[J]. IEEE Transactions on NuclearScience,2007,54(6).
[8] Changsik Yoo,etc. A 1.8-V 700-Mb/s/pin 512-MbDDR-II SDRAM With On-Die Termination and Off-ChipDriver Calibration[J]. IEEE Journal of Solid-State Cir-cuits,2004,39(6).
[9]Shuanghua Bai,David D.McLean,Jules Thibault. Impactof model structure on the performance of dynamic data rec-onciliation[J]. Computers&Chemical Engineering,2007,31(3):127-135.
[10]MJ Leibman,etc. Efficient data reconciliation and estima-tion for dynamic processes using nonlinear programming techniques[J]. Computers&Chemical Engineering,1992,16(10-11):963-986.
[11] JS Albuquerque,LT Biegler. Data reconciliation andgross-error detection for dynamic systems[J]. AicheJournal,1996,42(10):2841-2856.
[12]D MJ Bagajewicz. Design and retrofit of sensor networksin process plants[J]. Aiche Journal,1997,43(9):2300-2306.
[13]Kuge,S. etc. A 0.18-μm 256-Mb DDR-SDRAMwith low-cost post-mold tuning methodfor DLL replica[J]. IEEE Journal of Solid-State Circuits,2000,35(11).
[14]M Meyer,etc.Optimal selection of sensor location on acomplex plant, using a graph oriented approach[J].Computers&Chemical Engineering,1994,18(18):S535-S540.
[15]D Maquin,etc. Observability Analysis and Sensor Place-ment[J]. Ifac/imacs Symposium on Fault Detection,1994:13-15.