DRM/DAB/AM/FM频率综合器中吞吐脉冲分频器的设计
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摘要
为使DRM/DAB/AM/FM频率综合器具有良好性能,本文设计了一种高速大分频比低功耗吞吐脉冲分频器.此吞吐脉冲分频器由32/33双模预分频器(dual-modulus prescaler,DMP)、5位吞吐计数器和11位可编程分频器及时序控制电路构成.此吞吐脉冲分频器内部的不同模块分别采用SCL、TSPC、CMOS静态触发器及可置位的CMOS静态触发器等多种触发器结构优化,使此吞吐脉冲分频器具有高速、大分频比和低功耗的特点.此吞吐脉冲分频器应用中芯国际SMIC 0.18μm RF CMOS工艺流片,芯片核心面积为270μm×110μm.测试结果显示,在1.8 V工作电压的条件下,此吞吐脉冲分频器的最高工作频率为3.4 GHz,工作频率范围为0.9~3.4 GHz.在输入信号频率为3.4 GHz,分频比为45695时,功耗为3.2 mW.实验结果表明,此吞吐脉冲分频器完全满足DRM/DAB/AM/FM频率综合器的要求.
For the good performance of DRM / DAB / AM / FM frequency synthesizer,the implementation of a high-speed large division ratio low-power pulse swallow frequency divider is described,which consists of a divided-by-32 /33 dual-modulus prescaler( DMP),a 5 bits swallow counter,an 11-bits programmable divider,and a time sequence control circuit. The different modules of pulse swallow frequency divider apply SCL,TSPC,CMOS static flip-flop DFF,and CMOS static flip-flop DFF with preset to realize the low power, large division ratio,and high speed performances. The chip has been fabricated in a 0. 18 μm CMOS process of SMIC and the core area is 270 μm×110 μm. Measured results show that its most high operation frequency is 3. 4 GHz and the rang of operation frequency is from 0. 9 GHz to 3. 4 GHz. And when the operating frequency is 3. 4 GHz and division ratio is 45 695,the maximum core power consumption is 3. 2 mW under 1. 8 V power supply. Its performance satisfies the requirement of DRM / DAB / AM / FM frequency synthesizer.
For the good performance of DRM / DAB / AM / FM frequency synthesizer,the implementation of a high-speed large division ratio low-power pulse swallow frequency divider is described,which consists of a divided-by-32 /33 dual-modulus prescaler( DMP),a 5 bits swallow counter,an 11-bits programmable divider,and a time sequence control circuit. The different modules of pulse swallow frequency divider apply SCL,TSPC,CMOS static flip-flop DFF,and CMOS static flip-flop DFF with preset to realize the low power, large division ratio,and high speed performances. The chip has been fabricated in a 0. 18 μm CMOS process of SMIC and the core area is 270 μm×110 μm. Measured results show that its most high operation frequency is 3. 4 GHz and the rang of operation frequency is from 0. 9 GHz to 3. 4 GHz. And when the operating frequency is 3. 4 GHz and division ratio is 45 695,the maximum core power consumption is 3. 2 mW under 1. 8 V power supply. Its performance satisfies the requirement of DRM / DAB / AM / FM frequency synthesizer.
引文
[1]ETSI.ETSI ES 201 980.Digital Radio Mondiale(DRM);System Specnification[S].Nice:European Telecommunications Standards Institute,European Broadcasting Union,2005.
[2]ETSI.ETSI EN 300 401.Digital Audio Broadcasting(DAB)to Mobile,Portable and Fixed Receivers[S].Nice:European Telecommunications Standards Institute,European Broadcasting Union,2006.
[3]周建政.DRM/DAB/AM/FM接收机射频前端芯片设计中的关键技术研究[D].南京:东南大学,2009.
[4]周建政,王志功,李莉,等.DRM接收机射频前端芯片的频率规划设计[J].高技术通讯,2008,18(5):480-486.
[5]LIN C S,CHIEN T H,WEY C L.A 5.5-GHz 1-mW full-Modulus-range programmable frequency divider in90-nm CMOS process[J].IEEE Transactions on Circuits and Systems-II:Express Briefs,2011,58(9):550-554.
[6]CRANINCKX J,STEYAERT M.A 1.75 GHz 3 V dual modulus divider by 128/129 prescaler in 0.7μm CMOS[J].IEEE Journal of Solid-State Circuits,1996,31(7):890-897.
[7]YIU Xiaopeng,ZHOU Jianjun,YAN Xiaolang,et al.Sub-mW multi-GHz CMOS dual-modulus prescalers based on programmable injection-locked frequency dividers[C]//IEEE Radio Frequency Integrated Circuits Symposium,2008.Atlanta,GA,2008:431-434.
[8]XU Yong,WANG Zhigong,LI Zhiqun,et al.A novel high-speed lower-jitter lower-power dissipation dualmodulus prescaler and applications in PLL frequency synthesizer[J].Chinese Journal of Semiconductors,2005,26(1):176-179.
[9]LI Zhiqiang,CHEN Liqiang,ZHANG Jian,et al.A programmable 2.4 GHz CMOS multi-modulus frequency divider[J].Chinese Journal of Semiconductors,2008,29(2):521-526.
[10]SHU K,SCHEZ-SINENCIO E,SILVA-MARTNEZ,et al.A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier[J].IEEE Journal of SolidState Circuits,2003,38(6):866-974.
[11]CHI Baoyong,SHI Bingxue.A novel CMOS dualmodulus prescaler based on new optimized structure and synamic circuit technique[J].Chinese Journal of Semiconductors,2002,23(4):357-361.
[12]HUANG Qiuting,ROGENMOSER R.Speed optimization of edge-triggered CMOS circuits for gigahertz singlephase clocks[J].IEEE Journal of Solid-State Circuits,1996,31(3):456-465.
[13]de MIRANDA F P H,Jr Navarro S J,Van NOIJE W A M.A 4 GHz dual modulus divider-by 32/33 prescaler in0.35 pm CMOS technology[C]//17th Symposium on Integrated Circuits and Systems Design,2004.Pemanbuca,Brazil:[s.n.],94-99.
[14]XU Yong,WANG Zhigong,LI Zhiqun,et al.A novel high-speed lower-jitter lower-power dissipation dualmodulus prescaler and applications in PLL frequency synthesizer[J].Chinese Journal of Semiconductors,2005,26(1):176-179.
[15]GAO Haijun,SUN Lingling,LIU Jun.Pulse swallow frequency divider with idle DFFs automatically powered off[J].Electronics Letters,2012,48(11):636-638.
[16]YU Lu,FAN Xiangning,LI Bin.A 4-6 GHz low-voltage CMOS integer-M frequency divider applied in wireless sensor networks[C]//IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.Xi'an:[s.n.],2012:1-3.
[17]PAN Jie,YANG Haigang,YANG Liwu.A high-speed low-power pulse-swallow divider with robustness consideration[C]//9th International Conference on Solid-State and Integrated-Circuit Technology.Beijing:[s.n.],2008:2168-2171.
[2]ETSI.ETSI EN 300 401.Digital Audio Broadcasting(DAB)to Mobile,Portable and Fixed Receivers[S].Nice:European Telecommunications Standards Institute,European Broadcasting Union,2006.
[3]周建政.DRM/DAB/AM/FM接收机射频前端芯片设计中的关键技术研究[D].南京:东南大学,2009.
[4]周建政,王志功,李莉,等.DRM接收机射频前端芯片的频率规划设计[J].高技术通讯,2008,18(5):480-486.
[5]LIN C S,CHIEN T H,WEY C L.A 5.5-GHz 1-mW full-Modulus-range programmable frequency divider in90-nm CMOS process[J].IEEE Transactions on Circuits and Systems-II:Express Briefs,2011,58(9):550-554.
[6]CRANINCKX J,STEYAERT M.A 1.75 GHz 3 V dual modulus divider by 128/129 prescaler in 0.7μm CMOS[J].IEEE Journal of Solid-State Circuits,1996,31(7):890-897.
[7]YIU Xiaopeng,ZHOU Jianjun,YAN Xiaolang,et al.Sub-mW multi-GHz CMOS dual-modulus prescalers based on programmable injection-locked frequency dividers[C]//IEEE Radio Frequency Integrated Circuits Symposium,2008.Atlanta,GA,2008:431-434.
[8]XU Yong,WANG Zhigong,LI Zhiqun,et al.A novel high-speed lower-jitter lower-power dissipation dualmodulus prescaler and applications in PLL frequency synthesizer[J].Chinese Journal of Semiconductors,2005,26(1):176-179.
[9]LI Zhiqiang,CHEN Liqiang,ZHANG Jian,et al.A programmable 2.4 GHz CMOS multi-modulus frequency divider[J].Chinese Journal of Semiconductors,2008,29(2):521-526.
[10]SHU K,SCHEZ-SINENCIO E,SILVA-MARTNEZ,et al.A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier[J].IEEE Journal of SolidState Circuits,2003,38(6):866-974.
[11]CHI Baoyong,SHI Bingxue.A novel CMOS dualmodulus prescaler based on new optimized structure and synamic circuit technique[J].Chinese Journal of Semiconductors,2002,23(4):357-361.
[12]HUANG Qiuting,ROGENMOSER R.Speed optimization of edge-triggered CMOS circuits for gigahertz singlephase clocks[J].IEEE Journal of Solid-State Circuits,1996,31(3):456-465.
[13]de MIRANDA F P H,Jr Navarro S J,Van NOIJE W A M.A 4 GHz dual modulus divider-by 32/33 prescaler in0.35 pm CMOS technology[C]//17th Symposium on Integrated Circuits and Systems Design,2004.Pemanbuca,Brazil:[s.n.],94-99.
[14]XU Yong,WANG Zhigong,LI Zhiqun,et al.A novel high-speed lower-jitter lower-power dissipation dualmodulus prescaler and applications in PLL frequency synthesizer[J].Chinese Journal of Semiconductors,2005,26(1):176-179.
[15]GAO Haijun,SUN Lingling,LIU Jun.Pulse swallow frequency divider with idle DFFs automatically powered off[J].Electronics Letters,2012,48(11):636-638.
[16]YU Lu,FAN Xiangning,LI Bin.A 4-6 GHz low-voltage CMOS integer-M frequency divider applied in wireless sensor networks[C]//IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.Xi'an:[s.n.],2012:1-3.
[17]PAN Jie,YANG Haigang,YANG Liwu.A high-speed low-power pulse-swallow divider with robustness consideration[C]//9th International Conference on Solid-State and Integrated-Circuit Technology.Beijing:[s.n.],2008:2168-2171.