40GBASE-KR4传输通道仿真与背板设计优化
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摘要
随着云计算和大数据的应用普及,人们对数据中心的容量和交换速率提出了越来越高的要求。高速背板作为搭建高性能数据平台的关键部件,其设计面临最大的挑战在于传输通道信号速率高达10.312 5 Gb/s,穿越至少两组连接器以及最长40 inch的有损传输线。通过HFSS进行单元建模与参数提取,ADS进行通道整体建模,采用协同仿真方法,预测通道损耗指标与眼图波形。根据仿真结果指导关键器件选型、设计优化、预(去)加重与均衡参数设置,成功实现基于40GBASE-KR4规范的高速传输通道设计。
With the application and popularization of cloud computing and big data, higher and higher demands for the data-center capacity and exchange rate. High-speed backplane is key component for building up high-performance data platform, the biggest challenge faced by its to design lies in the channel with signal rate of up to 10.312 5 Gb/s, passing through at least two sets of connectors and of up to 40 inches lossy transmission-line. By modeling 3D model and extracting block parameters with software HFSS, the overall transmission channel model is built up in Agilent ADS, and the loss performances and eye waveform predicted by coordinated simulation. Simulation results give guidance to the key device selection, design optimization, pre-(de-) weighting and equalization parameter setting-up, and thus the high-speed transmission channel design based on 40GBASE-KR4 specification is successfully implemented.
With the application and popularization of cloud computing and big data, higher and higher demands for the data-center capacity and exchange rate. High-speed backplane is key component for building up high-performance data platform, the biggest challenge faced by its to design lies in the channel with signal rate of up to 10.312 5 Gb/s, passing through at least two sets of connectors and of up to 40 inches lossy transmission-line. By modeling 3D model and extracting block parameters with software HFSS, the overall transmission channel model is built up in Agilent ADS, and the loss performances and eye waveform predicted by coordinated simulation. Simulation results give guidance to the key device selection, design optimization, pre-(de-) weighting and equalization parameter setting-up, and thus the high-speed transmission channel design based on 40GBASE-KR4 specification is successfully implemented.
引文
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[2]郑浩,金利峰.高速串行背板10Gbps信号传输性能仿真和分析[J].计算机工程与科学,2011,33(10):70-75.ZHENG Hao,JIN Li-feng.Simulation and Analysis of 10Gbps Signal Transmission on the Serial-Link Backplane[J].Computer Engineering&Science,2011,33(10):70-75.
[3]Eric Bogatin.信号完整性分析[M].李玉山,李丽平,译.北京:电子工业出版社,2005:198-208.Eric Bogatin.Signal Integrity:Simplified[M].LI Yu-shan,LI Li-ping,Translation.Beijing:Publishing House of Electronics Industry,2005:198-208.
[4]李彦,吴培明,寇小明.高速串行Rapid IO总线背板信号完整性仿真研究[J].鱼雷技术,2011,19(03):167-171.LI Yan,WU Pei-ming,KOU Xiao-ming.Signal Integrity of High Speed Serial Rapid IO Bus Backboard[J].Torpedo Technology,2011,19(03):167-171.
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