一种IBIS模型建模方法
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摘要
在芯片设计时,我们经常通过HSIPCE仿真来完成验证开发工作。HSIPCE模型是晶体管级模型,在系统级信号完整性仿真应用中有很大的局限性:仿真耗时长,易泄露产品秘密,不利于知识产权保护。当前,在系统级信号完整性仿真中,IBIS模型被广泛使用,能被主流的软件接受并应用于仿真工作。因此,我们需进行器件的IBIS模型建模,并将IBIS模型提供给用户。本文主要介绍IBIS模型及模型的创建方法与模型的验证。
As a rule, HSIPCE emulator is always used to do validation in the IC's design. The HSIPCE model is a transistor level model, which has limitations on the system level simulation: long time simulating consumption, easy to reveal the product's privacy and unfriendly to protect the intellectual property rights. The IBIS model is widely used at the currently system level simulation analysis, it can be adopted by the mainstream of simulation software. As a result, we must prepare the IBIS model, and provide it to our user. This article introduces the IBIS model and the method to build and validate this model.
As a rule, HSIPCE emulator is always used to do validation in the IC's design. The HSIPCE model is a transistor level model, which has limitations on the system level simulation: long time simulating consumption, easy to reveal the product's privacy and unfriendly to protect the intellectual property rights. The IBIS model is widely used at the currently system level simulation analysis, it can be adopted by the mainstream of simulation software. As a result, we must prepare the IBIS model, and provide it to our user. This article introduces the IBIS model and the method to build and validate this model.
引文
[1]Lin Jun.《教你如何建IBIS模型》V2.0,2006.
[2]Cadence.T2B File Format Reference Guide,Version 16.6,June17,2013.
[3]Cadence.T2B Quick Reference,Version 16.6,June 28,2013.
[4]Cadence.T2B Tutorial for HSPICE Models,Version 16.6,July 10,2013.
[5]侯建平,张家训,何凯.一种封装管壳快速建模方法[J].电脑与电信,2017(6):34-36.
[2]Cadence.T2B File Format Reference Guide,Version 16.6,June17,2013.
[3]Cadence.T2B Quick Reference,Version 16.6,June 28,2013.
[4]Cadence.T2B Tutorial for HSPICE Models,Version 16.6,July 10,2013.
[5]侯建平,张家训,何凯.一种封装管壳快速建模方法[J].电脑与电信,2017(6):34-36.