28 nm PMOSFET器件短沟道效应机理研究与优化
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摘要
随着MOSFET器件尺寸不断缩小,短沟道效应越来越严重。基于28 nm低功耗逻辑平台,针对PMOSFET器件短沟道效应严重的现象,借助半导体工艺及器件仿真工具TCAD,研究PMOSFET短沟道效应的产生机制。提出一种通过调整pocket离子注入工艺条件改善短沟道效应的方法。通过优化工艺条件,该方法可以在保证长沟道器件Vt不变的情况下,有效改善28 nm PMOSFET器件的短沟道效应。
With MOSFET dimension scaling down, short channel effect(SCE) is becoming more and more severe.Based on 28 nm low power logic platform, this work firstly investigated the mechanism of PMOSFET SCE by using TCAD simulation, and then proposed an optimization method by modifying the pocket implant condition.This optimization method could improve PMOSFET SCE effectively, and keep long channel device Vt constant.
With MOSFET dimension scaling down, short channel effect(SCE) is becoming more and more severe.Based on 28 nm low power logic platform, this work firstly investigated the mechanism of PMOSFET SCE by using TCAD simulation, and then proposed an optimization method by modifying the pocket implant condition.This optimization method could improve PMOSFET SCE effectively, and keep long channel device Vt constant.
引文
[1] A.Hori,B.Mizuno.CMOS Device Technology toward 50 nm Region Performance and Drain Architecture[J]. International Electron Devices Meeting,1999:641-644.
[2] K.Roy,S.Mukhopadhyay,H.MAHMOODI-MEIMAND,et al.Leakage current mechanisms and leakager eduction techniques in deep-sub micrometer CMOS circuits[J]. PROCEEDINGS OF THE IEEE,2003,91(2):305-327.
[3] Q.Xie,J.XU,Y.Taur.Review and critique of analytic models of MOSFET hortchannel effects in subthreshold[J].IEEE TRANSACTIONS ON ELECTRON DEVICES,2012:1569-1579.
[4] B.El-Kareh.Silicon Devices and Process Integration[M].Springer Science+Business Media,LLC,2009.
[5] S.Wolf.Silicon processing for the VLSI era, volume 3:the submicron MOSFET[M].California,USA:Lattice Press, 1995.
[6] Y.Taur,T.H.NING.Fundamentals of Modern VLSI Devices,2nd edition[M].Cambridge,UK:Cambridge University Press,2009.
[7] F.H.Gaensslen.Geometry effects of small MOSFET devices[J]. IBM J.Res.Dev., 1979,23(6):682-688.
[8] D.J.Frank,R.H.Dennard,E.Nowak, et al.Device scaling limits of Si MOSFETs and their application dependencies[J].PROCEEDINGS OF THE IEEE,2001,89(3):258-288.
[9] T. N. Nguyen. Small-geometry MOS transistors:Physics and modeling of surface and buried-channel MOSFETS[D].Stanford, CA:Ph.D.dissertation,Stanford Univ., 1984.
[10] C.C.HU. Scal ing CMOS Devices Through Alternative Structures[J]. Science in China(Series F), 2001,44(1):1-7:
[11] C.C.HU.Modern Semiconductor Devices for Integrated Circuits[M].China:China Science Publishing&Media LTD,2012.
[12] T.Hori.A 0.1-μm CMOS technology with tilt-implanted punch through stopper(TIPS)[J].IEEE IEDM Tech.Dig., 1994:75.
[13] H.CHEN,J.ZHAO,C.S. Teng,et al.Submicron large-angle-tilt implanted drain technology for mixed-signal applications[J].IEEE IEDM Tech.Dig.,1994:91.
[2] K.Roy,S.Mukhopadhyay,H.MAHMOODI-MEIMAND,et al.Leakage current mechanisms and leakager eduction techniques in deep-sub micrometer CMOS circuits[J]. PROCEEDINGS OF THE IEEE,2003,91(2):305-327.
[3] Q.Xie,J.XU,Y.Taur.Review and critique of analytic models of MOSFET hortchannel effects in subthreshold[J].IEEE TRANSACTIONS ON ELECTRON DEVICES,2012:1569-1579.
[4] B.El-Kareh.Silicon Devices and Process Integration[M].Springer Science+Business Media,LLC,2009.
[5] S.Wolf.Silicon processing for the VLSI era, volume 3:the submicron MOSFET[M].California,USA:Lattice Press, 1995.
[6] Y.Taur,T.H.NING.Fundamentals of Modern VLSI Devices,2nd edition[M].Cambridge,UK:Cambridge University Press,2009.
[7] F.H.Gaensslen.Geometry effects of small MOSFET devices[J]. IBM J.Res.Dev., 1979,23(6):682-688.
[8] D.J.Frank,R.H.Dennard,E.Nowak, et al.Device scaling limits of Si MOSFETs and their application dependencies[J].PROCEEDINGS OF THE IEEE,2001,89(3):258-288.
[9] T. N. Nguyen. Small-geometry MOS transistors:Physics and modeling of surface and buried-channel MOSFETS[D].Stanford, CA:Ph.D.dissertation,Stanford Univ., 1984.
[10] C.C.HU. Scal ing CMOS Devices Through Alternative Structures[J]. Science in China(Series F), 2001,44(1):1-7:
[11] C.C.HU.Modern Semiconductor Devices for Integrated Circuits[M].China:China Science Publishing&Media LTD,2012.
[12] T.Hori.A 0.1-μm CMOS technology with tilt-implanted punch through stopper(TIPS)[J].IEEE IEDM Tech.Dig., 1994:75.
[13] H.CHEN,J.ZHAO,C.S. Teng,et al.Submicron large-angle-tilt implanted drain technology for mixed-signal applications[J].IEEE IEDM Tech.Dig.,1994:91.