基于PCIe2.0协议的PCS层弹性缓冲器设计
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摘要
弹性缓冲器能够补偿时钟偏差,解决了不同时钟域下的数据传输问题,被广泛应用于高速数据流通信中.结合PCIe 2.0协议,采用常半满方式对弹性缓冲器进行了设计.在读写指针的对比过程中,相对于传统的同步指针的实现方法,采用常半满的检查方式和半满同步方法,简化了逻辑结构.并且在充分考虑协议的基础上,不仅实现了时钟补偿的功能,而且能很好地与接收端的其他模块完成接口对接.经modelsim仿真验证,所设计的缓冲器支持250 MHz的读写时钟频率,输入输出数据为20bit,适用于5G全速率(250 MHz)和2.5G半速率(125 MHz)两种模式.
Elastic buffer can compensate the clock deviation to solve the problem of data transmission under different clock domains,so it is widely used in high speed communication system.Based on PCIe 2.0protocol,this paper designs an Elastic buffer with normal half-full method.Comparing with the traditional method to synchronize the pointer,it checks the reading pointer when the writing pointer is on the half position in elastic buffer.Thus,it simplified the logical structure.In addition,it not only compensate the clock deviation,but also connect with interfaces of other module compatibly at the receiver of PCS.After verifying on modelsim,the writing and reading clock can achieve 250 MHz,the width of input and output data is 20 bit.So it can support two modes,5GT/s(fullrate)and 2.5GT/s(half-rate).
Elastic buffer can compensate the clock deviation to solve the problem of data transmission under different clock domains,so it is widely used in high speed communication system.Based on PCIe 2.0protocol,this paper designs an Elastic buffer with normal half-full method.Comparing with the traditional method to synchronize the pointer,it checks the reading pointer when the writing pointer is on the half position in elastic buffer.Thus,it simplified the logical structure.In addition,it not only compensate the clock deviation,but also connect with interfaces of other module compatibly at the receiver of PCS.After verifying on modelsim,the writing and reading clock can achieve 250 MHz,the width of input and output data is 20 bit.So it can support two modes,5GT/s(fullrate)and 2.5GT/s(half-rate).
引文
[1]PCI-SIG.PCI Express 2.0Base Specification Revision0.9.[EB/OL].[2015-11-20].www.pci-sig.com,2011.
[2]朱小明,王小利,程曾.USB3.0物理层中弹性缓冲的设计与实现[J].微电子学与计算机,2012,29(6):117-118.
[3]Cummings CE.Simulation and synthesis techniques for asynchronous FIFO design[R].SNUG,2002.
[4]Joe Winkles.Elastic Buffer Implementations in PCI Express Devices[M].US:MindShare Inc,2003.
[5]Intel Corporation.PHY Interface for the PCI Express Architecture Version 2.0[P].2007.
[2]朱小明,王小利,程曾.USB3.0物理层中弹性缓冲的设计与实现[J].微电子学与计算机,2012,29(6):117-118.
[3]Cummings CE.Simulation and synthesis techniques for asynchronous FIFO design[R].SNUG,2002.
[4]Joe Winkles.Elastic Buffer Implementations in PCI Express Devices[M].US:MindShare Inc,2003.
[5]Intel Corporation.PHY Interface for the PCI Express Architecture Version 2.0[P].2007.