基于FPGA的Systolic乘法技术研究
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摘要
Systolic乘法是一种基于SIMD-MC2模型的矩阵乘算法,无法直接应用在单独的嵌入式系统中,所以提出一种采用FPGA技术实现Systolic乘法的方法。该方法将FPGA的硬件并行特性与巧妙的并行算法结合起来,利用FPGA灵活可编程的特点,在FPGA内部设计了一种基于MC2模型的节点阵列来实现Systolic乘法。实际应用中,可以灵活地修改节点单元的数量和节点的功能来满足不同规模的运算矩阵需求并充分利用FPGA的资源。仿真结果验证了该方法的正确性。实际测试结果表明:该方法具有较快的速度和较高的实时性。
Systolic multiplication is an algorithm based on the SIMD-MC2 model,but it cannot be applied in the embedded system directly.We propose an implementation of Systolic multiplication by FPGA technology,which combines the hardware parallelism of the FPGA and the parallel algorithm together.To realize Systolic multiplication,we design a node array based on the MC2 model inside the FPGA by making use of the flexible and programmable features of the FPGA.In practical applications,the number and function of the nodes can be modified flexibly to meet the needs of different scale matrixes and the FPGA resources are fully utilized.Simulation results verify the proposed method,and the actual test results show that this method has a faster speed and a higher real-time performance.
Systolic multiplication is an algorithm based on the SIMD-MC2 model,but it cannot be applied in the embedded system directly.We propose an implementation of Systolic multiplication by FPGA technology,which combines the hardware parallelism of the FPGA and the parallel algorithm together.To realize Systolic multiplication,we design a node array based on the MC2 model inside the FPGA by making use of the flexible and programmable features of the FPGA.In practical applications,the number and function of the nodes can be modified flexibly to meet the needs of different scale matrixes and the FPGA resources are fully utilized.Simulation results verify the proposed method,and the actual test results show that this method has a faster speed and a higher real-time performance.
引文
[1] Dekel E,Nassimi D,Sahni S.Parallel matrix and graph algorithms[J].SIAM Journal on Computing,1981,10(4):657-675.
[2] Chen Guo-liang.Parallel computing:Architecture,algorithm,programming[M].3rd Edition.Beijing:Higher Education Press,2009.(in Chinese)
[3] Chen Guo-Liang.Design and analysis of parallel algorithms[M].3rd Edition.Beijing:Higher Education Press,2009.(in Chinese)
[4] Karra M C,Bekakos M P,Milovanovic I Z,et al.FPGA implementation of a unidirectional Systolic array generator for matrix-vector multiplication[C]∥IEEE International Conference on Signal Processing and Communications,2007:1.
[5] Horita T,Takanami I.An FPGA-based fault-tolerant 2DSystolic array for matrix multiplications[M]∥Transactions on Computational Science,2011:108-124.
[6] Sonawane D N,Sutaone M S,Malek I.Systolic architecture for integer point matrix multiplication using FPGA[C]∥Proc of the 4th IEEE Conference on Industrial Electronics and Applications,2009:3822-3825.
[7] Vucha M,Rajawat A.Design and FPGA implementation of Systolic array architecture for matrix multiplication[J].International Journal of Computer Applications,2011,26(3):18-22.
[8] Kung H T.Why Systolic architectures[J].IEEE Computer,1982,15(1):37-46.
[9] Zheng Fei,Xie Kang-lin.Systolic array and the algebraic specification of the Global view[J].Computer Engineering and Science,1992,4(3):25-32.(in chinese)
[10] Guerra C,Melhem R G.Synthesis of Systolic algorithm design[J].Parallel Computing,1989,12(2):155-207.
[11] Wan C R,Evans D J.Nineteen ways of Systolic matrix multiplication[J].International Journal of Computer Mathematics,1998,68(1-2):1-2.
[2] 陈国良.并行计算——结构·算法·编程(·第三版·)[M].北京:高等教育出版社,2009.
[3] 陈国良.并行算法的设计与分析(·第三版·)[M].北京:高等教育出版社,2009.
[9] 郑飞,谢康林.Systolic阵列及其全局视图的代数描述[J].计算机工程与科学,1992,14(3):25-32.
[2] Chen Guo-liang.Parallel computing:Architecture,algorithm,programming[M].3rd Edition.Beijing:Higher Education Press,2009.(in Chinese)
[3] Chen Guo-Liang.Design and analysis of parallel algorithms[M].3rd Edition.Beijing:Higher Education Press,2009.(in Chinese)
[4] Karra M C,Bekakos M P,Milovanovic I Z,et al.FPGA implementation of a unidirectional Systolic array generator for matrix-vector multiplication[C]∥IEEE International Conference on Signal Processing and Communications,2007:1.
[5] Horita T,Takanami I.An FPGA-based fault-tolerant 2DSystolic array for matrix multiplications[M]∥Transactions on Computational Science,2011:108-124.
[6] Sonawane D N,Sutaone M S,Malek I.Systolic architecture for integer point matrix multiplication using FPGA[C]∥Proc of the 4th IEEE Conference on Industrial Electronics and Applications,2009:3822-3825.
[7] Vucha M,Rajawat A.Design and FPGA implementation of Systolic array architecture for matrix multiplication[J].International Journal of Computer Applications,2011,26(3):18-22.
[8] Kung H T.Why Systolic architectures[J].IEEE Computer,1982,15(1):37-46.
[9] Zheng Fei,Xie Kang-lin.Systolic array and the algebraic specification of the Global view[J].Computer Engineering and Science,1992,4(3):25-32.(in chinese)
[10] Guerra C,Melhem R G.Synthesis of Systolic algorithm design[J].Parallel Computing,1989,12(2):155-207.
[11] Wan C R,Evans D J.Nineteen ways of Systolic matrix multiplication[J].International Journal of Computer Mathematics,1998,68(1-2):1-2.
[2] 陈国良.并行计算——结构·算法·编程(·第三版·)[M].北京:高等教育出版社,2009.
[3] 陈国良.并行算法的设计与分析(·第三版·)[M].北京:高等教育出版社,2009.
[9] 郑飞,谢康林.Systolic阵列及其全局视图的代数描述[J].计算机工程与科学,1992,14(3):25-32.