三维TSV集成电路电磁敏感性分析方法
|
摘要
研究了三维集成电路(3D ICs)中硅通孔(TSV)的建模方法及三维集成电路电源分配网络(PDN)的建模方法,并结合印制电路板(PCB)的电源分布网络和芯片PDN模型,提出了一种对板级三维集成电路进行电源网络上电磁敏感性(EMS)的建模和协同分析方法。首先给出了地-信号(GS)结构和地-信号1-信号2-地(GSSG)结构TSV的电路模型,电路模型与数值仿真结果做了对比,验证了TSV电路建模方法的准确性。接着对PCB板级三维集成电路中PCB的电源分布网络,PCB过孔,集成电路封装参数进行建模。最后创建了一个PCB-三维集成电路电磁敏感性级联分析模型,使用该模型来研究三维集成电路对电源干扰的敏感特性,并由此指导三维集成电路的敏感性分析。
This paper focuses on the circuit modeling method of through silicon via( TSV) and power distribution network( PDN) in 3 D integrated circuits( 3 D ICs). Combined with the PDN on printed circuit board( PCB) and the chip PDN model,an electromagnetic susceptibility( EMS) modeling and collaborative analysis method for 3 D ICs on PCB was proposed. Firstly,a ground-signal( GS) TSV pair and two TSV pairs of ground-signal1-signal2-ground( GSSG) were established in,and these circuit models were compared with the numerical simulation results,which validated the accuracy of the circuit modeling method of TSV. Then,the modeling method of PDN of PCB,PCB through via hole,IC's package parameters in an IC were discussed.Finally,an EMS cascade connection analysis model from PCB to 3 D ICs was developed and used to analyze the electromagnetic susceptibility characteristics of 3 D ICs to power interference,which can guide the susceptibility analysis of 3 D ICs.
This paper focuses on the circuit modeling method of through silicon via( TSV) and power distribution network( PDN) in 3 D integrated circuits( 3 D ICs). Combined with the PDN on printed circuit board( PCB) and the chip PDN model,an electromagnetic susceptibility( EMS) modeling and collaborative analysis method for 3 D ICs on PCB was proposed. Firstly,a ground-signal( GS) TSV pair and two TSV pairs of ground-signal1-signal2-ground( GSSG) were established in,and these circuit models were compared with the numerical simulation results,which validated the accuracy of the circuit modeling method of TSV. Then,the modeling method of PDN of PCB,PCB through via hole,IC's package parameters in an IC were discussed.Finally,an EMS cascade connection analysis model from PCB to 3 D ICs was developed and used to analyze the electromagnetic susceptibility characteristics of 3 D ICs to power interference,which can guide the susceptibility analysis of 3 D ICs.
引文
[1]KNICKERBOCKER J U,ANDRY P S,DANG B,et al.3D silicon integration[C]∥2008 58th Electronic Components and Technology Conference.Piscataway,NJ:IEEE Press,2008:538-543.
[2]CADIX L,FARCY A,BERMOND C,et al.Modelling of through silicon via RF performance and impact on signal transmission in3D integrated circuits[C]∥IEEE International Conference on3D System Integration,2009.Piscataway,NJ:IEEE Press,2009:1-7.
[3]ZHU Y,MA S,SUN X,et al.Developssment and characterization of a through-multilayer TSV integrated SRAM module[C]∥2013 IEEE 63rd Electronic Components and Technology Conference.Piscataway,NJ:IEEE Press,2013:885-890.
[4]KIM J S,OH C S,LEE H,et al.A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking[C]∥2011 IEEE International Solid-State Circuits Conference.Piscataway,NJ:IEEE Press,2011:496-498.
[5]YOON K,KIM G,LEE W,et al.Modeling and analysis of coupling between TSVs,metal,and RDL interconnects in TSV-based 3D IC with silicon interposer[C]∥Electronics Packaging Technology Conference,2009.Piscataway,NJ:IEEE Press,2009:702-706.
[6]HAN K J,SWAMINATHAN M,JEONG J.Modeling of throughsilicon via(TSV)interposer considering depletion capacitance and substrate layer thickness effects[J].IEEE Transactions on Components,Packaging and Manufacturing Technology,2015,5(1):108-118.
[7]NDIP I,ZOSCHKE K,LBICKE K,et al.Analytical,numerical-,and measurement-based nethods for extracting the electrical parameters of through silicon vias(TSVs)[J].IEEE Transactions on Components,Packaging and Manufacturing Technology,2014,4(3):504-515.
[8]XU Z,BEECE A,ZHANG D,et al.Characterization and modeling of solder balls and through-strata-vias(TSVs)in 3D architecture[C]∥19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.Piscataway,NJ:IEEE Press,2010:37-40.
[9]CHO J,SHIM J,SONG E,et al.Active circuit to through silicon via(TSV)noise coupling[C]∥2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.Piscataway,NJ:IEEE Press,2009:97-100.
[10]SONG T,LIU C,KIM D,et al.Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs[C]∥2011 12th International Symposium on Quality Electronic Design(ISQED).Piscataway,NJ:IEEE Press,2011:1-7.
[11]XIE B,SWAMINATHAN M,HAN K J,et al.Coupling analysis of through-silicon via(TSV)arrays in silicon interposers for 3Dsystems[C]∥2011 IEEE International Symposium on Electromagnetic Compatibility(EMC).Piscataway,NJ:IEEE Press,2011:16-21.
[12]CURRAN B,NDIP I,GUTTOVSKI S,et al.The impacts of dimensions and return current path geometry on coupling in single ended through silicon vias[C]∥2009 59th Electronic Components and Technology Conference.Piscataway,NJ:IEEE Press,2009:1092-1097.
[13]CHO J,SONG E,YOON K,et al.Modeling and analysis of through-silicon via(TSV)noise coupling and suppression using a guard ring[J].IEEE Transactions on Components,Packaging and Manufacturing Technology,2011,1(2):220-233.
[14]XU Z,BEECE A,ZHANG D,et al.Crosstalk evaluation,suppression and modeling in 3D through-strata-via(TSV)network[C]∥IEEE International 3D Systems Integration Conference(3DIC).Piscataway,NJ:IEEE Press,2010:1-8.
[15]CHIANG C H,KUO L M,HU Y C,et al.Sealing bump with bottom-up Cu TSV plating fabrication in 3-D integration scheme[J].IEEE Electron Device Letters,2013,34(5):671-673.
[2]CADIX L,FARCY A,BERMOND C,et al.Modelling of through silicon via RF performance and impact on signal transmission in3D integrated circuits[C]∥IEEE International Conference on3D System Integration,2009.Piscataway,NJ:IEEE Press,2009:1-7.
[3]ZHU Y,MA S,SUN X,et al.Developssment and characterization of a through-multilayer TSV integrated SRAM module[C]∥2013 IEEE 63rd Electronic Components and Technology Conference.Piscataway,NJ:IEEE Press,2013:885-890.
[4]KIM J S,OH C S,LEE H,et al.A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking[C]∥2011 IEEE International Solid-State Circuits Conference.Piscataway,NJ:IEEE Press,2011:496-498.
[5]YOON K,KIM G,LEE W,et al.Modeling and analysis of coupling between TSVs,metal,and RDL interconnects in TSV-based 3D IC with silicon interposer[C]∥Electronics Packaging Technology Conference,2009.Piscataway,NJ:IEEE Press,2009:702-706.
[6]HAN K J,SWAMINATHAN M,JEONG J.Modeling of throughsilicon via(TSV)interposer considering depletion capacitance and substrate layer thickness effects[J].IEEE Transactions on Components,Packaging and Manufacturing Technology,2015,5(1):108-118.
[7]NDIP I,ZOSCHKE K,LBICKE K,et al.Analytical,numerical-,and measurement-based nethods for extracting the electrical parameters of through silicon vias(TSVs)[J].IEEE Transactions on Components,Packaging and Manufacturing Technology,2014,4(3):504-515.
[8]XU Z,BEECE A,ZHANG D,et al.Characterization and modeling of solder balls and through-strata-vias(TSVs)in 3D architecture[C]∥19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.Piscataway,NJ:IEEE Press,2010:37-40.
[9]CHO J,SHIM J,SONG E,et al.Active circuit to through silicon via(TSV)noise coupling[C]∥2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.Piscataway,NJ:IEEE Press,2009:97-100.
[10]SONG T,LIU C,KIM D,et al.Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs[C]∥2011 12th International Symposium on Quality Electronic Design(ISQED).Piscataway,NJ:IEEE Press,2011:1-7.
[11]XIE B,SWAMINATHAN M,HAN K J,et al.Coupling analysis of through-silicon via(TSV)arrays in silicon interposers for 3Dsystems[C]∥2011 IEEE International Symposium on Electromagnetic Compatibility(EMC).Piscataway,NJ:IEEE Press,2011:16-21.
[12]CURRAN B,NDIP I,GUTTOVSKI S,et al.The impacts of dimensions and return current path geometry on coupling in single ended through silicon vias[C]∥2009 59th Electronic Components and Technology Conference.Piscataway,NJ:IEEE Press,2009:1092-1097.
[13]CHO J,SONG E,YOON K,et al.Modeling and analysis of through-silicon via(TSV)noise coupling and suppression using a guard ring[J].IEEE Transactions on Components,Packaging and Manufacturing Technology,2011,1(2):220-233.
[14]XU Z,BEECE A,ZHANG D,et al.Crosstalk evaluation,suppression and modeling in 3D through-strata-via(TSV)network[C]∥IEEE International 3D Systems Integration Conference(3DIC).Piscataway,NJ:IEEE Press,2010:1-8.
[15]CHIANG C H,KUO L M,HU Y C,et al.Sealing bump with bottom-up Cu TSV plating fabrication in 3-D integration scheme[J].IEEE Electron Device Letters,2013,34(5):671-673.