一种长周期和大倍频系数条件下的数字锁相环
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摘要
遥感设备需要配备高精度的本地时钟源与卫星平台时钟同步,数字锁相环设计是时钟同步和倍频的关键技术,而长周期输入信号和大倍频系数从两方面增加了设计难度。设计了一种针对秒脉冲同步和10000倍倍频条件下的数字锁相环,通过建立Z域模型和S域近似分析了其响应特性,用现场可编程门阵列予以实现.实验表明,本设计实现的数字锁相环最短可以在5个输入时钟周期内进入锁定状态,稳定工作时每秒累积误差小于0.1 ms,在实际应用中可以稳定输出本地时钟,满足遥感设备时钟同步和倍频的需求。
The remote sensing equipment needs to be equipped with a high precision local clock source in order to synchronize with the clock of the satellite platform. The digital phase locked-loop design is a key technology of synchronization and frequency multiplication of the clock. Long period input signals and large frequency multiplication coefficient add more difficulties of the loop design from two different ways.Under the condition of second pulse synchronization and 10000 times frequency multiplication, a method of digital loop parameter algorithm was proposed. The response characteristics of the loop were analyzed by establishing the Z domain model and the approximate S domain model. The whole design was implemented by field programmable gate array. Experiments show that the design of the digital phase-locked loop can be locked in 5 input clock cycles, and the cumulative error is less than 0.1 ms per second during stable operation. In practical application, the digital phase locked loop can stabilize the output of the local clock to meet the needs of the remote sensing devices' clock synchronization and frequency multiplication.
The remote sensing equipment needs to be equipped with a high precision local clock source in order to synchronize with the clock of the satellite platform. The digital phase locked-loop design is a key technology of synchronization and frequency multiplication of the clock. Long period input signals and large frequency multiplication coefficient add more difficulties of the loop design from two different ways.Under the condition of second pulse synchronization and 10000 times frequency multiplication, a method of digital loop parameter algorithm was proposed. The response characteristics of the loop were analyzed by establishing the Z domain model and the approximate S domain model. The whole design was implemented by field programmable gate array. Experiments show that the design of the digital phase-locked loop can be locked in 5 input clock cycles, and the cumulative error is less than 0.1 ms per second during stable operation. In practical application, the digital phase locked loop can stabilize the output of the local clock to meet the needs of the remote sensing devices' clock synchronization and frequency multiplication.
引文
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[14] Ma Zhuo. The Research on Low Jitter PLL for High-Performance CPUs(面向高性能CPU的锁相环低抖动技术研究)[D]. Changsha:Doctorial Dissertation of National University of Defense Technology, 2013:23-25.
[15] Xu Shoushi, Tan Yong,GUO Wu.Signals and systems:Theory,Methods and Applications(信号与系统:理论方法和应用)[M]. 2nd ed. Heifei:University of Science and Technology of China Press, 2010:390-397(in Chinese).
[2] Long Hu, Liu Haowei, Li Zhiwei, et al. Narrow-linewidth tunable fiber laser for spectral calibration of spatial heterodyne spectrometer[J]. Chinese Journal of Quantum Electronics(量子电子学报),2017,34(3):339-343(in Chinese).
[3] Song Zhiping, Zhang Minghui, Hong Jin. Measured data processing method of spectropolarimeter based on PSIM technology[J]. Chinese Journal of Quantum Electronics(量子电子学报),2016,33(2):249-256(in Chinese).
[4] Du Peijun, Xia Junshi,Xue Zhaohui, et al. Review of hyperspectral remote sensing image classification[J].Journal of Remote Sensing(遥感学报),2016, 20(2):236-256(in Chinese).
[5] Wang Jun, Wang Lei, He Xin. The Study of high accuracy time keeping based on FPGA when navigation satellite losing connection[J]. Chinese Journal of Electron Devices(电子器件),2016,39(1):140-143(in Chinese).
[6] Gu Kang, Li Peng, Wang Chao, et al. Design of high precision time keeping system based on technology of ambient awareness[J]. Electronic Measurement Technology(电子测量技术),2015, 38(5):24-26+36?(in Chinese).
[7] Zeng Yifan, Wu Siqi. Design of time keeping circuit based on FPGA and FSM[J]. Computer Measurement and Control(计算机测量与控制),2014, 22(5):1565-1567(in Chinese).
[8] Zhai Xueming, Yang Lei, Yang Liang. Design on a GPS timing and time keeping scheme based on FPGA[J].Measurement and Control Technology(测控技术),2016, 35(5):153-156(in Chinese).
[9] Huang Xiang, Jiang Daozhuo. A high accuracy time keeping scheme based on GPS[J]. Automation of Electric Power Systems(电力系统自动化),2010, 34(18):74-77(in Chinese).
[10] Peng Yonglong, Zhu Jinbo, Li Yabin. Implementation of variable PI parameter control digital phase-locked loop based on FPGA[J]. Chinese Journal of Power Sources(电源技术),2016, 40(4):906-909(in Chinese).
[11] Xiao Shuai, Sun Jianbo, Geng Hua, et al. FPGA based ratio changeable all digital phase-locked-loop[J]. Transactions of China Electrotechnical Society(电工技术学报),2012,27(4):153-158(in Chinese).
[12] Pang Hao, Zu Yunxiao, Wang Zanji. A new design of all digital phase-locked loop[J]. Proceedings of The Chinese Society for Electrical Engineering(中国电机工程学报),2003, 23(2):37-41+131(in Chinese).
[13] Zhang Zhiwen, Zeng Zhibing, Luo Fulong, et al. Synchronous frequency multiplication technology based on total digital phase-locked loop[J].Electric Power Automation Equipment(电力自动化设备),2010, 30(2):123-126+130?(in Chinese).
[14] Ma Zhuo. The Research on Low Jitter PLL for High-Performance CPUs(面向高性能CPU的锁相环低抖动技术研究)[D]. Changsha:Doctorial Dissertation of National University of Defense Technology, 2013:23-25.
[15] Xu Shoushi, Tan Yong,GUO Wu.Signals and systems:Theory,Methods and Applications(信号与系统:理论方法和应用)[M]. 2nd ed. Heifei:University of Science and Technology of China Press, 2010:390-397(in Chinese).