带有p型岛的超低导通电阻绝缘体上硅器件新结构
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摘要
为了减小绝缘体上硅(SOI)器件的比导通电阻,提高器件的击穿电压,提出一种带有p型岛的SOI器件新结构.该结构的特征如下:首先,漂移区周围采用U型栅结构,在开启状态下,U型栅侧壁形成高密度电子积累层,提供了一个从源极到漏极低电阻电流路径,实现了超低比导通电阻;其次,在漂移区引入的氧化槽折叠了漂移区长度,大大提高了击穿电压;最后,在氧化槽中引入一个p型岛,该高掺杂p型岛使漂移区电场得到重新分配,提高了击穿电压,且p型岛的加入增大了漂移区浓度,使器件比导通电阻进一步降低.结果表明:在最高优值条件下,器件尺寸相同时,相比传统SOI结构,新结构的击穿电压提高了140%,比导通电阻降低了51.9%.
An ultralow specific on-resistance(Ron,sp)of a silicon on insulator(SOI)device with a p-type island is proposed to reduce the specific on-resistance and improve the breakdown voltage of an SOI device. The device has the following features. First,a U-shaped gate is installed around the drift region. In the on-state,the U-shaped gate induces a high-density electron accumulation layer along the sidewall,which provides a low-resistance current path from the source to the drain,to achieve an ultralow Ron,sp. Second,an oxidation trench is introduced into the drift region. This oxidation trench can fold the drift region length,which considerably increases the breakdown voltage.Finally,a p-type island is introduced. The highly doped p-type island redistributs the drift region electric field,which improves the breakdown voltage. The addition of the p-type island also increases the drift region concentration,which further decreases the device Ron,sp. Simulation results show that under the condition of the highest FOM,the breakdown voltage is increased by 140%,and the specific on-resistance is reduced by 51.9% compared with a conventional SOI device at the same cell pitch.
An ultralow specific on-resistance(Ron,sp)of a silicon on insulator(SOI)device with a p-type island is proposed to reduce the specific on-resistance and improve the breakdown voltage of an SOI device. The device has the following features. First,a U-shaped gate is installed around the drift region. In the on-state,the U-shaped gate induces a high-density electron accumulation layer along the sidewall,which provides a low-resistance current path from the source to the drain,to achieve an ultralow Ron,sp. Second,an oxidation trench is introduced into the drift region. This oxidation trench can fold the drift region length,which considerably increases the breakdown voltage.Finally,a p-type island is introduced. The highly doped p-type island redistributs the drift region electric field,which improves the breakdown voltage. The addition of the p-type island also increases the drift region concentration,which further decreases the device Ron,sp. Simulation results show that under the condition of the highest FOM,the breakdown voltage is increased by 140%,and the specific on-resistance is reduced by 51.9% compared with a conventional SOI device at the same cell pitch.
引文
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[8]石艳梅,刘继芝,姚素英,等.具有L型源极场板的双槽绝缘体上硅高压器件新结构[J].物理学报,2014,63(23):237305-1-237305-8.Shi Yanmei,Liu Jizhi,Yao Suying,et al.A dualtrench silicon on insulator high voltage device with an L-shaped source field plate[J].Acta Physica Sinica,2014,63(23):237305-1-237305-8(in Chinese).
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[12]Hu Shengdong,Chen Yinhui,Jin Jingjing,et al.A low specific on-resistance power trench MOSFET with a buried-interface-drain[J].Superlattices and Microstructures,2015,85:133-138.
[13]Huang Linhua,Luo Xiaorong,Wei Jie,et al.A snapback-free fast-switching SOI LIGBT with polysilicon regulative resistance and trench cathode[J].IEEE Transactions on Electron Devices,2017,64(9):3961-3966.
[14]Orouji A A,Rahimifar A,Jozi M,et al.A novel double-gate SOI MOSFET to improve the floating body effect by dual Si Ge trench[J].Journal of Computation Electronics,2016,15(2):537-544.
[15]Shi Xianlong,Luo Xiaorong,Wei Jie,et al.A novel LDMOS with a junction field plate and a partial N-buried layer[J].Chinese Physics B,2014,23(12):127303-1-127303-5.
[16]Zhou Kun,Luo Xiaorong,Li Zhaoji,et al.Analytical model and new structure of the variable-k dielectric trench LDMOS with improved breakdown voltage and specific on-resistance[J].IEEE Transactions on Electron Devices,2015,62(10):3334-3340.
[17]Fan Yuanhang,Luo Xiaorong,Wang Pei,et al.A high figure-of-merit SOI MOSFET with a double-sided charge oxide-trench[J].Chinese Physics Letter,2013,30(8):088503-1-088503-4.
[18]Wang Zhuo,Li Pengcheng,Zhang Bo,et al.Ultralow specific on-resistance trench MOSFET with a U-shaped extended gate[J].Chinese Physics Letter,2015,32(6):068501-1-068501-4.
[19]Luo Xiaorong,Fan Jie,Wang Yuangang,et al.Ultralow specific on-resistance high-voltage SOI lateral MOSFET[J].IEEE Electron Device Letter,2011,32(2):185-187.
[20]Luo Xiaorong,Luo Yinchun,Fan Ye,et al.A low specific on-resistance SOI MOSFET with dual gates and recessed drain[J].Chinese Physics B,2013,22(2):027304-1-027304-5.
[2]Ma Da,Luo Xiaorong,Wei Jie,et al.Ultra-low specific on-resistance high-voltage vertical double diffusion metal-oxide-semiconductor field-effect transistor with continuous electron accumulation layer[J].Chinese Physics B,2016,25(4):048502-1-048502-6.
[3]Zhou Kun,Luo Xiaorong,Huang Linhua,et al.An ultralow loss superjunction reverse blocking insulatedgate bipolar transistor with shorted-collector trench[J].IEEE Electron Device Letter,2016,37(11):1462-1465.
[4]Luo Xiaorong,Lei Tianfei,Wang Yuangang,et al.Low on-resistance SOI dual-trench-gate MOSFET[J].IEEE Transactions on Electron Devices,2012,59(2):504-509.
[5]Xia Chao,Cheng Xinhong,Wang Zhongjian,et al.Improvement of SOI trench LDMOS performance with double vertical metal field plate[J].IEEE Transactions on Electron Devices,2014,61(10):3477-3482.
[6]Wang Yuangang,Luo Xiaorong,Ge Rui,et al.Compound buried layer SOI high voltage device with a step buried oxide[J].Chinese Physics B,2011,20(7):077304-1-077304-6.
[7]Zhou Kun,Luo Xiaorong,Fan Yuanhang,et al.A low on-resistance buried current path SOI p-channel LDMOScompatible with n-channel LDMOS[J].Chin Phys B,2013,22(6):067306-1-067306-7.
[8]石艳梅,刘继芝,姚素英,等.具有L型源极场板的双槽绝缘体上硅高压器件新结构[J].物理学报,2014,63(23):237305-1-237305-8.Shi Yanmei,Liu Jizhi,Yao Suying,et al.A dualtrench silicon on insulator high voltage device with an L-shaped source field plate[J].Acta Physica Sinica,2014,63(23):237305-1-237305-8(in Chinese).
[9]Ge Weiwei,Luo Xiaorong,Wu Junfeng,et al.Ultralow on-resistance LDMOS with multi-plane electron accumulation layers[J].IEEE Electron Device Letter,2017,38(7):910-913.
[10]Hu Shengdong,Luo Jun,Jiang Yuyu,et al.Improving breakdown,conductive,and thermal performances for SOI high voltage LDMOS using a partial compound buried layer[J].Solid State Electron,2016,117:146-151.
[11]Yang Fujen,Gong Jeng,Su Ruyi,et al.A 700-V device in high-voltage power ICs with low on-state resistance and enhanced SOA[J].IEEE Transactions on Electron Devices,2013,60(9):2847-2853.
[12]Hu Shengdong,Chen Yinhui,Jin Jingjing,et al.A low specific on-resistance power trench MOSFET with a buried-interface-drain[J].Superlattices and Microstructures,2015,85:133-138.
[13]Huang Linhua,Luo Xiaorong,Wei Jie,et al.A snapback-free fast-switching SOI LIGBT with polysilicon regulative resistance and trench cathode[J].IEEE Transactions on Electron Devices,2017,64(9):3961-3966.
[14]Orouji A A,Rahimifar A,Jozi M,et al.A novel double-gate SOI MOSFET to improve the floating body effect by dual Si Ge trench[J].Journal of Computation Electronics,2016,15(2):537-544.
[15]Shi Xianlong,Luo Xiaorong,Wei Jie,et al.A novel LDMOS with a junction field plate and a partial N-buried layer[J].Chinese Physics B,2014,23(12):127303-1-127303-5.
[16]Zhou Kun,Luo Xiaorong,Li Zhaoji,et al.Analytical model and new structure of the variable-k dielectric trench LDMOS with improved breakdown voltage and specific on-resistance[J].IEEE Transactions on Electron Devices,2015,62(10):3334-3340.
[17]Fan Yuanhang,Luo Xiaorong,Wang Pei,et al.A high figure-of-merit SOI MOSFET with a double-sided charge oxide-trench[J].Chinese Physics Letter,2013,30(8):088503-1-088503-4.
[18]Wang Zhuo,Li Pengcheng,Zhang Bo,et al.Ultralow specific on-resistance trench MOSFET with a U-shaped extended gate[J].Chinese Physics Letter,2015,32(6):068501-1-068501-4.
[19]Luo Xiaorong,Fan Jie,Wang Yuangang,et al.Ultralow specific on-resistance high-voltage SOI lateral MOSFET[J].IEEE Electron Device Letter,2011,32(2):185-187.
[20]Luo Xiaorong,Luo Yinchun,Fan Ye,et al.A low specific on-resistance SOI MOSFET with dual gates and recessed drain[J].Chinese Physics B,2013,22(2):027304-1-027304-5.