基于杂散电感分析的MOSFET模块布局结构设计的研究
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- 英文论文题名：Study of MOSFET Module Layout Structure Design Based on Analysis of Stray Inductance
- 论文作者：代茜 ; 徐菊 ; 郑利兵 ; 靳鹏云
- 英文论文作者：Dai Xi ; Xu Ju ; Zheng Libing ; Jin Pengyun ; Institute of Electrical Engineering ; Chinese ; Academy of Sciences ; University of Chinese Academy of Sciences
- 年：2016
- 作者机构：中国科学院电工研究所;中国科学院大学;
- 论文关键词：MOSFET功率模块 ; 芯片布局 ; 双脉冲测试 ; 开关损耗 ; 杂散参数 ; 有限元
- 英文论文关键词：MOSFET power module ; Chip layout ; Double-pulse test ; Switching loss ; Stray parameters ; Finite element
- 会议召开时间：2016-09-22
- 会议录名称：2016年中国环境与安全监测技术研讨会—第27届MICONEX2016科学仪器惠及民生系列分会场论文集
- 语种：中文
- 分类号：TN386
- 学会代码：XDKX
- 会议名称：2016年中国环境与安全监测技术研讨会—第27届MICONEX2016科学仪器惠及民生系列分会场
- 会议地点：中国北京
- 主办单位：中国仪器仪表学会
- 学会名称：现代科学仪器编辑部
- 页数：5
- 文件大小：3012k
- 原文格式：D
- 会议级别：全国
摘要
金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)模块内部芯片布局及封装结构的不同引起的寄生电感分布的差异对模块的可靠性有直接的影响。为了减小模块内部的杂散电感,提高模块工作的可靠性,本文提出了三种符合要求的功率模块芯片布局结构,对比分析了功率模块内部三种芯片布局结构产生的环路寄生电感对开关过程的影响。结果表明通过不同的布局结构设计,可以实现减小杂散电感,提高模块工作可靠性的目的,为模块的封装提供参考。
Different metal oxide semiconductor field effect transistormodulehas different parasitic inductance distribution, which is caused by internal chip layout and packaging structure, parasitic inductancehas the direct impact on the reliability of the module. In order to reduce the stray inductance in the module and improve the reliability of the module, three kinds of power modules was proposed in this paper.The influence of the circuit parasitic inductance generated by the three chip layout structure on the switching process was compared and analyzed. The resultsshowed that the layout of different structure design can reduce the stray inductance and improve the work reliability of the module. It can provide the reference for the module package.
Different metal oxide semiconductor field effect transistormodulehas different parasitic inductance distribution, which is caused by internal chip layout and packaging structure, parasitic inductancehas the direct impact on the reliability of the module. In order to reduce the stray inductance in the module and improve the reliability of the module, three kinds of power modules was proposed in this paper.The influence of the circuit parasitic inductance generated by the three chip layout structure on the switching process was compared and analyzed. The resultsshowed that the layout of different structure design can reduce the stray inductance and improve the work reliability of the module. It can provide the reference for the module package.
引文
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[2]肖向锋.电力电子器件产业发展战略研究[J].电力电子,2011(1):6-10.
[3]王兆安,杨旭,王晓宝.电力电子集成技术的现状及发展方向[J].电力电子技术,2003,37(5):90-94.
[4]褚华斌,钟小刚,吴志伟,等.功率MOSFET的研究与进展[J].半导体技术,2011,36(5):363-367.
[5]Xing K,Lee F C,Boroyevich D.Extraction of parasitics within wire-bond IGBT modules[C]//Applied Power Electronics C o n f e r e n c e a n d E x p o s i t i o n,1 9 9 8.A P E C'9 8.C o n f e r e n c e Proceedings 1998.,Thirteenth Annual.IEEE,1998,1:497-503.
[6]陈材,裴雪军,陈宇,等.基于开关瞬态过程分析的大容量变换器杂散参数抽取方法[J].中国电机工程学报,2011,31(21):40-47.
[7]Wang J,Chung H S,Li R T.Characterization and experimental assessment of the effects of parasitic elements on the MOSFETswitching performance[J].IEEE Transactions on Power Electronics,2013,28(1):573-590.
[8]Reusch D,Strydom J.Understanding the effect of PCB layout on circuit performance in a high-frequency gallium-nitride-based point of load converter[J].IEEE Transactions on Power Electronics,2014,29(4):2008-2015.
[9]Chen H,Qian Z.Modeling and characterization of parasitic inductive coupling effects on differential-mode EMI performance of a boost converter[J].IEEE Transactions on Electromagnetic Compatibility,2011,53(4):
[10]王勇.智能功率模块可靠性的有限元仿真研究[D].上海交通大学,2015.
[11]王春雷,郑利兵,方化潮,等.IGBT模块的杂散参数计算与封装设计研究[J].智能电网,2015,4:010
[12]郑大勇,陈广聪.IGBT动态参数测试方法分析[J].电子产品可靠性与环境试验,2013,31(A01):247-250.
[13]Zhang L,Guo S,Li X,et al.Integrated Si C MOSFET module with ultra low parasitic inductance for noise free ultra high speed switching[C]//Wide Bandgap Power Devices and Applications(Wi PDA),2015 IEEE 3rd Workshop on.IEEE,2015:224-229.
[14]冯高辉,袁立强,赵争鸣,等.基于开关瞬态过程分析的母排杂散电感提取方法研究[J].中国电机工程学报,2014,34(36):6442-6449.