嵌入式128Kb SRAM的研究与设计
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摘要
随着微电子技术水平的不断提高，SRAM呈现出更高集成度、更快速及更低功耗的发展趋势。近年来，集成SRAM的各种系统芯片已屡见不鲜，它们在改善系统性能、提高芯片可靠性、降低成本与功耗等方面都起到了积极的作用。本文主要针对应用于MCU的嵌入式128Kb静态存储器的设计进行了详细的阐述。文章结合存储单元静态噪声容限(SNM)及软误差率(SER)的分析，对静态六管单元进行了优化设计，在保证缩小芯片面积(存储单元的尺寸为：10.8×14.8um~2)的同时提高了存储单元的工作稳定性(SNM_(6T)=713mv)。设计中采用了存储阵列划分、分级字线以及CMOS正反馈差分读出放大器等先进技术，读写速度可达到20ns。并且由于采用阵列划分技术，电路功耗减小为传统设计的1/8。芯片采用0.6um CMOS硅栅双阱双层多晶双层铝互连的制造工艺，芯片尺寸为：6.31×4.57mm~2。SRAM的字长可在×8b、×16b、×32b间自行配置，方便了用户的使用。
With the development of microelectronics the SRAM trends can be summarized as fast speed, large capacity and low power. In recent years, all kinds of chip embedded with SRAM is becoming more and more popular, which demonstrate excellent characteristics such as fast data store speed, high reliability and low dissipation power. In this paper a 128Kb full-CMOS SRAM is described which is embedded in a 32b MCU. Based on the analysis of the SNM and the SER, the device parameters of the 6T cell are optimized, which not only reduce cell size (the memory cell size is 10.8×14.8um2) but also make the SRAM more reliable (the SNM6T is 713mv). In order to improve the performance of the SRAM, array partition, divided word line structure and CMOS positive feedback sense amplifier are adopted. All of them not only improve the speed of the chip, but also reduce the power dissipation of the chip to the 1/8 compare with the traditional design. The access time of the SRAM is 20ns. The chip is fabricated by a double polysilicon,
double metal and twin-well 0.6um CMOS process technology, and the chip size is 6.31×4.57 mm2. In addition, the chip can be configurated as a ×8b, ×16b or ×32b memory for the sake of convenience for the customer.
With the development of microelectronics the SRAM trends can be summarized as fast speed, large capacity and low power. In recent years, all kinds of chip embedded with SRAM is becoming more and more popular, which demonstrate excellent characteristics such as fast data store speed, high reliability and low dissipation power. In this paper a 128Kb full-CMOS SRAM is described which is embedded in a 32b MCU. Based on the analysis of the SNM and the SER, the device parameters of the 6T cell are optimized, which not only reduce cell size (the memory cell size is 10.8×14.8um2) but also make the SRAM more reliable (the SNM6T is 713mv). In order to improve the performance of the SRAM, array partition, divided word line structure and CMOS positive feedback sense amplifier are adopted. All of them not only improve the speed of the chip, but also reduce the power dissipation of the chip to the 1/8 compare with the traditional design. The access time of the SRAM is 20ns. The chip is fabricated by a double polysilicon,
double metal and twin-well 0.6um CMOS process technology, and the chip size is 6.31×4.57 mm2. In addition, the chip can be configurated as a ×8b, ×16b or ×32b memory for the sake of convenience for the customer.
引文
1．陈章龙，“中国单片机的发展”，2001嵌入式系统及单片机国际学术交流会论文集。
2．袁涛，“微控制器应用技术发展及个性化设计”，2001嵌入式系统及单片机国际学术交流会论文集。
3．过玉清，“高速与大容量静态RAM”，
4．“SRAM在激烈竞争中开拓新市场”，电子产品世界，1996，10
5．贾智，“SRAM技术与市场”，计算机元器件，2000，2
6. T. P. Haraszti, "cmos memory circuits", Kluwer academic publishers
7. H. Okuyama, T. Nakano, S. Nishida, E. Aono, H.Satoh, and S. Arita, "A 7.5-ns 32Kx8 CMOS SRAM", IEEE J. Solid-State Circuits, Vol. SC-23,pp.1054-1059, Octuber. 1988
8．王万业，“CMOS SRAM存储单元研究”，半导体技术，pp32—35,1997，4(2)。
9. M. Matsumiya, S. Kawashima, M. Sakata, M. Ookura, T. Miyabo, T. Koga, K. Itabashi, K. Mizutani, H.Shimada, and N. Suzuki, "a 15-ns 16-Mb CMOS SRAM with Interdigitated Bit-Line Architecture" IEEE J. Solid—State Circuits, Vol. SC-27,pp. 1497—1053, November. 1992
10. K. Anami, M. Yoshimoto, H. Shinohara, Y. Hirata, and T. Nakano, "Design Consideration of a Static Memory Cell". IEEE J. Solid—State Circuits, Vol. SC-18(4),pp.414—418, Agnst.1983
11．J．M．Rabaey．著，“数字集成电路：设计透视”(影印版)，清华大学出版社，1998．9
12. K. Itoh and Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies", Proceedings of the IEEE, Vol.83, No.4, April,1995
13. S.T.Chu, J. Dikken, C. D.Hartgring, F. J.List, J.G. Raemaekers, S. A.Bell, B. Walsh, and R. H.W. Salters, "A 25-ns Low-Power Full-CMOS 1-Mbit (i28kx8) SRAM", IEEE J. Solid—State Circuits, Vol. SC-23 (5),pp.1078—1083, October.1988
14. E. Seevinck, F. J.List, and J. Lohstroh, "Sataic-Noise Margin Anslysis of MOS SRAM Cells" IEEE J. Solid-State Circuits, Vol. SC-22(5), pp.748-754,
October. 1987
15． J. Lohstroh, E. Seevinck, and J. De Groot, "Worst-Case Static Noise Margin Criteria for Logic Circuits and Their Mathematical Equivalence", IEEE J. Solid-State Circuits, Vol. SC-18(6) ,pp.803-807, December.1983
16． P. M. Carter and B. R.Wilkins, "Influences on Soft Error Rates in Static RAM's", IEEE J. Solid-State Circuits, Vol. SC-22(3) ,pp.430-436, June.1987
17． 贺朝会，李国政，罗晋生，刘恩科，"CMOS SRAM 单粒子翻转效应的解析 分析"半导体学报，pp174-178,2000, 21(2)
18． S. E. Kems, and B.D. Shafer, "The Design of Radiation-Hardened Ics for Space: A Compendium of Approaches" Proceedings of the IEEE, Vol.76(ll), pp.1470-1508,November,1988
19． H. Nambu, K. Kanetani, K. Yamasaki, K. Higeta, M. Usami, Y. Fujimura, K. Ando, T. Kusunoki, K. Yamaguchi, and N. Homma, "A 1． 8-ns Access, 550-MHz, 4． 5-Mb CMOS SRAM" IEEE J. Solid-State Circuits, Vol. SC-33(11) ,pp.l650-1657, November. 1998
20． W. C. H.Gubbels, C. D. Hartgring, R. H. W. Salters, J. A. M . Lammerts, M. J. Tooher, P. F. P. C.Hens, J.J.J. Brastiaens, J. M.F.V. Dijk, and M. A. Sprokel, "a 40-ns/100-pF Low-Power Full-CMOS 256K(32K+8) SRAM", IEEE J. Solid-State Circuits, Vol. SC-22(5) ,pp.741-747, October.1987
21． T. Hirose, H. Kuriyama, S. Murakami, K. Yuzuriha, T. Mukai, K. Tsutsumi, Y. Nishimura, Y. Kohno, and K. Anami, "a 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture", IEEE J. Solid-State Circuits, Vol. SC-25(5) ,pp. 1068-1073, October. 1990
22． T. Sakurai, J. Matsunaga, M. Isobe, T. Ohtani, K. Sawada, A. Aono, H. Nozawa, T. Iizuka, and S. Kohyama, "A Low Power 46ns 256kbit CMOS Static RAM with Dynamic Double Word Line" IEEE J. Solid-State Circuits, Vol. SC-19(5) ,pp.578-584, October. 1984
23． M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano, and T. Nakano, "A Divided Word-Line Structure in the Static RAM and Its
Application to a 64K Full CMOS RAM" IEEE J. Solid—State Circuits, Vol. SC-18(5), pp.497—485, October. 1983
24. L. C. Sood, J. S. Golab ,J. Salter, J. E. Leiss, and J..J. Barnes, "A Fast 8K×8 CMOS SRAM With Internal Power Down Design Techniques" IEEE J. Solid—State Circuits, Vol. SC-20(5),pp.941—950, October. 1985.
25. B. Chappell, S. E. Schuster, and G. A. Sai-Halasz "Stability and SER Analysis of Static RAM Cells" IEEE J. Solid—State Circuits, Vol. SC-20(1),pp.383—390, February. 1985
26. S. T. Flannagan, P. A. Reed, P. H. Voss, S. G Nogle, L. J. Day, D. Y. Sheng, J. J. Barnesm, and R. I. Kung, "Two 13-ns 64k CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques", IEEE J. Solid—State Circuits, Vol. SC-21(5),pp.692—703, October.1986
27. H. Okuyama, T. Nakano, S. Nishida, E. Aono, H. Satoh, and S. Arita, "A 7.5-ns 32k×8 CMOS SRAM", IEEE J. Solid—State Circuits, Vol. SC-23(5),pp.1054—1059, October. 1988
28. H. Shinohara, K. Anami, D. Ichinose, T. Wada, Y. Kohno, Y. Kawai, Y. Akasaka, and S. Kayano, "A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line", IEEE J. Solid—State Circuits, Vol. SC-20(5),pp.929—934, October. 1985
29. E. G. Friedman, and S. Powell, "Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI", IEEE J. Solid—State Circuits, Vol. SC-21(2), pp.240—246, April. 1986
30．甘学温主编，“数字CMOS VLSI分析与设计基础”，北京大学出版社，1999，2
31．曾平英、李兆麟、毛志刚等，“ASIC可测性设计技术”微电子学，Vol．29(3)，PP．150-153，1999，6
32．何蓉晖，李华伟、李晓维、宫云战等，“一款通用CPU的存储器内建自测试设计”，同济大学学报，Vol．30(10)，pp．1204-1208，2002，10
33．洪先龙、严晓浪、乔长阁等编“超大规模集成电路布图理论与算法”，科学出版社，1998
2．袁涛，“微控制器应用技术发展及个性化设计”，2001嵌入式系统及单片机国际学术交流会论文集。
3．过玉清，“高速与大容量静态RAM”，
4．“SRAM在激烈竞争中开拓新市场”，电子产品世界，1996，10
5．贾智，“SRAM技术与市场”，计算机元器件，2000，2
6. T. P. Haraszti, "cmos memory circuits", Kluwer academic publishers
7. H. Okuyama, T. Nakano, S. Nishida, E. Aono, H.Satoh, and S. Arita, "A 7.5-ns 32Kx8 CMOS SRAM", IEEE J. Solid-State Circuits, Vol. SC-23,pp.1054-1059, Octuber. 1988
8．王万业，“CMOS SRAM存储单元研究”，半导体技术，pp32—35,1997，4(2)。
9. M. Matsumiya, S. Kawashima, M. Sakata, M. Ookura, T. Miyabo, T. Koga, K. Itabashi, K. Mizutani, H.Shimada, and N. Suzuki, "a 15-ns 16-Mb CMOS SRAM with Interdigitated Bit-Line Architecture" IEEE J. Solid—State Circuits, Vol. SC-27,pp. 1497—1053, November. 1992
10. K. Anami, M. Yoshimoto, H. Shinohara, Y. Hirata, and T. Nakano, "Design Consideration of a Static Memory Cell". IEEE J. Solid—State Circuits, Vol. SC-18(4),pp.414—418, Agnst.1983
11．J．M．Rabaey．著，“数字集成电路：设计透视”(影印版)，清华大学出版社，1998．9
12. K. Itoh and Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies", Proceedings of the IEEE, Vol.83, No.4, April,1995
13. S.T.Chu, J. Dikken, C. D.Hartgring, F. J.List, J.G. Raemaekers, S. A.Bell, B. Walsh, and R. H.W. Salters, "A 25-ns Low-Power Full-CMOS 1-Mbit (i28kx8) SRAM", IEEE J. Solid—State Circuits, Vol. SC-23 (5),pp.1078—1083, October.1988
14. E. Seevinck, F. J.List, and J. Lohstroh, "Sataic-Noise Margin Anslysis of MOS SRAM Cells" IEEE J. Solid-State Circuits, Vol. SC-22(5), pp.748-754,
October. 1987
15． J. Lohstroh, E. Seevinck, and J. De Groot, "Worst-Case Static Noise Margin Criteria for Logic Circuits and Their Mathematical Equivalence", IEEE J. Solid-State Circuits, Vol. SC-18(6) ,pp.803-807, December.1983
16． P. M. Carter and B. R.Wilkins, "Influences on Soft Error Rates in Static RAM's", IEEE J. Solid-State Circuits, Vol. SC-22(3) ,pp.430-436, June.1987
17． 贺朝会，李国政，罗晋生，刘恩科，"CMOS SRAM 单粒子翻转效应的解析 分析"半导体学报，pp174-178,2000, 21(2)
18． S. E. Kems, and B.D. Shafer, "The Design of Radiation-Hardened Ics for Space: A Compendium of Approaches" Proceedings of the IEEE, Vol.76(ll), pp.1470-1508,November,1988
19． H. Nambu, K. Kanetani, K. Yamasaki, K. Higeta, M. Usami, Y. Fujimura, K. Ando, T. Kusunoki, K. Yamaguchi, and N. Homma, "A 1． 8-ns Access, 550-MHz, 4． 5-Mb CMOS SRAM" IEEE J. Solid-State Circuits, Vol. SC-33(11) ,pp.l650-1657, November. 1998
20． W. C. H.Gubbels, C. D. Hartgring, R. H. W. Salters, J. A. M . Lammerts, M. J. Tooher, P. F. P. C.Hens, J.J.J. Brastiaens, J. M.F.V. Dijk, and M. A. Sprokel, "a 40-ns/100-pF Low-Power Full-CMOS 256K(32K+8) SRAM", IEEE J. Solid-State Circuits, Vol. SC-22(5) ,pp.741-747, October.1987
21． T. Hirose, H. Kuriyama, S. Murakami, K. Yuzuriha, T. Mukai, K. Tsutsumi, Y. Nishimura, Y. Kohno, and K. Anami, "a 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture", IEEE J. Solid-State Circuits, Vol. SC-25(5) ,pp. 1068-1073, October. 1990
22． T. Sakurai, J. Matsunaga, M. Isobe, T. Ohtani, K. Sawada, A. Aono, H. Nozawa, T. Iizuka, and S. Kohyama, "A Low Power 46ns 256kbit CMOS Static RAM with Dynamic Double Word Line" IEEE J. Solid-State Circuits, Vol. SC-19(5) ,pp.578-584, October. 1984
23． M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano, and T. Nakano, "A Divided Word-Line Structure in the Static RAM and Its
Application to a 64K Full CMOS RAM" IEEE J. Solid—State Circuits, Vol. SC-18(5), pp.497—485, October. 1983
24. L. C. Sood, J. S. Golab ,J. Salter, J. E. Leiss, and J..J. Barnes, "A Fast 8K×8 CMOS SRAM With Internal Power Down Design Techniques" IEEE J. Solid—State Circuits, Vol. SC-20(5),pp.941—950, October. 1985.
25. B. Chappell, S. E. Schuster, and G. A. Sai-Halasz "Stability and SER Analysis of Static RAM Cells" IEEE J. Solid—State Circuits, Vol. SC-20(1),pp.383—390, February. 1985
26. S. T. Flannagan, P. A. Reed, P. H. Voss, S. G Nogle, L. J. Day, D. Y. Sheng, J. J. Barnesm, and R. I. Kung, "Two 13-ns 64k CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques", IEEE J. Solid—State Circuits, Vol. SC-21(5),pp.692—703, October.1986
27. H. Okuyama, T. Nakano, S. Nishida, E. Aono, H. Satoh, and S. Arita, "A 7.5-ns 32k×8 CMOS SRAM", IEEE J. Solid—State Circuits, Vol. SC-23(5),pp.1054—1059, October. 1988
28. H. Shinohara, K. Anami, D. Ichinose, T. Wada, Y. Kohno, Y. Kawai, Y. Akasaka, and S. Kayano, "A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line", IEEE J. Solid—State Circuits, Vol. SC-20(5),pp.929—934, October. 1985
29. E. G. Friedman, and S. Powell, "Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI", IEEE J. Solid—State Circuits, Vol. SC-21(2), pp.240—246, April. 1986
30．甘学温主编，“数字CMOS VLSI分析与设计基础”，北京大学出版社，1999，2
31．曾平英、李兆麟、毛志刚等，“ASIC可测性设计技术”微电子学，Vol．29(3)，PP．150-153，1999，6
32．何蓉晖，李华伟、李晓维、宫云战等，“一款通用CPU的存储器内建自测试设计”，同济大学学报，Vol．30(10)，pp．1204-1208，2002，10
33．洪先龙、严晓浪、乔长阁等编“超大规模集成电路布图理论与算法”，科学出版社，1998