0.6μm CMOS 622Mb/s高速分接器设计
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摘要
分接器是光纤通信网中的关键器件。它位于光纤接收机的末端，将接收到的一路高速信号重新恢复成多路的低速信号。本文简要介绍了分接器的实现工艺和设计流程，以及复接和分接的原理。
分接器有三种主要结构：串型结构、并型结构和树型结构，本文分析了三种结构的工作原理及其优缺点。根据三种结构的各自特点和设计目标，选用树型结构作为分接器的基本结构。
电路设计是分接器设计的基础。速度、功耗、面积是电路设计要考虑的主要因素，不同的电路形式具有不同的优缺点，如CMOS互补逻辑电路功耗低，面积小，速度相对较慢；SCFL(源极耦合FET逻辑)电路速度高，功耗和面积较大。所以要针对具体设计需要选用适当的电路形式或其组合结构，以满足设计要求。触发器是分接器的基本组成单元，建立时间和保持时间是影响电路速度的关键，所以减小建立时间和保持时间是触发器设计的主要目标，本文着重介绍了SCFL锁存器的设计和优化方法。
本文介绍了分接器的版图设计考虑，并给出了仿真结果和芯片的晶圆级测试结果，并对测试结果进行了分析。
本文设计的1：4分接器采用CSMC-HJ 0.6μm CMOS工艺实现，测试结果表明，芯片成功的实现了SDH STM-4级别1：4分接器的功能，最高分接速率可达622Mb／s。
Demultiplexer is one of the key electronic components in optic-fiber transmission systems.It normally lies at the end of optic-fiber recerver,which recovery original low-speed signals from a high-speed signal.In this thesis,we discuss the circuit design techniques,the technology of the IC realization and principal of multiplexer and demultiplexer in transmission systems.
Three basic strctures for demultiplexer,i.e.serial,parallel and tree.Their working principal,advantages and disadvantages will be discussed in the thesis.According to their characteristics and the design objective.the tree architecture was selected.
Circuit design is the basis of design of demultiplexer.Speed,power and chip area are the main factors that should be considered in circuit design.Every circuit structure has its merits and drawbacks,e.g.CMOS logic family has a slower speed,but lower power,smaller area,SCFL (Source Couple FET Logic) family has a higher speed,but higher power,larger area.We should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors.Flip-flop is the fundamental element of demultiplexer,setup time and hold up time are key factors,which influence the speed of circuit,thus the design aim is how to reduce them.In this thesis we place emphasis on the design of SCFL latches.
Layout design is discussed briefly and simulation results are presented.At last,the test results from the relatived demultiplexer IC on wafer,will be domestrated and analysed.
Demultiplexer was fabricated in CSMC-HJ 0. 6um CMOS Technology.The test results show that demultiplexer accomplished the function in SDH STM-4 speed level.Furthermore,it can reach 622Mb/s data speed.
分接器有三种主要结构：串型结构、并型结构和树型结构，本文分析了三种结构的工作原理及其优缺点。根据三种结构的各自特点和设计目标，选用树型结构作为分接器的基本结构。
电路设计是分接器设计的基础。速度、功耗、面积是电路设计要考虑的主要因素，不同的电路形式具有不同的优缺点，如CMOS互补逻辑电路功耗低，面积小，速度相对较慢；SCFL(源极耦合FET逻辑)电路速度高，功耗和面积较大。所以要针对具体设计需要选用适当的电路形式或其组合结构，以满足设计要求。触发器是分接器的基本组成单元，建立时间和保持时间是影响电路速度的关键，所以减小建立时间和保持时间是触发器设计的主要目标，本文着重介绍了SCFL锁存器的设计和优化方法。
本文介绍了分接器的版图设计考虑，并给出了仿真结果和芯片的晶圆级测试结果，并对测试结果进行了分析。
本文设计的1：4分接器采用CSMC-HJ 0.6μm CMOS工艺实现，测试结果表明，芯片成功的实现了SDH STM-4级别1：4分接器的功能，最高分接速率可达622Mb／s。
Demultiplexer is one of the key electronic components in optic-fiber transmission systems.It normally lies at the end of optic-fiber recerver,which recovery original low-speed signals from a high-speed signal.In this thesis,we discuss the circuit design techniques,the technology of the IC realization and principal of multiplexer and demultiplexer in transmission systems.
Three basic strctures for demultiplexer,i.e.serial,parallel and tree.Their working principal,advantages and disadvantages will be discussed in the thesis.According to their characteristics and the design objective.the tree architecture was selected.
Circuit design is the basis of design of demultiplexer.Speed,power and chip area are the main factors that should be considered in circuit design.Every circuit structure has its merits and drawbacks,e.g.CMOS logic family has a slower speed,but lower power,smaller area,SCFL (Source Couple FET Logic) family has a higher speed,but higher power,larger area.We should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors.Flip-flop is the fundamental element of demultiplexer,setup time and hold up time are key factors,which influence the speed of circuit,thus the design aim is how to reduce them.In this thesis we place emphasis on the design of SCFL latches.
Layout design is discussed briefly and simulation results are presented.At last,the test results from the relatived demultiplexer IC on wafer,will be domestrated and analysed.
Demultiplexer was fabricated in CSMC-HJ 0. 6um CMOS Technology.The test results show that demultiplexer accomplished the function in SDH STM-4 speed level.Furthermore,it can reach 622Mb/s data speed.
引文
[1] 陈贵灿 邵志标 程军 编著，CMOS集成电路设计，西安西安交通大学出版社，2000．2
[2] 陆建华，超高速CMOS 32：1复接器集成电路设计，东南大学硕士学位论文，2000．3
[3] R.pullela U.Bhattacharya M.J.W.Rodwell, Multiplexer/Demultiplexer IC technology for 100Gb/s fiber-optic transmission。IEEE Joumal of Solid-State Circuits, 1996.5
[4] T.Seshita Y.Ikeda H.Wakimoto K.Ishida, A 20GHz 8bit multiplexer IC implemented with 0.5 μm GaAs MESFET's, IEEE Journal of Solid-State Circuits, 1994.12
[5] T.Otsuji K.Murata T.Enoki Y.Umeda, An 80-Gbit/s multiplexer IC using InAIAs/InGaAs/InP HEMTs, IEEE Journal of Solid-State Circuits, 1998.9
[5] T.Otsuji Y.Imai E.Sano S.Kimura S.Yamaguchi M.Yoneyam T. Enoki Y. Umeda, 40-Gb/s ICs for future lightwave communications systems, IEEE Journal of Solid-State Circuits, 1997.9
[7] M.Mokhtari T.Swahn M.Kardos T.Juhola G.Schuppener, InP-HBT chip-set for 40-Gb/s fiber optical communication systems operational at 3V, IEEE Journal of Solid-State Circuits, 1997.9
[8] K.Runge D.Daniel R.D.Standley J.L.Gimlett R.B.Nubling R.L.Pierson S.M.Beccue, AIGaAs/GaAs HBT I C's for high-speed lightwave transmission systems, IEEE Journal of Solid-State Circuits, 1992.10
[9] R.J.Bayruns E.A.Hofstatter H.T.Weston, A fine-line NMOS 3-Gbit/s 12-channel time-division multiplexer-demultiplexer chip set, IEEE Journal of Solid-State Circuits, 1989.6
[10] K.R.Shastri W.E.Carter, 1GHz CMOS 12:1 Time Division MUX/DMUX Pair, CICC, 1991.5
[11] 谢世钟，10Gb／s SDH光纤通信系统用光发射与光接收模块，电子产品世界，1999年4月
[12] 陶蕤 王志功 顾峥，低噪声集成压控振荡器噪声性能分析，2000年1月，总第102期
[13] 陈新华等，SDH系统2.5Gb／s CMOS激光发射机驱动电路99年全国光电子器件与集成技术会议论文集
[14] 王志功 柯锡明，2.5Gb／s光纤通信用0.35μm CMOS芯片设计成功，高技术通讯，2000．5
[15] 陶蕤 王志功2.5Gb／s光接收机跨阻前置放大器，半导体光电，2001．3
[16] 陶蕤 王志功 刘军 陈海涛，SDH系统STM-16速率级CMOS限幅放大器，光电子激光，2000．11
[17] 张明德 孙小菡编著，光纤通信原理与系统，南京东南大学出版社，1996．12
[18] 田磊，0.25μm CMOS 10Gb／s高速分接器设计，东南大学硕士学位论文，2001．5
[19] 王鸿生 龚双瑾编著，通信网基本技术，北京人民邮电出版社，1993．3
[20] 赵梓森编著，光纤通信工程，北京人民邮电出版社，1994．5
[21] 王志功编著，光纤通信集成电路设计，北京高等教育出版社，2003．6
[22] 卢文才，CMOS 1：4分接器的设计，东南大学硕士学位论文，2003．5
[23] Masakaji Shoji, Theory of CMOS Digital Circuits and Circuits Failures, Princeton University
[24] D.Hodges H.Jackson, Analysis and Design of Digital Intrgrated Circuits, McGraw-Hill, 1988
[25] Y.Suzuki K.Odagawa T.Abe, Clocked CMOS calculator circuitry, IEEE Journal of Solid-State Circuits, 1973.12
[26] 谢嘉奎 宣月清 冯军编著，电子线路线性部分(第四版)，北京高等教育出版社，1999．6
[27] 包志华 景为平，3.75 GHz 0.35μm CMOS 1：4静态分频器集成电路设计，南京邮电学院学报(自然科学版)，2001．4
[2] 陆建华，超高速CMOS 32：1复接器集成电路设计，东南大学硕士学位论文，2000．3
[3] R.pullela U.Bhattacharya M.J.W.Rodwell, Multiplexer/Demultiplexer IC technology for 100Gb/s fiber-optic transmission。IEEE Joumal of Solid-State Circuits, 1996.5
[4] T.Seshita Y.Ikeda H.Wakimoto K.Ishida, A 20GHz 8bit multiplexer IC implemented with 0.5 μm GaAs MESFET's, IEEE Journal of Solid-State Circuits, 1994.12
[5] T.Otsuji K.Murata T.Enoki Y.Umeda, An 80-Gbit/s multiplexer IC using InAIAs/InGaAs/InP HEMTs, IEEE Journal of Solid-State Circuits, 1998.9
[5] T.Otsuji Y.Imai E.Sano S.Kimura S.Yamaguchi M.Yoneyam T. Enoki Y. Umeda, 40-Gb/s ICs for future lightwave communications systems, IEEE Journal of Solid-State Circuits, 1997.9
[7] M.Mokhtari T.Swahn M.Kardos T.Juhola G.Schuppener, InP-HBT chip-set for 40-Gb/s fiber optical communication systems operational at 3V, IEEE Journal of Solid-State Circuits, 1997.9
[8] K.Runge D.Daniel R.D.Standley J.L.Gimlett R.B.Nubling R.L.Pierson S.M.Beccue, AIGaAs/GaAs HBT I C's for high-speed lightwave transmission systems, IEEE Journal of Solid-State Circuits, 1992.10
[9] R.J.Bayruns E.A.Hofstatter H.T.Weston, A fine-line NMOS 3-Gbit/s 12-channel time-division multiplexer-demultiplexer chip set, IEEE Journal of Solid-State Circuits, 1989.6
[10] K.R.Shastri W.E.Carter, 1GHz CMOS 12:1 Time Division MUX/DMUX Pair, CICC, 1991.5
[11] 谢世钟，10Gb／s SDH光纤通信系统用光发射与光接收模块，电子产品世界，1999年4月
[12] 陶蕤 王志功 顾峥，低噪声集成压控振荡器噪声性能分析，2000年1月，总第102期
[13] 陈新华等，SDH系统2.5Gb／s CMOS激光发射机驱动电路99年全国光电子器件与集成技术会议论文集
[14] 王志功 柯锡明，2.5Gb／s光纤通信用0.35μm CMOS芯片设计成功，高技术通讯，2000．5
[15] 陶蕤 王志功2.5Gb／s光接收机跨阻前置放大器，半导体光电，2001．3
[16] 陶蕤 王志功 刘军 陈海涛，SDH系统STM-16速率级CMOS限幅放大器，光电子激光，2000．11
[17] 张明德 孙小菡编著，光纤通信原理与系统，南京东南大学出版社，1996．12
[18] 田磊，0.25μm CMOS 10Gb／s高速分接器设计，东南大学硕士学位论文，2001．5
[19] 王鸿生 龚双瑾编著，通信网基本技术，北京人民邮电出版社，1993．3
[20] 赵梓森编著，光纤通信工程，北京人民邮电出版社，1994．5
[21] 王志功编著，光纤通信集成电路设计，北京高等教育出版社，2003．6
[22] 卢文才，CMOS 1：4分接器的设计，东南大学硕士学位论文，2003．5
[23] Masakaji Shoji, Theory of CMOS Digital Circuits and Circuits Failures, Princeton University
[24] D.Hodges H.Jackson, Analysis and Design of Digital Intrgrated Circuits, McGraw-Hill, 1988
[25] Y.Suzuki K.Odagawa T.Abe, Clocked CMOS calculator circuitry, IEEE Journal of Solid-State Circuits, 1973.12
[26] 谢嘉奎 宣月清 冯军编著，电子线路线性部分(第四版)，北京高等教育出版社，1999．6
[27] 包志华 景为平，3.75 GHz 0.35μm CMOS 1：4静态分频器集成电路设计，南京邮电学院学报(自然科学版)，2001．4