基于0.18μm CMOS工艺的低电压、低功耗、超高速集成电路设计
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摘要
IT业在不断发展和革新的过程中,呈现出网络化、数字化、智能化、低功耗等几大特点和发展趋势。人们需要高速、宽带的通信网络来互通信息。光纤通信由于其自身的优势将逐步取代电缆通信。在光纤传输系统中,分接器处于光接收机的末端,将经过数据判决后得到的高速串行信号转变为并行的多路低速信号。因此,分接器是实现高速通信系统的重要部分,其性能直接影响到最后的输出信号。而在光纤通信及无线通信系统中,分接器必须由分频器将高速时钟变成低速时钟。在此情况下,超高速的分频器是工作在最高频率的电路之一,起着至关重要的作用。因此随着CMOS工艺的进步,基于CMOS工艺的超高速分频器的设计具有重大的现实意义。
本论文的主要目标是,采用特征频率仅为49GHz的0.18μm CMOS工艺,分析、研究并实现工作频率超过20GHz的1:4超高速分频电路以及采用相同工艺,分析、研究符合STM-64(9.952Gb/s)级别的低电压、低功耗1:4分接器,并在下一次MPW完成投片及测试工作。为了使电路性能达到低电压、低功耗与超高速的统一,本文采用一种改进型共栅结构的动态负载锁存器。基于该锁存器,设计并实现了超高速1:4分频器。在片测试结果表明:其最高工作速率可达26GHz,分频范围超过20GHz;封装后的测试结果表明:其最高工作速率达19.6GHz,且在预期的10GHz工作频率获得了较为理想的输出信号。本文同时采用同种工艺在1.2V的电源电压下完成了10Gb/s 1:4分接器的仿真和版图设计,后仿真结果表明其完全达到设计指标,且核心功耗仅为10mW。该芯片将于下次MPW中投片、完成测试。
本论文给出了分接器电路及分频器电路的基本原理并以电路设计、版图设计、芯片测试的顺序详细介绍了电路的设计流程及1:4超高速分频器的测试结果。在片测试及封装测试结果表明,采用该方案实现的低电压、低功耗、超高速分频器性能优良,完全达到设计要求,为产业化积累了经验,做出了贡献。
Several characteristics and trends, such as network, digital, intelligence and low power present during the innovation and development of IT industry. High speed, broad band communication network are required to communicate information. For these reason, Optical communication will gradually replace cable communication. In optical transmission system, Demultiplexer(Demux) is at the tail end of the optic-fiber receiver. Demux transforms the one way high speed serial signal which from data decision to N (N>1) way low speed parallel signal. Therefore, Demux is an important part of high speed communication system, its performance directly influence the last output signal. So, high speed Demux circuit is the indispensable key circuit in optical communication. Additionally, super high speed frequency dividers are widely applied in optical communication and wireless communication system. In a Demux, frequency divider converts the high speed clock to the lower speed clock. In the case, frequency divider is one of the circuits working on the highest frequency. With the development of CMOS process, design of super high speed frequency divider based on CMOS process makes great sense.
The article's main objective is to analyze, research and realize a super high speed frequency divider circuit based on 0.18μm CMOS process, and the circuit's work rate is over 20GHz.And based on the same process, analyze, research a low voltage, low power 1:4 Demux applying for STM-64, the chip will be sent to foundry in the next MPW project, and subsequently be tested on wafer. Since the standard voltage in 0.18μm CMOS process is 1.8V, and f t is 49GHz, in 1.2V, traditional circuit structures are hard to work up to 10Gb/s, similarly, the traditional ones in 1.8V power supply are hard to work up to 20GHz.In order to achieve the unification of low voltage, low power and super high speed, the article applies an improved common-gate structure dynamic load latch. Based on this latch, design and realize a 1:4 super high speed frequency divider in TSMC 0.18μm CMOS process.On-wafer experimental results show its highest work rate can be up to 26GHz, and its work range is over 20GHz; Package experimental results show the chip can work up to 19.6GHz and performs well in 10GHz which is the desired work rate. The article also accomplishes the simulation and layout design of a 1.2V 10Gb/s 10mW 1:4 Demux based the same process, the chip will be sent to foundry in the next MPW project, and subsequently be tested on wafer.
The article presents the basic principle of Demux and frequency divider, and describes the design flow in detail by the sequence of circuit design, layout design and chip test. Finally, the paper gives the test results of the 1:4 super high speed frequency divider. The on-wafer and package measurement results of the chipset show that the low voltage, low power, super high speed frequency divider works well and totally meet the task of the design. The chip has the bright future in industrialization.
本论文的主要目标是,采用特征频率仅为49GHz的0.18μm CMOS工艺,分析、研究并实现工作频率超过20GHz的1:4超高速分频电路以及采用相同工艺,分析、研究符合STM-64(9.952Gb/s)级别的低电压、低功耗1:4分接器,并在下一次MPW完成投片及测试工作。为了使电路性能达到低电压、低功耗与超高速的统一,本文采用一种改进型共栅结构的动态负载锁存器。基于该锁存器,设计并实现了超高速1:4分频器。在片测试结果表明:其最高工作速率可达26GHz,分频范围超过20GHz;封装后的测试结果表明:其最高工作速率达19.6GHz,且在预期的10GHz工作频率获得了较为理想的输出信号。本文同时采用同种工艺在1.2V的电源电压下完成了10Gb/s 1:4分接器的仿真和版图设计,后仿真结果表明其完全达到设计指标,且核心功耗仅为10mW。该芯片将于下次MPW中投片、完成测试。
本论文给出了分接器电路及分频器电路的基本原理并以电路设计、版图设计、芯片测试的顺序详细介绍了电路的设计流程及1:4超高速分频器的测试结果。在片测试及封装测试结果表明,采用该方案实现的低电压、低功耗、超高速分频器性能优良,完全达到设计要求,为产业化积累了经验,做出了贡献。
Several characteristics and trends, such as network, digital, intelligence and low power present during the innovation and development of IT industry. High speed, broad band communication network are required to communicate information. For these reason, Optical communication will gradually replace cable communication. In optical transmission system, Demultiplexer(Demux) is at the tail end of the optic-fiber receiver. Demux transforms the one way high speed serial signal which from data decision to N (N>1) way low speed parallel signal. Therefore, Demux is an important part of high speed communication system, its performance directly influence the last output signal. So, high speed Demux circuit is the indispensable key circuit in optical communication. Additionally, super high speed frequency dividers are widely applied in optical communication and wireless communication system. In a Demux, frequency divider converts the high speed clock to the lower speed clock. In the case, frequency divider is one of the circuits working on the highest frequency. With the development of CMOS process, design of super high speed frequency divider based on CMOS process makes great sense.
The article's main objective is to analyze, research and realize a super high speed frequency divider circuit based on 0.18μm CMOS process, and the circuit's work rate is over 20GHz.And based on the same process, analyze, research a low voltage, low power 1:4 Demux applying for STM-64, the chip will be sent to foundry in the next MPW project, and subsequently be tested on wafer. Since the standard voltage in 0.18μm CMOS process is 1.8V, and f t is 49GHz, in 1.2V, traditional circuit structures are hard to work up to 10Gb/s, similarly, the traditional ones in 1.8V power supply are hard to work up to 20GHz.In order to achieve the unification of low voltage, low power and super high speed, the article applies an improved common-gate structure dynamic load latch. Based on this latch, design and realize a 1:4 super high speed frequency divider in TSMC 0.18μm CMOS process.On-wafer experimental results show its highest work rate can be up to 26GHz, and its work range is over 20GHz; Package experimental results show the chip can work up to 19.6GHz and performs well in 10GHz which is the desired work rate. The article also accomplishes the simulation and layout design of a 1.2V 10Gb/s 10mW 1:4 Demux based the same process, the chip will be sent to foundry in the next MPW project, and subsequently be tested on wafer.
The article presents the basic principle of Demux and frequency divider, and describes the design flow in detail by the sequence of circuit design, layout design and chip test. Finally, the paper gives the test results of the 1:4 super high speed frequency divider. The on-wafer and package measurement results of the chipset show that the low voltage, low power, super high speed frequency divider works well and totally meet the task of the design. The chip has the bright future in industrialization.
引文
[1] 纪越峰 赵荣华 顾畹仪 李国瑞“光纤数字通信实用基础” 科学文献技术出版社
[2] 赵梓森等 中国通信学会主编 “光纤通信工程(修订本)” 人民邮电出版社
[3] 王志功编著,“光纤通信集成电路设计”,高等教育出版社,2003 年 6 月
[1] R.L.Miller, “Fractional-Fractional-Frequency Generators Utilizing Regenerative Modulation”, Proc. IRE, vol. 27, pp. 446-456, July 1939
[2] J. Lee, B. Razavi, “A 40-GHz Frequency Divider in 0.18-μm CMOS Technology”. IEEE J Solid-State Circuits, VOL. 39, NO. 4, pp. 594 – 601, Apr. 2004
[3] 王欢,王志功,冯军等“12-GHz 0.25μm CMOS 1:2 动态分频器” 高技术通讯, pp. 45-50, 2003, 8
[4] Lu Jianhua,Wang Zhigong et al,”An 8.5GHz 1:8 Frequency Divider in 0.35μm CMOS Technology” 半导体学报,pp.17-29, 2003.4
[5] Z. Gu, A. Thiede. “18-GHz low-power CMOS static frequency divider”. Electronics Letters, VOL.39, NO.20, pp.1433-1434, Oct 2003
[6] Fang W, Brunnschweiler A, Ashburn P. “An Analytical Maximum Toggle Frequency Expression and its Application to Optimizing High-Speed ECL Frequency Dividers”, IEEE J. Solid-State Circuits, vol. 25, pp. 920-931,1990
[7] HongMo Wang, “A 1.8V 3mW 16.8GHz Frequency Divider in 0.25μm CMOS”, IEEE International Solid-State Circuits Conference, pp. 196-197, 2000
[8] 曾晓军,李天望,洪志良 “1V,19GHz CMOS 分频器设计” 半导体学报,pp. 416-419, 2003, 4
[9] 谢嘉奎,宣月清,冯军. 电子线路(线性部分)(第四版)[M]. 北京:高等教育出版社,pp. 90, 1999
[10] 王志功,沈永朝,黄颋 VLSI 设计讲义[Z]. 南京:东南大学无线电系,pp.33,2001
[11] Joseph M.C. Wong, Vincent S.L. Cheung, Howard C. Luong. “A 1-V 2.5-mW 5.3-GHz Frequency Divider in a 0.35- m CMOS Process”. IEEE J. Solid-State Circuits, vol. 38, pp. 1643-1648, 2003.
[12] 谢嘉奎,宣月清,冯军. 电子线路(线性部分)(第四版)[M]. 北京:高等教育出版社,pp. 143,1999
[13] Behzad Razavi. Design of Analog CMOS Integrated Circuits [M]. McGraw-Hill International Edition. pp. 67-76, 2001
[1] 曾智龙等 “三种复用技术的比较” 飞通光电子技术 2001 第二卷第三期
[2] 田磊 “0.25μm CMOS 10Gb/s 高速分接器设计” 2001.5
[3] 王志功编著,“光纤通信集成电路设计”,高等教育出版社,2003 年 6 月
[4] Akira Tanabe, Yasushi Nakahara, Akio Furukawa, and Tohru Mogami,” A Redundant Multivalued Logic for a 10-Gb/s CMOS Demultiplexer IC” in IEEE Journal of solid-state circuits, vol. 38, no. 1, Jan 2003
[5] Behzad Razavi,模拟 CMOS 集成电路设计,西安交通大学出版社,2003,pp 340
[6] Jan M. Raby, Digital Integrated Circuits-A Design Perspective, 清华大学出版社 Prentice Hall International ,Inc. 1999
[7] Akira Tanabe,Masato Umetani, et al, “0.18μm CMOS 10Gb/s Multiplexer/Demultiplexer Ics Using Current Mode Logic with Tolerance Threshold Voltage Fluctuation,”in IEEE Journal of solid-state circuits,vol.36, no.6,Jun 2001
[8] Daniel Kehrer,Hans-Dieter Wohlmuth,Herbert Knapp,et al, “40Gb/s 2:1 Multiplexer and 1:2 Demultiplexer in 120nm CMOS,” 2003 IEEE International Solid-State Circuits Conference
[9] 卢文才,CMOS 1:4 分接器的设计[硕士论文],东南大学,2003
[1] Ullan, M.; Lozano, M.; Campabadal, F.; Fleta, C.; Garcia, C.; Gonzalez, F.; Bernabeu, J.; “High Pitch Metal-On-Glass Technology For Pad Pitch Adaptation Between Detectors And Readout Electronics” in Nuclear Science, IEEE Transactions on Volume 51, Issue 3, Part 3, June 2004 Page(s):968 - 974
[2] Ming-Dou Ker, Hsin-Chin Jiang, and Chyh-Yih Chang “Design on the Low-Capacitance Bond Pad for High-Frequency I/O Circuits in CMOS Technology” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001
[3] C. C. Hsue and S. C. Chien, “Polycide bonding pad structure,” U.S.Patent 5 734 200, Mar. 1998
[4] Alan Hastings,模拟电路版图的艺术(影印版)清华大学出版社
[5] Pinping Sun; Yong Lian; Ajjikuttira, A.B.” A 10-Gb/s, 1.5-Volt low-power 1:4 demultiplexer for optical fiber communication” in ASIC, 2003. Proceedings. 5th International Conference on Volume 2, 21-24 Oct. 2003 Page(s):1082 - 1085 Vol.2
[6] Akira Tanabe, Yasushi Nakahara, Akio Furukawa, and Tohru Mogami,” A Redundant Multivalued Logic for a 10-Gb/s CMOS Demultiplexer IC” in IEEE Journal of solid-state circuits, vol. 38, no. 1, Jan 2003
[2] 赵梓森等 中国通信学会主编 “光纤通信工程(修订本)” 人民邮电出版社
[3] 王志功编著,“光纤通信集成电路设计”,高等教育出版社,2003 年 6 月
[1] R.L.Miller, “Fractional-Fractional-Frequency Generators Utilizing Regenerative Modulation”, Proc. IRE, vol. 27, pp. 446-456, July 1939
[2] J. Lee, B. Razavi, “A 40-GHz Frequency Divider in 0.18-μm CMOS Technology”. IEEE J Solid-State Circuits, VOL. 39, NO. 4, pp. 594 – 601, Apr. 2004
[3] 王欢,王志功,冯军等“12-GHz 0.25μm CMOS 1:2 动态分频器” 高技术通讯, pp. 45-50, 2003, 8
[4] Lu Jianhua,Wang Zhigong et al,”An 8.5GHz 1:8 Frequency Divider in 0.35μm CMOS Technology” 半导体学报,pp.17-29, 2003.4
[5] Z. Gu, A. Thiede. “18-GHz low-power CMOS static frequency divider”. Electronics Letters, VOL.39, NO.20, pp.1433-1434, Oct 2003
[6] Fang W, Brunnschweiler A, Ashburn P. “An Analytical Maximum Toggle Frequency Expression and its Application to Optimizing High-Speed ECL Frequency Dividers”, IEEE J. Solid-State Circuits, vol. 25, pp. 920-931,1990
[7] HongMo Wang, “A 1.8V 3mW 16.8GHz Frequency Divider in 0.25μm CMOS”, IEEE International Solid-State Circuits Conference, pp. 196-197, 2000
[8] 曾晓军,李天望,洪志良 “1V,19GHz CMOS 分频器设计” 半导体学报,pp. 416-419, 2003, 4
[9] 谢嘉奎,宣月清,冯军. 电子线路(线性部分)(第四版)[M]. 北京:高等教育出版社,pp. 90, 1999
[10] 王志功,沈永朝,黄颋 VLSI 设计讲义[Z]. 南京:东南大学无线电系,pp.33,2001
[11] Joseph M.C. Wong, Vincent S.L. Cheung, Howard C. Luong. “A 1-V 2.5-mW 5.3-GHz Frequency Divider in a 0.35- m CMOS Process”. IEEE J. Solid-State Circuits, vol. 38, pp. 1643-1648, 2003.
[12] 谢嘉奎,宣月清,冯军. 电子线路(线性部分)(第四版)[M]. 北京:高等教育出版社,pp. 143,1999
[13] Behzad Razavi. Design of Analog CMOS Integrated Circuits [M]. McGraw-Hill International Edition. pp. 67-76, 2001
[1] 曾智龙等 “三种复用技术的比较” 飞通光电子技术 2001 第二卷第三期
[2] 田磊 “0.25μm CMOS 10Gb/s 高速分接器设计” 2001.5
[3] 王志功编著,“光纤通信集成电路设计”,高等教育出版社,2003 年 6 月
[4] Akira Tanabe, Yasushi Nakahara, Akio Furukawa, and Tohru Mogami,” A Redundant Multivalued Logic for a 10-Gb/s CMOS Demultiplexer IC” in IEEE Journal of solid-state circuits, vol. 38, no. 1, Jan 2003
[5] Behzad Razavi,模拟 CMOS 集成电路设计,西安交通大学出版社,2003,pp 340
[6] Jan M. Raby, Digital Integrated Circuits-A Design Perspective, 清华大学出版社 Prentice Hall International ,Inc. 1999
[7] Akira Tanabe,Masato Umetani, et al, “0.18μm CMOS 10Gb/s Multiplexer/Demultiplexer Ics Using Current Mode Logic with Tolerance Threshold Voltage Fluctuation,”in IEEE Journal of solid-state circuits,vol.36, no.6,Jun 2001
[8] Daniel Kehrer,Hans-Dieter Wohlmuth,Herbert Knapp,et al, “40Gb/s 2:1 Multiplexer and 1:2 Demultiplexer in 120nm CMOS,” 2003 IEEE International Solid-State Circuits Conference
[9] 卢文才,CMOS 1:4 分接器的设计[硕士论文],东南大学,2003
[1] Ullan, M.; Lozano, M.; Campabadal, F.; Fleta, C.; Garcia, C.; Gonzalez, F.; Bernabeu, J.; “High Pitch Metal-On-Glass Technology For Pad Pitch Adaptation Between Detectors And Readout Electronics” in Nuclear Science, IEEE Transactions on Volume 51, Issue 3, Part 3, June 2004 Page(s):968 - 974
[2] Ming-Dou Ker, Hsin-Chin Jiang, and Chyh-Yih Chang “Design on the Low-Capacitance Bond Pad for High-Frequency I/O Circuits in CMOS Technology” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001
[3] C. C. Hsue and S. C. Chien, “Polycide bonding pad structure,” U.S.Patent 5 734 200, Mar. 1998
[4] Alan Hastings,模拟电路版图的艺术(影印版)清华大学出版社
[5] Pinping Sun; Yong Lian; Ajjikuttira, A.B.” A 10-Gb/s, 1.5-Volt low-power 1:4 demultiplexer for optical fiber communication” in ASIC, 2003. Proceedings. 5th International Conference on Volume 2, 21-24 Oct. 2003 Page(s):1082 - 1085 Vol.2
[6] Akira Tanabe, Yasushi Nakahara, Akio Furukawa, and Tohru Mogami,” A Redundant Multivalued Logic for a 10-Gb/s CMOS Demultiplexer IC” in IEEE Journal of solid-state circuits, vol. 38, no. 1, Jan 2003