高速可复用SPI总线的设计与Verilog HDL实现
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摘要
相对于并行总线,串行总线具有结构简单的优点。近年来人们对系统功能和性能的需求不断增长使得处理器需要的外设越来越多,这时串行总线相比于并行总线结构简单这一优点就逐渐显现出来了,因此应用范围也越来越广泛。
SPI (Serial Peripheral Interface)串行外设接口总线是一种3线同步全双工串行通信接口总线,在很多新型器件如LCD模块、FLASH、EEPROM存储器、数据输入、输出设备上都采用了SPI接口。但是在很多场合,微控制器或微处理器本身又不具有SPI接口,给数据传输带来不便。在FPGA技术发展迅速的时代,解决这个问题最方便的办法就是集成一个SPI核到芯片上。
本文的工作就是根据业界通用的SPI总线的标准,设计一种可复用的高速SPI总线。设计过程中很多变量都采用参数形式,具体应用于工程实践时根据实际需要更改参数即可,充分体现了可复用性。
由于SPI本身没有应答机制,对传输时序要求比较严格,所以就需要一个稳定可靠的同步时钟。针对这种需要,本文工作中特别设计了一个对奇偶分频分别考虑的时钟生成模块提供可靠的同步串行时钟。
执行串并转换功能的数据传输模块结构简单,消耗硬件资源少,但却有很强的功能,如:每次最高传输多少位数据可选,最高值为128;传输速度快,属于遵守SPI协议的同类器件里速度较快的。
设计思想用Verilog HDL语言实现,借助QuartusП做电路修正,在ModelSim仿真软件上仿真验证通过,达到高速可复用的要求。
Compared with parallel buses, the advantage of serial buses is that their structure of circuit is more simple. Recently, increasing with the requirement of the functions and performances of devices, the demand for multiple peripherals microprocessor is enhanced. Thus, serial buses have an extensive application in this aspect.
SPI (Serial Peripheral Interface) is a 3 line synchronous full-duplex serial communication interface bus. Many devices such as LCD, FLASH, EEPROM, Input/Output devices, adopt SPI. However, in many other aspects, microcontroller and microprocessor have no SPI interface, the shortcut is to integrate an SPI core to the chip.
In this thesis, a high speed reusable SPI bus is designed based on the universal SPI specification. In the design, the variables are supposed to be parameters, which can be altered easily in the project (application), embodies the reusability sufficiently.
Due to the lack of responsion mechanism, SPI calls for strict timing order. Thus a special clock-generate model including divider of even and odd integer is designed, which can generate a stable and reliable synchronous serial clock.
The spi_shift model, which performs parallel data conversion for serial and reverse direction, has a simple circuit. Although it needs only a few hardware, it is characterized with strong function, for example, the maximum bit of each transfer is variable, up to 128; the transmission speed is faster than other components based on SPI specification.
The algorithm of the high speed reusable SPI is implemented with Verilog HDL, adjusted with QuartusП, simulated and verified with ModelSim finally.
SPI (Serial Peripheral Interface)串行外设接口总线是一种3线同步全双工串行通信接口总线,在很多新型器件如LCD模块、FLASH、EEPROM存储器、数据输入、输出设备上都采用了SPI接口。但是在很多场合,微控制器或微处理器本身又不具有SPI接口,给数据传输带来不便。在FPGA技术发展迅速的时代,解决这个问题最方便的办法就是集成一个SPI核到芯片上。
本文的工作就是根据业界通用的SPI总线的标准,设计一种可复用的高速SPI总线。设计过程中很多变量都采用参数形式,具体应用于工程实践时根据实际需要更改参数即可,充分体现了可复用性。
由于SPI本身没有应答机制,对传输时序要求比较严格,所以就需要一个稳定可靠的同步时钟。针对这种需要,本文工作中特别设计了一个对奇偶分频分别考虑的时钟生成模块提供可靠的同步串行时钟。
执行串并转换功能的数据传输模块结构简单,消耗硬件资源少,但却有很强的功能,如:每次最高传输多少位数据可选,最高值为128;传输速度快,属于遵守SPI协议的同类器件里速度较快的。
设计思想用Verilog HDL语言实现,借助QuartusП做电路修正,在ModelSim仿真软件上仿真验证通过,达到高速可复用的要求。
Compared with parallel buses, the advantage of serial buses is that their structure of circuit is more simple. Recently, increasing with the requirement of the functions and performances of devices, the demand for multiple peripherals microprocessor is enhanced. Thus, serial buses have an extensive application in this aspect.
SPI (Serial Peripheral Interface) is a 3 line synchronous full-duplex serial communication interface bus. Many devices such as LCD, FLASH, EEPROM, Input/Output devices, adopt SPI. However, in many other aspects, microcontroller and microprocessor have no SPI interface, the shortcut is to integrate an SPI core to the chip.
In this thesis, a high speed reusable SPI bus is designed based on the universal SPI specification. In the design, the variables are supposed to be parameters, which can be altered easily in the project (application), embodies the reusability sufficiently.
Due to the lack of responsion mechanism, SPI calls for strict timing order. Thus a special clock-generate model including divider of even and odd integer is designed, which can generate a stable and reliable synchronous serial clock.
The spi_shift model, which performs parallel data conversion for serial and reverse direction, has a simple circuit. Although it needs only a few hardware, it is characterized with strong function, for example, the maximum bit of each transfer is variable, up to 128; the transmission speed is faster than other components based on SPI specification.
The algorithm of the high speed reusable SPI is implemented with Verilog HDL, adjusted with QuartusП, simulated and verified with ModelSim finally.
引文
[1] Michael Keating and Pierre Bricaud, Reuse Methodology Manual for System-on-a-Chips Designs, Kluwer Academic Publishers, 1999.
[2] www.eepw.com.cn,SOC 设计复杂性以及IP 复用方法.
[3] 李加元等,系统芯片设计中的可复用IP 技术。半导体技术,2004,31(1):15-17
[4] http: // www. eetc. globalsources. Com, Lesley Shannon.半导体产业IP 复用现状概述[EB/ OL]. 2004.1.31.
[5] Bricaud P J. IP reuse creation for system-on-a-chip design. Proceedings of the IEEE Custom Integrated Circuits, 1999, 395-401.
[6] Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores Revision B3 [M]. Silicore Corporation, 2001.
[7] 陆思安,可复用IP 核以及系统芯片SOC 的测试结构研究。浙江大学博士论文,2003:8-10.
[8] 高谷刚,罗春,可复用SPI 模块IP 核的设计与验证,单片机与嵌入式系统应用,2004(11):5-8.
[9] Jozwiak L. Quality-driven system-on-chip design. IEEE 2000 First International Symposium on Quality Electronic Design, 2000, 93-102.
[10] Proceeding of Workshop and IEEE EDS Minicolloquium on Nanometer CMOS Technology, IEEE EDS Shanghai Chapter, Fudan University, Shanghai, 2002.
[11] 杨之廉,申明超大规模集成电路设计方法学导论(第二版)。清华大学出版社,1999:7-9.
[12] 张军峰,王占领,基于EDA 技术的FPGA 设计。电子与电脑,2006(2):45-47.
[13] 王维博,吴自恒,用 FPGA/CPLD 实现 EDA 设计。四川工业学院学报,2004,23(2):6-8.
[14] 明导公司SOC 集成电路设计的新纪元。半导体技术, 2001,29(7):17-20.
[15] 孟宪元,王庆海,FPGA 的发展新动向。IC 与元器件,2002:68-70.
[16] www.opencore.org, Simon Srot, SPI Master Core Specification, Rev.0.6, May 16, 2007.
[17] 易志明,林凌,郝丽宏,李树靖,SPI串行总线接口及其实现。自动化与仪器仪表,2002(6):45-48.
[18] www.gecmag.com, Steve Logan, 可控制多种外设的 SPI/I2C 总线.
[19] 李宽余,戴瑜兴,张义兵,基于可编程逻辑器件的串行外设接口设计及实现。低压器件,2004(11):28-30.
[1] 尤一鸣等,单片机总线扩展技术。北京航空航天大学出版社,1994:5～7.
[2] http://blog.csdn.net/eternalee/archive/2001/10/19/5336.aspx.
[3] 陈穗光,葛建华,I2C 总线接口协议设计及 FPGA 的实现,山西电子技术,2006(6):37-38.
[4] The I2C-Bus Specification, Version 2.1, January, 2000: 4.
[5] 吴明辉,基于 ARM 的嵌入式系统开发与应用。人民邮电出版社,2004(6):199.
[6] Steve Logan, SPI/I2C Bus Controlling Multiple Sorts of Peripheral, 世界电子元器件,2006(9):54-59.
[7] 池峰,常越,用嵌入式系统的 SPI 模块实现 I2C 总线通信,单片机与嵌入式系统应用,2003(11):75-76.
[8] 居水荣,单片微控制器的功能集成方向(四),微电子技术,2002(4):24-26.
[9] 胡纪阳,BITBUS 网络模板及通信软件分析与开发,通信技术,1994(4):53-55.
[10] http://www.61ic.com/MCU/MCU/sq/200701/11269.html 姚成虎,同步串行总线接口扩展,工业仪表与自动化装置,2004(2):6-10.
[11] 孙天泽,付晓江,袁文菊,SPI 串行总线在嵌入式 Linux 系统中的编程实现,微电子学与计算机,2003(4):52-55.
[12] 罗宏浩,刘少克,MICROWIRE 总线与 SPI 总线的接口设计与应用,计算机测量与控制 2004(3):278-279.
[1] www.gecmag.com Steve Logan,可控制多种外设的 SPI/I2C 总线。世界电子元器件.
[2] www.opencore.org Simon Srot, SPI Master Core Specification, Rev.0.6, May 16, 2007.
[3] www.opencore.org Richard Herveille, Combining WISHBONE interface signals Application note, Rev.0.2, April 18, 2001.
[4] BASCOM-AVR Version1.11.7.4, 56-61.
[5] Xilinx Limited. Cool Runner- II Serial Peripheral Interface Master, 2002.
[6] 张泉,片上总线 WISHBONE 的 Verilog HDL 实现。硕士学位论文,同济大学,2005:21-22.
[7] Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores Revision B3 [M]. Silicore Corporation, 2001.
[8] Wishbone Frequently Asked Questions (FAQ).
[9] 方承志,李元,李明栋,用于嵌入式系统多路 SPI Master 接口设计。电子测量技术,2004(2):17-19.
[10] Jan M. Rabaey, 数字集成电路-设计透视(影印版)。清华大学出版社,1998:18-23.
[11] 梁祥,封吉平,安学军,基于 PC104 总线与 CPLD 的 SPI 接口设计。微计算机信息(嵌入式与 SOC),2005,21(12-2):5-7.
[1] 何永泰,基于CPLD的SPI接口设计。电脑开发与应用,2004,17(10):27～28.
[2] Muraoka, michiaki, Nishi, Hiroaki, et al. design methodology for SoC architectures based on reusable virtual cores, proceedings of the asia and south pacific design automation conference, ASP-DAC, proceedings of the ASP-DAC 2004 asia and south pacific design automation conference-2004, 2004:256-262.
[3] 唐杉等,数字IC设计:方法、技巧与实践。机械工业出版社,2006:123～129.
[4] 夏宇闻,Verilog 数字系统设计教程。北京航空航天大学出版社,2003.
[5] www.opencore.org/spi_master.
[6] I. I. Viscor, Gray counter in VHDL[J]. Proceedings of the Student FEI 2000, Brno 2000:399-401.
[7] 张剑宇,孙承绶,来金梅,章倩苓,2.4GHz频率合成器可编程分频器设计与实现。复旦学报(自然科学版),2005(1):44-45.
[8] Mohit Arora Clock Divider Made Easy. Synopsys Users Group, Boston, 2002.
[9] Emnett F, Biegel M. Power Reduction Through RTL Clock Gating. Synopsys Users Group, San Jose, 2000.
[1] X.R. Zheng, W.L. Deng, J. M. Fan, G. H. Chen, X. W. Lin, An IP Simulation and Verification Platform Based on FPGA, Journal of South China University of Technology (Natural Science Edition) 2006, Vol. 34 No.1:38~42.
[2] http://training.chinaecnet.com, FPGA器件的仿真验证、设计约束、时序分析与状态机设计技巧.
[3] 胡军强,李津生,洪佩琳,基于Modelsim FLI接口的FPGA仿真技术。电子技术应用,2002(07):26～29.
[2] www.eepw.com.cn,SOC 设计复杂性以及IP 复用方法.
[3] 李加元等,系统芯片设计中的可复用IP 技术。半导体技术,2004,31(1):15-17
[4] http: // www. eetc. globalsources. Com, Lesley Shannon.半导体产业IP 复用现状概述[EB/ OL]. 2004.1.31.
[5] Bricaud P J. IP reuse creation for system-on-a-chip design. Proceedings of the IEEE Custom Integrated Circuits, 1999, 395-401.
[6] Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores Revision B3 [M]. Silicore Corporation, 2001.
[7] 陆思安,可复用IP 核以及系统芯片SOC 的测试结构研究。浙江大学博士论文,2003:8-10.
[8] 高谷刚,罗春,可复用SPI 模块IP 核的设计与验证,单片机与嵌入式系统应用,2004(11):5-8.
[9] Jozwiak L. Quality-driven system-on-chip design. IEEE 2000 First International Symposium on Quality Electronic Design, 2000, 93-102.
[10] Proceeding of Workshop and IEEE EDS Minicolloquium on Nanometer CMOS Technology, IEEE EDS Shanghai Chapter, Fudan University, Shanghai, 2002.
[11] 杨之廉,申明超大规模集成电路设计方法学导论(第二版)。清华大学出版社,1999:7-9.
[12] 张军峰,王占领,基于EDA 技术的FPGA 设计。电子与电脑,2006(2):45-47.
[13] 王维博,吴自恒,用 FPGA/CPLD 实现 EDA 设计。四川工业学院学报,2004,23(2):6-8.
[14] 明导公司SOC 集成电路设计的新纪元。半导体技术, 2001,29(7):17-20.
[15] 孟宪元,王庆海,FPGA 的发展新动向。IC 与元器件,2002:68-70.
[16] www.opencore.org, Simon Srot, SPI Master Core Specification, Rev.0.6, May 16, 2007.
[17] 易志明,林凌,郝丽宏,李树靖,SPI串行总线接口及其实现。自动化与仪器仪表,2002(6):45-48.
[18] www.gecmag.com, Steve Logan, 可控制多种外设的 SPI/I2C 总线.
[19] 李宽余,戴瑜兴,张义兵,基于可编程逻辑器件的串行外设接口设计及实现。低压器件,2004(11):28-30.
[1] 尤一鸣等,单片机总线扩展技术。北京航空航天大学出版社,1994:5～7.
[2] http://blog.csdn.net/eternalee/archive/2001/10/19/5336.aspx.
[3] 陈穗光,葛建华,I2C 总线接口协议设计及 FPGA 的实现,山西电子技术,2006(6):37-38.
[4] The I2C-Bus Specification, Version 2.1, January, 2000: 4.
[5] 吴明辉,基于 ARM 的嵌入式系统开发与应用。人民邮电出版社,2004(6):199.
[6] Steve Logan, SPI/I2C Bus Controlling Multiple Sorts of Peripheral, 世界电子元器件,2006(9):54-59.
[7] 池峰,常越,用嵌入式系统的 SPI 模块实现 I2C 总线通信,单片机与嵌入式系统应用,2003(11):75-76.
[8] 居水荣,单片微控制器的功能集成方向(四),微电子技术,2002(4):24-26.
[9] 胡纪阳,BITBUS 网络模板及通信软件分析与开发,通信技术,1994(4):53-55.
[10] http://www.61ic.com/MCU/MCU/sq/200701/11269.html 姚成虎,同步串行总线接口扩展,工业仪表与自动化装置,2004(2):6-10.
[11] 孙天泽,付晓江,袁文菊,SPI 串行总线在嵌入式 Linux 系统中的编程实现,微电子学与计算机,2003(4):52-55.
[12] 罗宏浩,刘少克,MICROWIRE 总线与 SPI 总线的接口设计与应用,计算机测量与控制 2004(3):278-279.
[1] www.gecmag.com Steve Logan,可控制多种外设的 SPI/I2C 总线。世界电子元器件.
[2] www.opencore.org Simon Srot, SPI Master Core Specification, Rev.0.6, May 16, 2007.
[3] www.opencore.org Richard Herveille, Combining WISHBONE interface signals Application note, Rev.0.2, April 18, 2001.
[4] BASCOM-AVR Version1.11.7.4, 56-61.
[5] Xilinx Limited. Cool Runner- II Serial Peripheral Interface Master, 2002.
[6] 张泉,片上总线 WISHBONE 的 Verilog HDL 实现。硕士学位论文,同济大学,2005:21-22.
[7] Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores Revision B3 [M]. Silicore Corporation, 2001.
[8] Wishbone Frequently Asked Questions (FAQ).
[9] 方承志,李元,李明栋,用于嵌入式系统多路 SPI Master 接口设计。电子测量技术,2004(2):17-19.
[10] Jan M. Rabaey, 数字集成电路-设计透视(影印版)。清华大学出版社,1998:18-23.
[11] 梁祥,封吉平,安学军,基于 PC104 总线与 CPLD 的 SPI 接口设计。微计算机信息(嵌入式与 SOC),2005,21(12-2):5-7.
[1] 何永泰,基于CPLD的SPI接口设计。电脑开发与应用,2004,17(10):27～28.
[2] Muraoka, michiaki, Nishi, Hiroaki, et al. design methodology for SoC architectures based on reusable virtual cores, proceedings of the asia and south pacific design automation conference, ASP-DAC, proceedings of the ASP-DAC 2004 asia and south pacific design automation conference-2004, 2004:256-262.
[3] 唐杉等,数字IC设计:方法、技巧与实践。机械工业出版社,2006:123～129.
[4] 夏宇闻,Verilog 数字系统设计教程。北京航空航天大学出版社,2003.
[5] www.opencore.org/spi_master.
[6] I. I. Viscor, Gray counter in VHDL[J]. Proceedings of the Student FEI 2000, Brno 2000:399-401.
[7] 张剑宇,孙承绶,来金梅,章倩苓,2.4GHz频率合成器可编程分频器设计与实现。复旦学报(自然科学版),2005(1):44-45.
[8] Mohit Arora Clock Divider Made Easy. Synopsys Users Group, Boston, 2002.
[9] Emnett F, Biegel M. Power Reduction Through RTL Clock Gating. Synopsys Users Group, San Jose, 2000.
[1] X.R. Zheng, W.L. Deng, J. M. Fan, G. H. Chen, X. W. Lin, An IP Simulation and Verification Platform Based on FPGA, Journal of South China University of Technology (Natural Science Edition) 2006, Vol. 34 No.1:38~42.
[2] http://training.chinaecnet.com, FPGA器件的仿真验证、设计约束、时序分析与状态机设计技巧.
[3] 胡军强,李津生,洪佩琳,基于Modelsim FLI接口的FPGA仿真技术。电子技术应用,2002(07):26～29.