OFDM系统中高性能LDPC码解码器的研究与实现
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摘要
随着多媒体广播、蜂窝通信、VLSI技术不断向前发展,移动用户数量和业务成指数关系增长。下一代通信系统必然具有大容量、高速度以及低功耗的特点。由于全球无线电环境千变万化,各种标准层出不穷,多模式可配置移动终端是大势所趋。为了保证传输的可靠性,FEC码获得了高速发展和广泛应用。作为最接近香农极限的FEC码,LDPC码被广泛应用于DVB-S2、DTMB、CMMB、WLAN、WiMAX等系统中。因此,设计高性能LDPC码解码器是当前研究热点之一。
由于存在大量的并行计算、存储器读写访问以及寄存器翻转,高速LDPC码解码器的功耗和面积都比较大。而提高并行度会带来很多问题,诸如数据相关性、可配置性以及存储器访问冲突等。本论文针对不同应用环境设计LDPC码解码器,解决高并行度带来的相关问题,优化它们的功耗和面积,提高它们的可配置性。
通过加快算法收敛速度、横向更新和纵向更新完全交叠、双通道并行计算、以及深度流水线等关键技术,解码器的吞吐率得到进一步提高。通过减少存储器访问、动态门控时钟、提前终止策略以及并行和流水线处理等关键技术,进一步降低了解码器的功耗。通过降低计算复杂度、减少存储器资源、优化存储器结构以及提高利用率等关键技术,进一步减小了解码器的面积。
基于以上关键技术的研究,设计并实现了四块不同并行度的解码器Ⅰ、Ⅱ、Ⅲ和Ⅳ。解码器Ⅰ和Ⅱ的吞吐率达到100Mb/s,适合于DTMB和CMMB等多媒体广播系统；解码器Ⅲ和Ⅳ的吞吐率大于250Mb/s,适合于WiMAX和4G等高速蜂窝移动通信系统。所有以上关键技术和方法都通过了解码器芯片的验证和测试。
With rapid developments of multimedia broadcasting, celluar communication, and VLSI technology, mobile users and services grow at an exponential rate.The next generation of communication system must feature large capacity, high speed, and lower power. Due to changing radio environments and diverse standards, multi-mode configurable mobile terminals are in demand. To insure reliable transmission, FEC codes get fast developments and wide applications. LDPC code, close to Shannon limit, is widely applied in the DVB-S2, DTMB, CMMB, WLAN, WiMAX, etc. Therefore, designing high-performance LDPC decoder is now one of the hotspots.
Due to mass parallel computing, memory read-write accesses, and register overturns, high-speed LDPC decoders feature high power and large area. Improving parallel degree results many problems, such as data dependency, configurability, memory access conflicts, etc. Based on different applications, the dissertation designs several LDPC decoders, solves the problems from high parallel degree, optimizes their power consumption and area, and boosts their configurability. The main contributions of the dissertation include the following aspects.
With key techniques of speeding up decoding convergency, two-phase fully overlapping, dual-path parallel computing, and deep pipelining, the decoders' throughputs are improved further. With key techniques of memory access reduction, dynamic clock gating, early termination strategy, and parallel and pipelining, the decoders'powers are lowered further. With key techniques of computing complexity and memory resource reduction, memory structure optimization, and utilization ratio improvement, the decoders'areas are much smaller.
Based on the study of the above key techniques, four decodersⅠ,Ⅱ,Ⅲ, andⅣwith different parallel degrees are designed and implemented. DecodersⅠandⅡattain about 100Mb/s and are fit for the multimedia broadcasting systems:DTMB and CMMB; DecodersⅢandⅣattain>250Mb/s and are fit for the high-speed celluar mobile communication system:WiMAX and 4G. All the key techniques and methods are tested and verified in the decoder chips.
由于存在大量的并行计算、存储器读写访问以及寄存器翻转,高速LDPC码解码器的功耗和面积都比较大。而提高并行度会带来很多问题,诸如数据相关性、可配置性以及存储器访问冲突等。本论文针对不同应用环境设计LDPC码解码器,解决高并行度带来的相关问题,优化它们的功耗和面积,提高它们的可配置性。
通过加快算法收敛速度、横向更新和纵向更新完全交叠、双通道并行计算、以及深度流水线等关键技术,解码器的吞吐率得到进一步提高。通过减少存储器访问、动态门控时钟、提前终止策略以及并行和流水线处理等关键技术,进一步降低了解码器的功耗。通过降低计算复杂度、减少存储器资源、优化存储器结构以及提高利用率等关键技术,进一步减小了解码器的面积。
基于以上关键技术的研究,设计并实现了四块不同并行度的解码器Ⅰ、Ⅱ、Ⅲ和Ⅳ。解码器Ⅰ和Ⅱ的吞吐率达到100Mb/s,适合于DTMB和CMMB等多媒体广播系统；解码器Ⅲ和Ⅳ的吞吐率大于250Mb/s,适合于WiMAX和4G等高速蜂窝移动通信系统。所有以上关键技术和方法都通过了解码器芯片的验证和测试。
With rapid developments of multimedia broadcasting, celluar communication, and VLSI technology, mobile users and services grow at an exponential rate.The next generation of communication system must feature large capacity, high speed, and lower power. Due to changing radio environments and diverse standards, multi-mode configurable mobile terminals are in demand. To insure reliable transmission, FEC codes get fast developments and wide applications. LDPC code, close to Shannon limit, is widely applied in the DVB-S2, DTMB, CMMB, WLAN, WiMAX, etc. Therefore, designing high-performance LDPC decoder is now one of the hotspots.
Due to mass parallel computing, memory read-write accesses, and register overturns, high-speed LDPC decoders feature high power and large area. Improving parallel degree results many problems, such as data dependency, configurability, memory access conflicts, etc. Based on different applications, the dissertation designs several LDPC decoders, solves the problems from high parallel degree, optimizes their power consumption and area, and boosts their configurability. The main contributions of the dissertation include the following aspects.
With key techniques of speeding up decoding convergency, two-phase fully overlapping, dual-path parallel computing, and deep pipelining, the decoders' throughputs are improved further. With key techniques of memory access reduction, dynamic clock gating, early termination strategy, and parallel and pipelining, the decoders'powers are lowered further. With key techniques of computing complexity and memory resource reduction, memory structure optimization, and utilization ratio improvement, the decoders'areas are much smaller.
Based on the study of the above key techniques, four decodersⅠ,Ⅱ,Ⅲ, andⅣwith different parallel degrees are designed and implemented. DecodersⅠandⅡattain about 100Mb/s and are fit for the multimedia broadcasting systems:DTMB and CMMB; DecodersⅢandⅣattain>250Mb/s and are fit for the high-speed celluar mobile communication system:WiMAX and 4G. All the key techniques and methods are tested and verified in the decoder chips.
引文
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