低接触势垒ErSi_（2-x）和YSi_（2-x）薄膜的制备及特性研究
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摘要
随着集成电路器件尺寸的持续缩小,与Si超低接触电阻率的要求以及新型源漏结构器件的出现,迫切需要降低金属硅化物的接触势垒。因此能与n型Si形成低接触势垒的稀土金属硅化物(如ErSi_(2-x)、YSi_(2-x)等)日益引起研究者的关注。但是,薄膜的氧化问题及表面形貌缺陷问题阻碍了稀土金属硅化物在大规模生产工艺中的应用。本论文以ErSi_(2-x)和YSi_(2-x)为主要研究对象,利用蒸发、溅射和快速热退火等常规工艺手段和一系列物相、形貌、电学表征方法对上述两个问题进行了深入的研究,取得了以下主要结果:
1.YSi_(2-x)薄膜的生长及性质表征
Y/Si(100)在500℃至950℃快速热退火条件下,可生成非常稳定且具有较低薄层电阻的YSi_(2-x)薄膜,但存在氧化问题。硅化物形成的同时伴随着针孔的出现,其形状为方形或者长方形,尺寸在微米量级。YSi_(2-x)/p-Si(100)接触势垒高度随退火温度变化不大,在0.633 eV至0.686 eV之间。I-V-T测试表明,YSi_(2-x)/n-Si(100)接触的Schottky势垒存在微观不均匀性,该不均匀性可用高斯分布模型描述。500℃、600℃和900℃退火样品的平均势垒高度分别为0.460 eV、0.376eV和0.324 eV,而700℃和800℃退火形成的YSi_(2-x)/n-Si(100)二极管样品在低温时仍表现出“欧姆”特性(整流比较低,约为几十)。
2.ErSi_(2-x)薄膜的生长及性质表征
Er/Si(100)在500℃至1000℃退火条件下,也可生成非常稳定且薄层电阻较低的ErSi_(2-x)薄膜。分析表明,Er/Si(100)样品退火时的固相反应可以看作界面硅化反应与表面氧化反应的相互竞争过程。针孔现象在ErSi_(2-x)薄膜中同样存在,然而对于很薄的ErSi_(2-x)薄膜,则可能形成金字塔形缺陷结构。当金属Er层比较厚的时候,退火形成的ErSi_(2-x)/p-Si(100)接触受到氧化的影响较小,测得的接触势垒高度在0.783 eV至0.805 eV之间,且随退火温度变化不大。但对很薄的样品,氧化很容易造成接触特性的退化和破坏。I-V-T测试表明,ErSi_(2-x)/n-Si(100)接触的Schottky势垒也存在着微观不均匀性,该不均匀性也可用高斯分布模型描述,不同退火温度样品的平均势垒高度在0.343～0.427 eV之间,而700℃、800℃和900℃退火样品的势垒不均匀性相对较大,因此这三个退火温度的二极管样品在低温时仍呈现“欧姆”特性。
3.利用W覆盖层制备ErSi_(2-x)薄膜及其性质表征
将W覆盖层技术应用于自对准ErSi_(2-x)工艺,并用该方法成功地制备了自对准的ErSi_(2-x)/p-Si(100)二极管样品。实验表明,W覆盖层不仅能有效防止薄膜出现金字塔形缺陷,获得平整的ErSi_(2-x)薄膜,而且对抑制ErSi_(2-x)薄膜氧化、改善ErSi_(2-x)/p-Si(100)的接触特性也有促进作用。
4.Er中间层对Ni/Si(100)固相反应、NiSi/Si(100)接触特性的影响
对Ni/Er/Si(100)三元体系的研究发现,很薄中间层Er的加入,会提高NiSi形成温度,并抑制Ni_2Si等富Ni硅化物相的出现,在700℃及以上温度退火所形成的NiSi_2则有明显的(100)择优生长晶向。然而,退火之后发现Er大部分偏析到NiSi薄膜表层,因此Er的掺入并不能有效地调制NiSi/n-Si(100)的Schottky势垒高度。
5.掺Pt对Si(100)上生长的NiSi薄膜应力影响研究
原位应力测试表明,Si(100)衬底上生长的纯NiSi薄膜和纯PtSi薄膜的室温应力主要是热应力,且分别为775MPa和1.31GPa,而对于Ni_(1-x)Pt_xSi合金硅化物薄膜,室温应力则随着Pt含量的增加而逐渐增大,造成应力增大的主要原因是Pt的加入提高了薄膜的应力弛豫温度。
As the feature size of modern complementary metal-oxide-semiconductor devices is continuously scaling, the urgent demand for low contact resistivity with Si as well as the emerging of new source/drain structures requires the Schottky barriers of silicide contacts on Si to be very low. Rare earth (RE) silicides such as ErSi_(2-x) and YSi_(2-x) have aroused much research interest in recent years for their very low Schottky barriers on n-type Si. However, RE silicides suffer from oxidation problems and surface morphological defects. In this dissertation, a study has been carried out on ErSi_(2-x) and YSi_(2-x) prepared by evaporation, sputtering and rapid thermal annealing (RTA). Various characterization methods were employed to investigate the phase, morphology and electrical properties of the formed silicide layers on Si(100). The dissertation obtained the following results.
1. Growth and properties of YSi_(2-x) on Si(100)
By evaporation of Y on Si(100) substrate followed by RTA, YSi_(2-x) film can be formed at 500℃annealing and keep stable up to 950℃annealing. However, oxidation problems could not be avoided. As the silicide formed, pinholes were also observed to form in the silicide layers. The pinhole has a shape of either a square or a rectangle. The contact barrier of YSi_(2-x) on p-Si(100) was found to be between 0.633 eV and 0.686 eV which does not vary significantly with different annealing temperatures. The I-V-T characteristics of YSi_(2-x)/n-Si(100) Schottky diodes show that microscopic inhomogeneity of Schottky barrier height (SBH) exists in this contact system, which can be described by a Gaussian distribution model. The mean SBH of the YSi_(2-x)/n-Si(100) diode was shown to be 0.460, 0.376, 0.324 eV for annealing temperatures of 500, 600, 900℃, respectively, and possibly even lower for 700 and 800℃annealing temperatures. The diodes annealed at 700 and 800℃showed ohmic-like behaviour even when cooled down to temperature as low as 90 K.
2. Growth and properties of ESi_(2-x) on Si(100)
By sputter deposition of Er on Si(100) followed by RTA, ErSi_(2-x) film can be formed at 500℃annealing and keep stable up to 1000℃annealing. The solid phase reaction of the Er film on the Si substrate can be considered as a competition between the silicidation at the Er/Si interface and the oxidation at the film surface. Pinholes or pyramidal defects were observed to form in the formed ErSi_(2-x) film depending on the initial Er thickness. When the silicide layer is thick, the SBH of the ErSi_(2-x)/p-Si(100) contact was found to vary between 0.783 and 0.805 eV for annealing temperature ranging from 500 to 900℃. As the thickness of the ErSi_(2-x) layer is reduced, the contact properties of the ErSi_(2-x)/p-Si(100) diode are degraded due to severe oxidation problems. The SBH inhomogeneity also exists in ErSi_(2-x)/n-Si(100) contacts, which can also be well described by the Gaussian distribution model. The mean SBHs of the ErSi_(2-x)/n-Si(100) contacts were extracted to be 0.343-0.427 eV for different annealing temperatures. And the SBH inhomogeneity for the diodes annealed at 700, 800 and 900℃was found to be larger than for those annealed at 500 and 600℃, which explains well the ohmic-like behaviour at low temperatures for the diodes annealed at 700, 800 and 900℃.
3. Formation of ErSi_(2-x) film with W capping layer
A W capping technique was investigated to fabricate self-aligned ErSi_(2-x)/p-Si(100) diodes. With the W capping, the formed ErSi_(2-x) film was observed to be quite smooth without any pinhole or pyramidal defect. This technique also helps to suppress oxidation and to improve the contact properties of the ErSi_(2-x) on p-type Si.
4. Effect of erbium interlayer on nickel silicide formation on Si(100)
In the study of Ni/Er/Si(100) ternary system, the NiSi formation temperature was found to increase depending on the Er interlayer thickness (0.5-3.0 nm). With Er(2 nm) interlayer, the formed NiSi_2 after annealing at 700℃or above was observed to be highly textured with (100) preferred orientation. During the NiSi formation, Er segregates to the surface with little remaining at the NiSi/Si(100) interface. Therefore, no appreciable SBH modulation was observed in the NiSi/n-Si(100) contact by Er addition.
5. Effect of Pt addition on the stress of NiSi film formed on Si(100)
Systematic in-situ stress measurement on Ni_(1-x)Pt_xSi formed on Si(100) showed that the residual thermal stress at room temperature is 775 MPa and 1.31 GPa for NiSi and PtSi films grown on Si(100) substrates, respectively. For the Ni_(1-x)Pt_xSi alloy film, the residual stress was observed to increase steadily with Pt composition. The stress relaxation temperature, which also increases with the Pt composition, was found to be reason for such a law.
1.YSi_(2-x)薄膜的生长及性质表征
Y/Si(100)在500℃至950℃快速热退火条件下,可生成非常稳定且具有较低薄层电阻的YSi_(2-x)薄膜,但存在氧化问题。硅化物形成的同时伴随着针孔的出现,其形状为方形或者长方形,尺寸在微米量级。YSi_(2-x)/p-Si(100)接触势垒高度随退火温度变化不大,在0.633 eV至0.686 eV之间。I-V-T测试表明,YSi_(2-x)/n-Si(100)接触的Schottky势垒存在微观不均匀性,该不均匀性可用高斯分布模型描述。500℃、600℃和900℃退火样品的平均势垒高度分别为0.460 eV、0.376eV和0.324 eV,而700℃和800℃退火形成的YSi_(2-x)/n-Si(100)二极管样品在低温时仍表现出“欧姆”特性(整流比较低,约为几十)。
2.ErSi_(2-x)薄膜的生长及性质表征
Er/Si(100)在500℃至1000℃退火条件下,也可生成非常稳定且薄层电阻较低的ErSi_(2-x)薄膜。分析表明,Er/Si(100)样品退火时的固相反应可以看作界面硅化反应与表面氧化反应的相互竞争过程。针孔现象在ErSi_(2-x)薄膜中同样存在,然而对于很薄的ErSi_(2-x)薄膜,则可能形成金字塔形缺陷结构。当金属Er层比较厚的时候,退火形成的ErSi_(2-x)/p-Si(100)接触受到氧化的影响较小,测得的接触势垒高度在0.783 eV至0.805 eV之间,且随退火温度变化不大。但对很薄的样品,氧化很容易造成接触特性的退化和破坏。I-V-T测试表明,ErSi_(2-x)/n-Si(100)接触的Schottky势垒也存在着微观不均匀性,该不均匀性也可用高斯分布模型描述,不同退火温度样品的平均势垒高度在0.343～0.427 eV之间,而700℃、800℃和900℃退火样品的势垒不均匀性相对较大,因此这三个退火温度的二极管样品在低温时仍呈现“欧姆”特性。
3.利用W覆盖层制备ErSi_(2-x)薄膜及其性质表征
将W覆盖层技术应用于自对准ErSi_(2-x)工艺,并用该方法成功地制备了自对准的ErSi_(2-x)/p-Si(100)二极管样品。实验表明,W覆盖层不仅能有效防止薄膜出现金字塔形缺陷,获得平整的ErSi_(2-x)薄膜,而且对抑制ErSi_(2-x)薄膜氧化、改善ErSi_(2-x)/p-Si(100)的接触特性也有促进作用。
4.Er中间层对Ni/Si(100)固相反应、NiSi/Si(100)接触特性的影响
对Ni/Er/Si(100)三元体系的研究发现,很薄中间层Er的加入,会提高NiSi形成温度,并抑制Ni_2Si等富Ni硅化物相的出现,在700℃及以上温度退火所形成的NiSi_2则有明显的(100)择优生长晶向。然而,退火之后发现Er大部分偏析到NiSi薄膜表层,因此Er的掺入并不能有效地调制NiSi/n-Si(100)的Schottky势垒高度。
5.掺Pt对Si(100)上生长的NiSi薄膜应力影响研究
原位应力测试表明,Si(100)衬底上生长的纯NiSi薄膜和纯PtSi薄膜的室温应力主要是热应力,且分别为775MPa和1.31GPa,而对于Ni_(1-x)Pt_xSi合金硅化物薄膜,室温应力则随着Pt含量的增加而逐渐增大,造成应力增大的主要原因是Pt的加入提高了薄膜的应力弛豫温度。
As the feature size of modern complementary metal-oxide-semiconductor devices is continuously scaling, the urgent demand for low contact resistivity with Si as well as the emerging of new source/drain structures requires the Schottky barriers of silicide contacts on Si to be very low. Rare earth (RE) silicides such as ErSi_(2-x) and YSi_(2-x) have aroused much research interest in recent years for their very low Schottky barriers on n-type Si. However, RE silicides suffer from oxidation problems and surface morphological defects. In this dissertation, a study has been carried out on ErSi_(2-x) and YSi_(2-x) prepared by evaporation, sputtering and rapid thermal annealing (RTA). Various characterization methods were employed to investigate the phase, morphology and electrical properties of the formed silicide layers on Si(100). The dissertation obtained the following results.
1. Growth and properties of YSi_(2-x) on Si(100)
By evaporation of Y on Si(100) substrate followed by RTA, YSi_(2-x) film can be formed at 500℃annealing and keep stable up to 950℃annealing. However, oxidation problems could not be avoided. As the silicide formed, pinholes were also observed to form in the silicide layers. The pinhole has a shape of either a square or a rectangle. The contact barrier of YSi_(2-x) on p-Si(100) was found to be between 0.633 eV and 0.686 eV which does not vary significantly with different annealing temperatures. The I-V-T characteristics of YSi_(2-x)/n-Si(100) Schottky diodes show that microscopic inhomogeneity of Schottky barrier height (SBH) exists in this contact system, which can be described by a Gaussian distribution model. The mean SBH of the YSi_(2-x)/n-Si(100) diode was shown to be 0.460, 0.376, 0.324 eV for annealing temperatures of 500, 600, 900℃, respectively, and possibly even lower for 700 and 800℃annealing temperatures. The diodes annealed at 700 and 800℃showed ohmic-like behaviour even when cooled down to temperature as low as 90 K.
2. Growth and properties of ESi_(2-x) on Si(100)
By sputter deposition of Er on Si(100) followed by RTA, ErSi_(2-x) film can be formed at 500℃annealing and keep stable up to 1000℃annealing. The solid phase reaction of the Er film on the Si substrate can be considered as a competition between the silicidation at the Er/Si interface and the oxidation at the film surface. Pinholes or pyramidal defects were observed to form in the formed ErSi_(2-x) film depending on the initial Er thickness. When the silicide layer is thick, the SBH of the ErSi_(2-x)/p-Si(100) contact was found to vary between 0.783 and 0.805 eV for annealing temperature ranging from 500 to 900℃. As the thickness of the ErSi_(2-x) layer is reduced, the contact properties of the ErSi_(2-x)/p-Si(100) diode are degraded due to severe oxidation problems. The SBH inhomogeneity also exists in ErSi_(2-x)/n-Si(100) contacts, which can also be well described by the Gaussian distribution model. The mean SBHs of the ErSi_(2-x)/n-Si(100) contacts were extracted to be 0.343-0.427 eV for different annealing temperatures. And the SBH inhomogeneity for the diodes annealed at 700, 800 and 900℃was found to be larger than for those annealed at 500 and 600℃, which explains well the ohmic-like behaviour at low temperatures for the diodes annealed at 700, 800 and 900℃.
3. Formation of ErSi_(2-x) film with W capping layer
A W capping technique was investigated to fabricate self-aligned ErSi_(2-x)/p-Si(100) diodes. With the W capping, the formed ErSi_(2-x) film was observed to be quite smooth without any pinhole or pyramidal defect. This technique also helps to suppress oxidation and to improve the contact properties of the ErSi_(2-x) on p-type Si.
4. Effect of erbium interlayer on nickel silicide formation on Si(100)
In the study of Ni/Er/Si(100) ternary system, the NiSi formation temperature was found to increase depending on the Er interlayer thickness (0.5-3.0 nm). With Er(2 nm) interlayer, the formed NiSi_2 after annealing at 700℃or above was observed to be highly textured with (100) preferred orientation. During the NiSi formation, Er segregates to the surface with little remaining at the NiSi/Si(100) interface. Therefore, no appreciable SBH modulation was observed in the NiSi/n-Si(100) contact by Er addition.
5. Effect of Pt addition on the stress of NiSi film formed on Si(100)
Systematic in-situ stress measurement on Ni_(1-x)Pt_xSi formed on Si(100) showed that the residual thermal stress at room temperature is 775 MPa and 1.31 GPa for NiSi and PtSi films grown on Si(100) substrates, respectively. For the Ni_(1-x)Pt_xSi alloy film, the residual stress was observed to increase steadily with Pt composition. The stress relaxation temperature, which also increases with the Pt composition, was found to be reason for such a law.
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