基于FPGA的雷达信号侦察数字接收机关键技术研究
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摘要
随着信号处理技术的进步和电子技术的发展,雷达信号侦察接收机逐渐从模拟体制向数字体制转变。软件无线电概念的提出,促使雷达侦察接收机朝大带宽、全截获方向发展,现有的串行信号处理体制已经很难满足系统要求。FPGA器件的出现,为实现宽带雷达信号侦察数字接收机提供了硬件支持。
本文结合FPGA芯片特点,在前人研究基础上,从算法和硬件实现两方面,对雷达信号侦察数字接收机若干关键技术进行了研究和创新,主要研究内容包括以下几个方面。
1)给出了基于QuartusII/Matlab和ISE/ModelSim/Matlab的两种FPGA设计联合仿真技术。这种联合仿真技术,大大提高了基于FPGA的雷达信号侦察数字接收机的设计效率。
2)给出了一种基于FFT/IFFT的宽带数字正交变换算法,并将该算法在FPGA中进行了硬件实现,设计可对600MHz带宽内的输入信号进行实时正交变换。
3)提出了一种全并行结构FFT的FPGA实现方案,并将其在FPGA芯片中进行了硬件实现,设计能够在一个时钟周期内完成32点并行FFT运算,满足了数字信道化接收机对数据处理速度的要求。
4)提出了一种自相关信号检测FPGA实现方案,通过改变FIFO长度改变自相关运算点数,实现了弱信号检测。提出通过二次门限处理来消除检测脉冲中的毛刺和凹陷,降低了虚警概率,提高了检测结果的可靠性。
5)在单通道自相关信号检测算法基础上,提出采用三路并行检测,每路采用不同的相关点数和检测门限,再综合考虑三路检测结果,得到最终检测结果。给出了算法FPGA实现过程,并对设计进行了联合时序仿真,提高了检测性能。
6)给出了一种利用FFT变换后的两根最大谱线进行插值的快速高精度频率估计方法,并将该算法在FPGA硬件中进行了实现。通过利用FFT运算后的实/虚部最大值进行插值,降低了硬件资源消耗、缩短了运算延迟。
7)结合4)、5)、6)中的研究成果,完成了对雷达脉冲信号到达时间、终止时间、脉冲宽度和脉冲频率的估计,最终在一块FPGA芯片内实现了一个精简的雷达信号侦察数字接收机,并在微波暗室中进行了测试。
As the development of signal processing and electronic technology, the system of radar signal reconnaissance receiver has been changed from analog to digital. The emergence of software radio concept prompts the development of wideband and full interception of radar reconnaissance. Present serial signal processing structure was difficult to meet the system’s requirements. However, the invention of FPGA device makes it convenient to realize such a wideband radar signal reconnaissance digital receiver.
According to the characteristics of FPGA chip, several novel algorithms and hardware implementation technologies of radar signal reconnaissance digital receiver have been researched, which were based on the previous research achievements of our group. The main contents and innovations of this dissertation were following.
1) Two kinds of co-simulation technologies, such as Matlab/ QuartusII and ISE/ModelSim/Matlab, were presented to implement FPGA. The design efficiency of radar signal reconnaissance receiver using FPGA could be improved greatly by these co-simulation methods.
2) A wideband digital In-phase/Quadrature(I/Q) transformation algorithm based on FFT/IFFT was presented. And then it was implemented in FPGA. This design can complete a real time continuous I/Q transformation of he input data with 600MHz bandwidth.
3) A full parallel FFT arithmetic and its implementation in FPGA were presented. The total 32 points FFT computation could be accomplished within only one clock cycle. The operation speed can meet the requirement of the channellized digital reconnaissance receiver.
4) A self-correlation signal detection algorithm and its implementation in FPGA were presented. By modifying the FIFO depth, the length of self-correlation can be altered conveniently, which could be used to detect weak signal. The thorns and protuberances appeared while detecting radar pulse would be eliminated through setting the second threshold. The probability of false alarm is reduced and the reliability of detection result improved.
5) A effective multi-channel self-correlation signal detection algorithm was proposed. The basic structure of this algorithm included three channels. Each channel was an independent self-correlation cell with different correlation length and detection threshold. Through combining the detection results of three independent channels, final detection result was given. The implementation procedure of this algorithm in FPGA was presented. The co-simulation results showed that the signal detection capability can be improved greatly.
6) A fast and accurate frequency estimation method, which was derived by interpolating between two maximum FFT coefficients, was presented. Then it was implemented in FPGA chip. In order to reduce operation delay and save hardware resources, only real or image part of the two maximum FFT coefficients were used when implementing this algorithm in FPGA.
7) Summarizing the results presented above, a radar signal reconnaissance digital receiver was implemented in a single FPGA chip. The capabilities of intercepting radar signal, estimating arriving time, terminative time, pulse width and pulse frequency can be obtained by this single chip receiver at real time. Finally, the receiver was tested in microwave darkroom.
本文结合FPGA芯片特点,在前人研究基础上,从算法和硬件实现两方面,对雷达信号侦察数字接收机若干关键技术进行了研究和创新,主要研究内容包括以下几个方面。
1)给出了基于QuartusII/Matlab和ISE/ModelSim/Matlab的两种FPGA设计联合仿真技术。这种联合仿真技术,大大提高了基于FPGA的雷达信号侦察数字接收机的设计效率。
2)给出了一种基于FFT/IFFT的宽带数字正交变换算法,并将该算法在FPGA中进行了硬件实现,设计可对600MHz带宽内的输入信号进行实时正交变换。
3)提出了一种全并行结构FFT的FPGA实现方案,并将其在FPGA芯片中进行了硬件实现,设计能够在一个时钟周期内完成32点并行FFT运算,满足了数字信道化接收机对数据处理速度的要求。
4)提出了一种自相关信号检测FPGA实现方案,通过改变FIFO长度改变自相关运算点数,实现了弱信号检测。提出通过二次门限处理来消除检测脉冲中的毛刺和凹陷,降低了虚警概率,提高了检测结果的可靠性。
5)在单通道自相关信号检测算法基础上,提出采用三路并行检测,每路采用不同的相关点数和检测门限,再综合考虑三路检测结果,得到最终检测结果。给出了算法FPGA实现过程,并对设计进行了联合时序仿真,提高了检测性能。
6)给出了一种利用FFT变换后的两根最大谱线进行插值的快速高精度频率估计方法,并将该算法在FPGA硬件中进行了实现。通过利用FFT运算后的实/虚部最大值进行插值,降低了硬件资源消耗、缩短了运算延迟。
7)结合4)、5)、6)中的研究成果,完成了对雷达脉冲信号到达时间、终止时间、脉冲宽度和脉冲频率的估计,最终在一块FPGA芯片内实现了一个精简的雷达信号侦察数字接收机,并在微波暗室中进行了测试。
As the development of signal processing and electronic technology, the system of radar signal reconnaissance receiver has been changed from analog to digital. The emergence of software radio concept prompts the development of wideband and full interception of radar reconnaissance. Present serial signal processing structure was difficult to meet the system’s requirements. However, the invention of FPGA device makes it convenient to realize such a wideband radar signal reconnaissance digital receiver.
According to the characteristics of FPGA chip, several novel algorithms and hardware implementation technologies of radar signal reconnaissance digital receiver have been researched, which were based on the previous research achievements of our group. The main contents and innovations of this dissertation were following.
1) Two kinds of co-simulation technologies, such as Matlab/ QuartusII and ISE/ModelSim/Matlab, were presented to implement FPGA. The design efficiency of radar signal reconnaissance receiver using FPGA could be improved greatly by these co-simulation methods.
2) A wideband digital In-phase/Quadrature(I/Q) transformation algorithm based on FFT/IFFT was presented. And then it was implemented in FPGA. This design can complete a real time continuous I/Q transformation of he input data with 600MHz bandwidth.
3) A full parallel FFT arithmetic and its implementation in FPGA were presented. The total 32 points FFT computation could be accomplished within only one clock cycle. The operation speed can meet the requirement of the channellized digital reconnaissance receiver.
4) A self-correlation signal detection algorithm and its implementation in FPGA were presented. By modifying the FIFO depth, the length of self-correlation can be altered conveniently, which could be used to detect weak signal. The thorns and protuberances appeared while detecting radar pulse would be eliminated through setting the second threshold. The probability of false alarm is reduced and the reliability of detection result improved.
5) A effective multi-channel self-correlation signal detection algorithm was proposed. The basic structure of this algorithm included three channels. Each channel was an independent self-correlation cell with different correlation length and detection threshold. Through combining the detection results of three independent channels, final detection result was given. The implementation procedure of this algorithm in FPGA was presented. The co-simulation results showed that the signal detection capability can be improved greatly.
6) A fast and accurate frequency estimation method, which was derived by interpolating between two maximum FFT coefficients, was presented. Then it was implemented in FPGA chip. In order to reduce operation delay and save hardware resources, only real or image part of the two maximum FFT coefficients were used when implementing this algorithm in FPGA.
7) Summarizing the results presented above, a radar signal reconnaissance digital receiver was implemented in a single FPGA chip. The capabilities of intercepting radar signal, estimating arriving time, terminative time, pulse width and pulse frequency can be obtained by this single chip receiver at real time. Finally, the receiver was tested in microwave darkroom.
引文
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