异质栅MOS热载流子效应的研究
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摘要
随着MOSFET器件尺寸以及器件沟道长度的不断减小,沟道内的电场和电流密度迅速增长,会使得热载流子几率形成的几率增大,一旦内部电场达到临界值后,载流子的速度达到饱和,这样不仅不能提高器件的速度,相反由此带来热载流子效应会引起器件的失效。
本文对超大规模集成电路中MOS器件的可靠性问题进行了分析,特别针对MOS器件等比例缩小带来的可靠性问题进行讨论。利用二维数值模拟软件MEDICI进行器件仿真,结合实验数据分析了常规NMOSFET的热载流子分类、热载流子效应的产生机制、衬底电流的形成机理等。
为了遏制热载流子效应,提出一种新的结构异质栅场效应晶体管(DMGMOS FET),其栅极是由两种功函数不同的材料拼接而成的。本文系统的对于DMGMOS FET结构的热载流子效应相关参数进行探讨。
首先采用分区的电势近似法和通用边界条件,求解二维泊松方程,建立适用于新结构的表面势和电场的二维解析模型。再根据DMGMOS FET栅电流和衬底电流的形成理论,利用“几率电子模型”深入剖析DMGMOS热载流子效应的失效机理,并建立适用于深亚微米、超深亚微米DMG结构器件的栅电流以及衬底电流模型。通过计算机数值模拟软件MEDICI模拟得到新结构器件沟道表面势、电场、衬底电流以及栅电流的变化趋势与理论模型所得到的规律一致,从而验证了理论模型的合理性。
本文还通过仿真方法对新结构器件与常规MOSFET的抗热载流子性能进行了对比研究。通过电势、电场、栅电流以及衬底电流等参数的仿真结果验证了DMG结构的优越性。同时用实验结果表明,新结构器件能够有效抑制短沟道效应(SCE)、减小漏感应势垒降低效应(DIBL)等。新结构器件的衬底电流、漏电流都是温度的敏感参数,所以随着器件尺寸减小,自热效应会对热载流子效应产生较大的影响。
分析了晶格温度对碰撞电离的影响,通过研究结果表明,低漏端电压下的碰撞电离率同样是温度的敏感参数。当电压较低时,产生的碰撞电离不再是电场造成的,而是由于晶格温度。
最后,改变器件栅的结构参数,在抗击热载流子效应方面提出栅结构的最优化参数。通过仿真软件对热载流子效应的监测指数进行仿真,得出增大栅功函数差可以降低热载流子效应,并且指出两个栅长度比例为1：1时,器件的抗热载流子性能最佳。
With scaling down of the device, the electric field and the current density of MOSFET increase sharply.And it would increase the probability of the hot carriers'formation. If the electrical field in the channel reach the critical value, the velocity of hot carriers would get to saturation.It can't improve the speed of the device,on the other hand,it would cause device failure.
The reliability problems are analyzed for MOSFET in VLSI, especially for hot carrier effects due to scaling down in MOSFET. By two-dimentional device simulator MEDICI, the hot-carrier classification,the hot-carriers generation mechanism,the formation of substrate current of conventional NMOSFET are analyzed.
A dual-material-gate MOSFET was proposed to suppress the hot carrier effect.The gate consists of two different materials contacting laterally and with different functions. Some parameters for the hot carrier effect of the novel device was studied systemically.
First, using the multi-region potential distribution and universal boundary conditions, the two dimensional analytical models of surface potential and electrical field for the novel device were derived by solving the two dimensional Poisson's equation. According to the theory for the formation of the gate current and the substrate current, using "probability election model" to study the failure mechanism of hot carrier effect. The gate current model and the substrate current for ultra-deep submicron DMG MOSFET are proposed. By computer simulation MEDICI,it is given that the variety of the surface potential、the electrical field、the substrate current and the gate current. The simulation results tally well with the existing experimental data and theoretical models, which proves that the theories are reasonable.
The characteristics of the novel device were studied as compared with the conventional MOSFET. we simulate some parameters which can surveillance the hot carrier effect efficiently, such as electric field、substrate current and gate current et al. It is clear that DMG MOSFET has better performance. It was also shown that the novel device could suppress the short channel effect, drain-induced barrier lowering effect. The gate current and substrate current are sensitive with temperature.So with the scaling down, the self-heating effect would have great influence.
The lattice temperature would influence impact ionization. The occurring of impact ionization was because of lattice temperature.
By simulation,we got the best structure parameter with which the device have wonderful performance.
本文对超大规模集成电路中MOS器件的可靠性问题进行了分析,特别针对MOS器件等比例缩小带来的可靠性问题进行讨论。利用二维数值模拟软件MEDICI进行器件仿真,结合实验数据分析了常规NMOSFET的热载流子分类、热载流子效应的产生机制、衬底电流的形成机理等。
为了遏制热载流子效应,提出一种新的结构异质栅场效应晶体管(DMGMOS FET),其栅极是由两种功函数不同的材料拼接而成的。本文系统的对于DMGMOS FET结构的热载流子效应相关参数进行探讨。
首先采用分区的电势近似法和通用边界条件,求解二维泊松方程,建立适用于新结构的表面势和电场的二维解析模型。再根据DMGMOS FET栅电流和衬底电流的形成理论,利用“几率电子模型”深入剖析DMGMOS热载流子效应的失效机理,并建立适用于深亚微米、超深亚微米DMG结构器件的栅电流以及衬底电流模型。通过计算机数值模拟软件MEDICI模拟得到新结构器件沟道表面势、电场、衬底电流以及栅电流的变化趋势与理论模型所得到的规律一致,从而验证了理论模型的合理性。
本文还通过仿真方法对新结构器件与常规MOSFET的抗热载流子性能进行了对比研究。通过电势、电场、栅电流以及衬底电流等参数的仿真结果验证了DMG结构的优越性。同时用实验结果表明,新结构器件能够有效抑制短沟道效应(SCE)、减小漏感应势垒降低效应(DIBL)等。新结构器件的衬底电流、漏电流都是温度的敏感参数,所以随着器件尺寸减小,自热效应会对热载流子效应产生较大的影响。
分析了晶格温度对碰撞电离的影响,通过研究结果表明,低漏端电压下的碰撞电离率同样是温度的敏感参数。当电压较低时,产生的碰撞电离不再是电场造成的,而是由于晶格温度。
最后,改变器件栅的结构参数,在抗击热载流子效应方面提出栅结构的最优化参数。通过仿真软件对热载流子效应的监测指数进行仿真,得出增大栅功函数差可以降低热载流子效应,并且指出两个栅长度比例为1：1时,器件的抗热载流子性能最佳。
With scaling down of the device, the electric field and the current density of MOSFET increase sharply.And it would increase the probability of the hot carriers'formation. If the electrical field in the channel reach the critical value, the velocity of hot carriers would get to saturation.It can't improve the speed of the device,on the other hand,it would cause device failure.
The reliability problems are analyzed for MOSFET in VLSI, especially for hot carrier effects due to scaling down in MOSFET. By two-dimentional device simulator MEDICI, the hot-carrier classification,the hot-carriers generation mechanism,the formation of substrate current of conventional NMOSFET are analyzed.
A dual-material-gate MOSFET was proposed to suppress the hot carrier effect.The gate consists of two different materials contacting laterally and with different functions. Some parameters for the hot carrier effect of the novel device was studied systemically.
First, using the multi-region potential distribution and universal boundary conditions, the two dimensional analytical models of surface potential and electrical field for the novel device were derived by solving the two dimensional Poisson's equation. According to the theory for the formation of the gate current and the substrate current, using "probability election model" to study the failure mechanism of hot carrier effect. The gate current model and the substrate current for ultra-deep submicron DMG MOSFET are proposed. By computer simulation MEDICI,it is given that the variety of the surface potential、the electrical field、the substrate current and the gate current. The simulation results tally well with the existing experimental data and theoretical models, which proves that the theories are reasonable.
The characteristics of the novel device were studied as compared with the conventional MOSFET. we simulate some parameters which can surveillance the hot carrier effect efficiently, such as electric field、substrate current and gate current et al. It is clear that DMG MOSFET has better performance. It was also shown that the novel device could suppress the short channel effect, drain-induced barrier lowering effect. The gate current and substrate current are sensitive with temperature.So with the scaling down, the self-heating effect would have great influence.
The lattice temperature would influence impact ionization. The occurring of impact ionization was because of lattice temperature.
By simulation,we got the best structure parameter with which the device have wonderful performance.
引文
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[2]W.Schottky,Halblertertheomeder Sperrschicht[J]. Naturwissenscha-ften. 1938,26:843
[3]J.Bardeen and W.H.Brattain, The transistor, a semiconductor triode[J]. Phys.Rev. 1948,71:230
[4]W.Shockley, A unipolar field effect transistor[J]. Proc.IRE.1952,40:1365
[5]J.J.Ebers, Four terminal of p-n-p-n transistors[J]. Proc.IRE.1952,40:1361
[6]D.M.Chapin,C.S.Fuller,and GL.Pearson.A new silicon p-n junction photocell for converting solar radiation into electrical power[J]. J.Appl.Phys.1954,25:676
[7]H.Kroemer, Theory of a wide gap emitter for transistors [J]. Proc, IRE.1957, 45:1535
[8]Gubanov A I.Theory of the contact of two semiconductors of the same type of conductivity.Zh.Tekh.Fiz[J].1951,21:304
[9]Anderson R L. Ge-GaAs heterojunctions[J].IBM.J.Rev.Dev.1960,4:283
[10]L.Esaki.New phenomenon in narrow germanium p-n junctions[J]. Phys.Rev.1958,109.603
[11]D.Kahng and M.M.Atalla. Silicon silicon dioxide surface device[c].IRE Device Research Conference.Pittsburgh,1960
[12]GC.Dacey and I.M.Ross. The Field-Effect Transistor [J].Bell System Technical Journal.1955,34,1149
[13]R.F.Pieefet and J.A.Shield. Simplified Long-Channel MOSFET Theory[J].Solid State Electronics,1983,26:143
[14]程永萱等.模拟集成电子学[M].北京：电子工业出版社,1987
[15]张建人.MOS集成电路分析与设计基础[M].北京：电子工业出版社,1988
[16]贾松良.双极集成电路分析与设计基础[M].北京：高等教育出版社,1983：
[17]陈星弼,唐茂成.晶体管原理与设计[M].成都：成都电讯工程学院出版社,1987
[18]Hu G. A better understanding of CMOS latehup[J].IEEE Trans Eleetron Dev, 1984:31(1):62-70
[19]Blat C E, Nicollian E H. Mechanism of Negative-bias-temperature instability [J]. Appl Phys,1991,69(3):1712
[20]Ping Chung Li, Ibrahim.N.Hajj. Computer-aid redesign of VLSI circuits for hot-carrier reliability[J].IEEE Trans.on CAD,1996,15,453
[21]Wolfgang H.Krautschneid, Hartmud Terletzki, and Qin Wang. Reliabilty Problems of submieron MOS transistors and circuits[J]. Microelectronics and Reliability,1992,32:1499
[22]Schroder D.K., Babcock J.A. Negative bias temperature instability Road to cross in deep submicron silicon semiconductor manufacturing [J].Journal of Applied Phys ics,2003,94 (1):1～18
[23]韩晓亮,郝跃,刘红霞.影响PMOSFET中NBTI效应的相关因素研究[J].微电子学,2004：547～550
[24]C. Hu.Hot-electron effects in MOSF ET's[J]. IED-M.Tech.Dig,1983:176
[25]J.Frey.Where do hot-electrons come from[J].IEEE Circuits & Device Magzine.1991:31
[26]J.D.Hayden et al.,A high-Peformance half-micrometer generation CMOS technology for fast SRAMs[J].IEEE Trans.Electron Devices,1991,38:876
[27]R.H.Dennard,F.H.Gaensslen,H.N.Yu,V.OL.Rideout,E.Bassous and A.R.Leblanc,Design of ion-imPlanted MOSFET's with very small Physical dimensions[J].Solid-State Circuits,1974:256
[28]Takashi Hori,Junji Hirase,Yoshinori Odake and Takatoshi Yasui. Deep-submicrometer large-angle-tilt implanted drain (LATID) technology [J]. IEEE Trans.Electron Devices,1992,39:2312
[29]K.R.Mistry,T.F.Fox,R.P.Preston,N.D.Arora,B.S.Doyle,and D.E.Nelsen.Circuit design guidelines for n-channel MOSFET hot carrier robustness[J].IEEE Trans.Electron Devices,1.993,40:1284
[30]Y.Pan, The hot-carrier induced degradation mechanisms of 0.8um LDD P-MOSFET with 850℃ wet gate oxidation[J].IEEE/IRPS,1993:43～47
[31]M.Shur. Split-gate field effect transistor[J].Appl.Phys.Lett.1989,54:162
[32]深亚微米MOS器件热载流子效应的研究[D].西安：西安电子科技大学,1999
[33]超深亚微米MOSFET器件中热载流子效应的研究[D].兰州：兰州大学,2008
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