网络处理器内核体系结构研究
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摘要
如今，被认为是推动下一代网络发展的一项核心技术的网络处理器已开始越来越多地受到业界的关注，网络处理器的出现被认为是通信半导体工业发展的一场革命，市场已经接受了NP贡献给网络设备的价值，国内外的许多公司和大学也纷纷投入力量展开了相关研究。
本文首先研究了高性能处理器流水线的性能与结构以及对相关和中断的处理等关键技术，作者作为设计人员参与研究并设计了32位嵌入式微处理器APMP的流水线。接着，在大量考察了多种商用网络处理器的结构的基础上，本文初步分析了网络处理器的硬件结构特点，并对网络处理器中使用的新技术进行了讨论，在此基础上，本文选取了美国AMCC公司推出的一款具有交换架构和32位RISC处理内核的网络处理器NP3400作为主要研究对象，以ARMP的流水线为基础，设计了RISC处理核的流水线。
论文的研究内容是国防“十五”预研项目“专用高性能微处理器”的一部分。
Nowadays, network processors (NP) are considered as a key technology that promotes the development of next generation network, and it has caught people's attention more and more. The appearance of network processor is thought to be a revolution of the communication industry. The market has accepted the contribution to network development of NP. Many companies and universities put people in the research of NP.
This paper, first, studies the performance and architecture of high performance processor pipeline, and the technology that used to deal with the correlation and interrupt in pipeline. The author takes part in study and design of pipeline of ARMP, which is a 32-bit embed microprocessor. Secondly, this paper analyses several kind of NP, based on this work, author summarizes the characteristic of NP, and introduces the new technology that used by NP. Finally, author chooses the NP3400 network processor, which has a fabric and 32-bit RISC processor core and is the product of AMCC Company, to be the reference design, based on the pipeline of ARMP, scheme out the pipeline of RISC processor core that compatible with NP3400.
The work in this thesis is part of National 05' project entitled "Application Specified high performance microprocessor".
本文首先研究了高性能处理器流水线的性能与结构以及对相关和中断的处理等关键技术，作者作为设计人员参与研究并设计了32位嵌入式微处理器APMP的流水线。接着，在大量考察了多种商用网络处理器的结构的基础上，本文初步分析了网络处理器的硬件结构特点，并对网络处理器中使用的新技术进行了讨论，在此基础上，本文选取了美国AMCC公司推出的一款具有交换架构和32位RISC处理内核的网络处理器NP3400作为主要研究对象，以ARMP的流水线为基础，设计了RISC处理核的流水线。
论文的研究内容是国防“十五”预研项目“专用高性能微处理器”的一部分。
Nowadays, network processors (NP) are considered as a key technology that promotes the development of next generation network, and it has caught people's attention more and more. The appearance of network processor is thought to be a revolution of the communication industry. The market has accepted the contribution to network development of NP. Many companies and universities put people in the research of NP.
This paper, first, studies the performance and architecture of high performance processor pipeline, and the technology that used to deal with the correlation and interrupt in pipeline. The author takes part in study and design of pipeline of ARMP, which is a 32-bit embed microprocessor. Secondly, this paper analyses several kind of NP, based on this work, author summarizes the characteristic of NP, and introduces the new technology that used by NP. Finally, author chooses the NP3400 network processor, which has a fabric and 32-bit RISC processor core and is the product of AMCC Company, to be the reference design, based on the pipeline of ARMP, scheme out the pipeline of RISC processor core that compatible with NP3400.
The work in this thesis is part of National 05' project entitled "Application Specified high performance microprocessor".
引文
[1] Mel Tsail, Chidamber Kulkarni. Christian Sauer, Niraj Shahl, Kurt Keutzer "A Benchmarking Methodology for Network Processors" In Ist Network Processor Workshop, 8thInt. Syrup. on High Performance Computer Architectures (HPCA), Feb. 3rd 2002 Boston, MA
[2] Muthu Venkatachalam, Prashant Chandra. RajYavatkar "A highly flexible, distributed multiprocessor architecture for network processing" In Computer Networks 41 (2003)
[3] Paul Manmon, tan Bartiey "HASTPATHPROCESSING IN THE INTERNET CORE"@http ://www.s3group.com/
[4] TilmanWolfand Mark A. Franklin "Locality-Aware Predictive Scheduling of Network Processors" Departments of Computer Science and Electrical Engineering Washington University in St. Louis, MO, USA
[5] Samarjit Chakraborty, Simon K(?)unzli, Lothar Thiele, Andreas Herkersdorf, Patricia Sagmeister "Performance evaluation of network processor architectures combining simulation with analytical estimation" In Computer Networks 41 (2003) 641-665
[6] Lothar Thiele, Samarjit Chakraborty, Matthias Gries. Simon K unzli "Design Space Exploration of Network Processor Architectures" Computer Engineering and Networks Laboratory Swiss Federal Institute of Technology (ETH) Z"urich, Switzerland
[7] Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, and Brian N. Bershad "Characterizing Processor Architectures for Programmable Network Interfaces" From the Proceedings of the 2000 International Conference on Supercomputing, Santa Fe, N.M., May, 2000
[8] Tomas Henriksson "Hardware Architecture for Protocol Processing" In Linkoping Studies in Science and Technology Thesis No. 911
[9] Prashanth Pappu,TilmanWolf "Scheduling Processing Resources in Programmable Routers" Department of Computer ScienceWashington University in St. Louis, MO, USA
[10] 谭章熹，林闯．任丰源，周文江《网络处理的分析与研究》《软件学报》2003 VOL．14．NO．2
[11] Stephen Melvin, Yale Patt "Handling of Packet Dependencies A Critical lssue for Highly Parallel Network Processors" Published in the International Conference on ompilers,Architecture, and Synthesis for Embedded Systems (CASES), October 8-11 2002, Grenoble, France.
[12] Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer. "On the Performance of multithreaded Architectures for Network Processors" Technical Report 2000-10-01 Department of Computer Science & Engineering University of Washington Seattle, WA 98195
[13] Niraj Shah "Understanding Network Processors" VERSION 1.0, 4 SEPTEMBER 2001
[14] Tilman Wolf, Mark A. Franklin, Edward W. Spitznagel"Design Tradeoffs for Embedded Network Processors" Departments of Computer Science & Electrical Engineering Washington University. St. Louis, Missouri July 10, 2000
[15] Mohammad Peyravian. Jean Calvignac "Fundamental architectural considerations for network processors" Computer Networks 41 (2003) 587-600
[16] Xiaoning Nie, Lajos Gazsi. Frank Engel, Gerhard Fettweis "A New Network Processor Architecture for High-Speed Communication" 2001.10
[17] 任恭海，32位嵌入式航空机载RISC微处理器的研究及系统设计，西北工业大学博士论文，1996年。
[18] 朱霞．线程级并行硬件技术研究．西北工业大学博士论文．2003年。
[19] Larson and Davidson. Cost-effective Processor Design With an Application to Fast Fourier Transform Computers. In Proc. 11th Ann. Allerton Conf. Circuits and System Theory, Urbana, pp.546-557, 1973Steven R. Kunkel and James E. Smith Optimal Pipelining in Supercomputers
[20] P. M. Kogge, The Architecture of Pipelined Computers, McGraw-Hill, New York, 1981
[21] Wolf T, Franklin MA."CommBench—a telecommunica-tions benchmark for network processors" In: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software. Austin, TX, 2000. 154～162
[22] "AMCC nP3400 Programmer Manual" MMC 2000-0056 Document Issue 1.4, April 2001
[2] Muthu Venkatachalam, Prashant Chandra. RajYavatkar "A highly flexible, distributed multiprocessor architecture for network processing" In Computer Networks 41 (2003)
[3] Paul Manmon, tan Bartiey "HASTPATHPROCESSING IN THE INTERNET CORE"@http ://www.s3group.com/
[4] TilmanWolfand Mark A. Franklin "Locality-Aware Predictive Scheduling of Network Processors" Departments of Computer Science and Electrical Engineering Washington University in St. Louis, MO, USA
[5] Samarjit Chakraborty, Simon K(?)unzli, Lothar Thiele, Andreas Herkersdorf, Patricia Sagmeister "Performance evaluation of network processor architectures combining simulation with analytical estimation" In Computer Networks 41 (2003) 641-665
[6] Lothar Thiele, Samarjit Chakraborty, Matthias Gries. Simon K unzli "Design Space Exploration of Network Processor Architectures" Computer Engineering and Networks Laboratory Swiss Federal Institute of Technology (ETH) Z"urich, Switzerland
[7] Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, and Brian N. Bershad "Characterizing Processor Architectures for Programmable Network Interfaces" From the Proceedings of the 2000 International Conference on Supercomputing, Santa Fe, N.M., May, 2000
[8] Tomas Henriksson "Hardware Architecture for Protocol Processing" In Linkoping Studies in Science and Technology Thesis No. 911
[9] Prashanth Pappu,TilmanWolf "Scheduling Processing Resources in Programmable Routers" Department of Computer ScienceWashington University in St. Louis, MO, USA
[10] 谭章熹，林闯．任丰源，周文江《网络处理的分析与研究》《软件学报》2003 VOL．14．NO．2
[11] Stephen Melvin, Yale Patt "Handling of Packet Dependencies A Critical lssue for Highly Parallel Network Processors" Published in the International Conference on ompilers,Architecture, and Synthesis for Embedded Systems (CASES), October 8-11 2002, Grenoble, France.
[12] Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer. "On the Performance of multithreaded Architectures for Network Processors" Technical Report 2000-10-01 Department of Computer Science & Engineering University of Washington Seattle, WA 98195
[13] Niraj Shah "Understanding Network Processors" VERSION 1.0, 4 SEPTEMBER 2001
[14] Tilman Wolf, Mark A. Franklin, Edward W. Spitznagel"Design Tradeoffs for Embedded Network Processors" Departments of Computer Science & Electrical Engineering Washington University. St. Louis, Missouri July 10, 2000
[15] Mohammad Peyravian. Jean Calvignac "Fundamental architectural considerations for network processors" Computer Networks 41 (2003) 587-600
[16] Xiaoning Nie, Lajos Gazsi. Frank Engel, Gerhard Fettweis "A New Network Processor Architecture for High-Speed Communication" 2001.10
[17] 任恭海，32位嵌入式航空机载RISC微处理器的研究及系统设计，西北工业大学博士论文，1996年。
[18] 朱霞．线程级并行硬件技术研究．西北工业大学博士论文．2003年。
[19] Larson and Davidson. Cost-effective Processor Design With an Application to Fast Fourier Transform Computers. In Proc. 11th Ann. Allerton Conf. Circuits and System Theory, Urbana, pp.546-557, 1973Steven R. Kunkel and James E. Smith Optimal Pipelining in Supercomputers
[20] P. M. Kogge, The Architecture of Pipelined Computers, McGraw-Hill, New York, 1981
[21] Wolf T, Franklin MA."CommBench—a telecommunica-tions benchmark for network processors" In: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software. Austin, TX, 2000. 154～162
[22] "AMCC nP3400 Programmer Manual" MMC 2000-0056 Document Issue 1.4, April 2001