基于UWB通信系统信道编解码的FPGA实现
摘要
由于通信信道固有的噪声和衰落特性,加上存储媒介的缺陷等原因,以及新的通信业务和信息业务的不断涌现,用户对信息传输的质量要求和速率要求不断提高。信道编码提高了信息传输的可靠性,但是常用的信道编码理论对于UWB系统还未有充分的探讨。
本课题研究的目的在于通过信道纠错码中的级联码仿真试验,为UWB信道纠错码提供试验和实践依据,为考察UWB通信系统的信道编码纠错能力提供参考依据。
本文通过在QuartusII软件上进行级联纠错码的编写和仿真,编写了级联码的编解码程序(卷积码+交织+RS码),并加以仿真,测试了单独的RS码纠错能力和级联码纠错能力(卷积码+交织+RS码),仿真和分析了二者之间的差距,给出实际UWB系统中级联纠错的方法。本文的研究内容主要包括以下几个方面:
(1)采用横向对比方法,分析UWB系统和DVB-T、DVB-D,建立系统分析模型,并研究诸模型的异同。
(2)研究卷积码,采用维特比Viterbi译码方法设计,纠随机错误能力,满足了译码设备简单的需求。
(3)通过设计交织和解交织,解决集群出错问题。
(4)根据RS码特性,分析突发性错误纠错方法,给出RS码编译码方法。
本文中由实验和仿真得到的结论反映了信道编码中的级联纠错码的实际模型和应用特性,为信道纠错码在复杂UWB系统中的进一步应用提供了理论基础;RS码与卷积码和交织技术并联组合的纠错方法对降低信道编码的错误率、提高纠错能力、满足通信需要具有一定的参考价值。
As a result of the inherent noise and the fading feature, added to shortcomings of the storage media, as well as the appearances of the new communication service and new information business, clients require better more quality for information transmission service and transmission rate. The channel coding improves the reliability for the code transmission procedure, meanwhile the tranditional code theory provides inadequate study and evidence for the UWB communication system.
This thesis aims at establishing an practical FEC model for the Cchannel coding through experiments and simulations, supply a reliable basid for UWB。
This thesis includes some basic contents, which contain the edition and simulation of the source code for the Cascade Code, to design the RS code, interleaver technology and convolution code separately, meanwhile simulate them, test the ability of error correction for the RS Code and Cascade Code independently, and furtherly more analysize the difference between them, provide the actural solution of the cascade for the UWB system. This paper mainly concentrates on the following aspects:
(1) A crossive comparision of UWB, DVB-T and DVB-D, to set up their models, and to study the difference among them.
(2) To meeting the application cases, charging methods and efficiency of supercapacitors are discussed in the thesis. The charging speed and safety problems are solved by designing a high current constant-current power supply device.
(3) Designing the Interleaver and Deinterleaver code, to solve the mass error.
(4) Depending on the characteristics of the RS code, to analyze the sudden errors, supply the measures of the RS encoding and decoding.
The conclusions in this thesis drawn from experiments and simulations indicate the properties of their actual model and the rules of the their applications, supply the improved theory foundation for more use. The Error-Correction methond, that is the Reed-Solomn Code, combined with the Convolution Code and interleave technology, is an appropriate selection to decrease the error rate of channel code and improve the ability of correcting, also has some valuable reference for them.
本课题研究的目的在于通过信道纠错码中的级联码仿真试验,为UWB信道纠错码提供试验和实践依据,为考察UWB通信系统的信道编码纠错能力提供参考依据。
本文通过在QuartusII软件上进行级联纠错码的编写和仿真,编写了级联码的编解码程序(卷积码+交织+RS码),并加以仿真,测试了单独的RS码纠错能力和级联码纠错能力(卷积码+交织+RS码),仿真和分析了二者之间的差距,给出实际UWB系统中级联纠错的方法。本文的研究内容主要包括以下几个方面:
(1)采用横向对比方法,分析UWB系统和DVB-T、DVB-D,建立系统分析模型,并研究诸模型的异同。
(2)研究卷积码,采用维特比Viterbi译码方法设计,纠随机错误能力,满足了译码设备简单的需求。
(3)通过设计交织和解交织,解决集群出错问题。
(4)根据RS码特性,分析突发性错误纠错方法,给出RS码编译码方法。
本文中由实验和仿真得到的结论反映了信道编码中的级联纠错码的实际模型和应用特性,为信道纠错码在复杂UWB系统中的进一步应用提供了理论基础;RS码与卷积码和交织技术并联组合的纠错方法对降低信道编码的错误率、提高纠错能力、满足通信需要具有一定的参考价值。
As a result of the inherent noise and the fading feature, added to shortcomings of the storage media, as well as the appearances of the new communication service and new information business, clients require better more quality for information transmission service and transmission rate. The channel coding improves the reliability for the code transmission procedure, meanwhile the tranditional code theory provides inadequate study and evidence for the UWB communication system.
This thesis aims at establishing an practical FEC model for the Cchannel coding through experiments and simulations, supply a reliable basid for UWB。
This thesis includes some basic contents, which contain the edition and simulation of the source code for the Cascade Code, to design the RS code, interleaver technology and convolution code separately, meanwhile simulate them, test the ability of error correction for the RS Code and Cascade Code independently, and furtherly more analysize the difference between them, provide the actural solution of the cascade for the UWB system. This paper mainly concentrates on the following aspects:
(1) A crossive comparision of UWB, DVB-T and DVB-D, to set up their models, and to study the difference among them.
(2) To meeting the application cases, charging methods and efficiency of supercapacitors are discussed in the thesis. The charging speed and safety problems are solved by designing a high current constant-current power supply device.
(3) Designing the Interleaver and Deinterleaver code, to solve the mass error.
(4) Depending on the characteristics of the RS code, to analyze the sudden errors, supply the measures of the RS encoding and decoding.
The conclusions in this thesis drawn from experiments and simulations indicate the properties of their actual model and the rules of the their applications, supply the improved theory foundation for more use. The Error-Correction methond, that is the Reed-Solomn Code, combined with the Convolution Code and interleave technology, is an appropriate selection to decrease the error rate of channel code and improve the ability of correcting, also has some valuable reference for them.
引文
1赵晓群.现代编码理论.华中科技大学出版社, 2003, 8(4):163-165
2张忠培,史志平.现代编码理论与应用.国防工业出版社, 2007, 25
3肖国镇.编码理论.国防工业出版社, 1993
4贾世楼.信息理论基础(第二版).哈尔滨工业大学出版社,2001:P7-9
5 R.J.McEliece. The Theory of Information and Coding.第2版(美)电子工业出版社,2003:253-254
6王新梅,肖国振.纠错码原理与方法.西安:西安电子科技大学出版,2001
7冯重熙等.现代数字通信技术.第1版.北京:人民邮电出版社, 1987
8吴克颖,李晖,王育民.基于卷积码的码交织器的设计.计算机学报. 2000(4):382-385
9岳殿武,徐澄沂.关于纠错码的若干新方向.重庆邮电学院报.2000(12):1-6
10马秀莲等.数字通信差错控制技术.第1版.北京:中国铁道出版社,1991
11王进祥,毛志刚. RS译码器综述.微电子学, 1997(2):(115-120)
12汪晓岩等.基于复数基的RS译码器的FPGA优化实现.通信学报. 2003(4):85-93
13王进祥,张乃通.流水线结构RS(255,223)译码器的VSLI设计.计算机研究与发展, 2000(1):(61-65)
14 Colls K. ASIC synthesis of flexible 80Mbit/s Reed-Solomon code. EDA&T, Beijing,China,1994
15 D.V.Sarwate, N.R.Shanbag. High-Speed Architecture for Reed-Solomon Decoders. IEEE Trans. On VLSI Systems, 2001, 9(5):641-655
16 Maki,G K. VLSI Reed-Solomon decoder design. In:MILCOM’86.1986 IEEE Military Communications Conference, 1986, 3
17周世东,梅顺良,姚彦.并行级联卷积码的最新进展.电子学报. 1998(7):59-65
18王国立. RS+卷积级联码在无线本地环路中的性能分析.电子产品世界. 1999(12):27-28
19刘培,葛建华,刘刚.级联卷积码的性能评估.电子学报.2003.7,Vol.7:P1089-1091.
20岳殿武,徐澄沂.关于纠错码的若干新方向.重庆邮电学院学报. 2000(12):1-6
21吴瑕. RS码的研究与应用.西安:西安电子科技大学,2001
22刘培,葛建华,刘刚.级联卷积码的性能评估.电子学报.2003.7.31. P1089-1091.
23鄂炜,苏广川.高速Viterbi译码器的优化和实现.电子技术应用.2003(4):50-51
24程晓江,马晓军,刘洛馄.卷积码Viterbi译码器的FPAG的设计与实现.通信技术.2003(3):34-36
25孙晓岩,付永庆. Viterbi译码器的FPAG实现技术研究.应用科技.2003(5):11-13
26付永庆,孙晓岩,李福昌.实现Viterbi译码器幸存路径存储及译码输出的一种新方法.应用科技.2003(3):25-32
27 Omar Aitsab and Raxnesh Pyndiah,Performances of Concatenated Reed-Solomon code and convolution code with interleaved coding. IEEE.PP:934-938,1997.
28徐志军,徐光辉. VHDL程序设计及应用.清华大学出版社,2000:20-22
29卢毅. VHDL与数字电路设计.科学出版社,2001:263-265
30张雅绮,李锵. Verilog HDL高级数字设计.电子工业出版社,2006.
31冷长奎,王建新.数字电路与逻辑设计.第l版.南京:南京理工大学
32王霞,张传生等.级联码结合交织技术的纠错性能研究.无线通信技术. 2000.2:P29~32
33吴克颖,李晖.基于卷积码的码交织器的设计.计算机学报. 2000(4):382-385
34毕成余,赵力.交织在信道编码中的应用.信息技术与信息化. 2005(2):P36-38
35阮铭,徐友云,宋文涛.基于FGPA的高速Viterbi译码器设计与实现.电讯技术.2001(l):96-99
36张绍军,王新智.用Verilog硬件描述语言实现Viterbi译码.空军雷达学院学报.2002(12):61-63
37 H.M.Shao, T.K.Truong, L.J.Deutsh.Reed.“A VLSI design of a pipeline Reed-Solomon decoder”IEEE Trans. Compute, vol C-34,pp.393-402, May1985
38 Jah-ming Hau and Chin-Liang Wang.“An Area-Efficient Pipelined VLSI architecture for decoding of Reed-Solomon Codes Based on a Time-Domain Algorithm”. IEEE Trans. Circuit and system for video technology vol.7 No. 6, December 1997
39 S.T.J.Femn, M.Beaissa and D.Taylor.“Improved algorithm for division over GF(2m)”. Electronics Letters 4th March 1993 vol.29 no.5
40 Howard M.shao and Irving S.“On the VLSI Desing of a Pipeline Reed-Solomon Decoder Using Systolic Arrays”, IEEE trans. vol.37 No.10, October 1988
41 GeogeC.Clark. Error-CorrectionCoding for Dig-Communications. New York: Plenum Press, 1981
42 Cay Dholakia. Introduetion to Convolutional Codes and With Applications. Kluwer Ahead Publisher, 1994
43侯伯亨,顾新. VHDL硬件描述语言与数字逻辑电路设计.西安:西安电子科技大学出版社, 2004
44褚振勇,翁木云. FPGA设计及应用.西安:西安电子科技大学出版社, 2002
45 J.Yuan, B.Vucetic, W.Feng. Combined turbo codes and interleave design. IEEE Trans Cormnun, 1999, 47:484-487
2张忠培,史志平.现代编码理论与应用.国防工业出版社, 2007, 25
3肖国镇.编码理论.国防工业出版社, 1993
4贾世楼.信息理论基础(第二版).哈尔滨工业大学出版社,2001:P7-9
5 R.J.McEliece. The Theory of Information and Coding.第2版(美)电子工业出版社,2003:253-254
6王新梅,肖国振.纠错码原理与方法.西安:西安电子科技大学出版,2001
7冯重熙等.现代数字通信技术.第1版.北京:人民邮电出版社, 1987
8吴克颖,李晖,王育民.基于卷积码的码交织器的设计.计算机学报. 2000(4):382-385
9岳殿武,徐澄沂.关于纠错码的若干新方向.重庆邮电学院报.2000(12):1-6
10马秀莲等.数字通信差错控制技术.第1版.北京:中国铁道出版社,1991
11王进祥,毛志刚. RS译码器综述.微电子学, 1997(2):(115-120)
12汪晓岩等.基于复数基的RS译码器的FPGA优化实现.通信学报. 2003(4):85-93
13王进祥,张乃通.流水线结构RS(255,223)译码器的VSLI设计.计算机研究与发展, 2000(1):(61-65)
14 Colls K. ASIC synthesis of flexible 80Mbit/s Reed-Solomon code. EDA&T, Beijing,China,1994
15 D.V.Sarwate, N.R.Shanbag. High-Speed Architecture for Reed-Solomon Decoders. IEEE Trans. On VLSI Systems, 2001, 9(5):641-655
16 Maki,G K. VLSI Reed-Solomon decoder design. In:MILCOM’86.1986 IEEE Military Communications Conference, 1986, 3
17周世东,梅顺良,姚彦.并行级联卷积码的最新进展.电子学报. 1998(7):59-65
18王国立. RS+卷积级联码在无线本地环路中的性能分析.电子产品世界. 1999(12):27-28
19刘培,葛建华,刘刚.级联卷积码的性能评估.电子学报.2003.7,Vol.7:P1089-1091.
20岳殿武,徐澄沂.关于纠错码的若干新方向.重庆邮电学院学报. 2000(12):1-6
21吴瑕. RS码的研究与应用.西安:西安电子科技大学,2001
22刘培,葛建华,刘刚.级联卷积码的性能评估.电子学报.2003.7.31. P1089-1091.
23鄂炜,苏广川.高速Viterbi译码器的优化和实现.电子技术应用.2003(4):50-51
24程晓江,马晓军,刘洛馄.卷积码Viterbi译码器的FPAG的设计与实现.通信技术.2003(3):34-36
25孙晓岩,付永庆. Viterbi译码器的FPAG实现技术研究.应用科技.2003(5):11-13
26付永庆,孙晓岩,李福昌.实现Viterbi译码器幸存路径存储及译码输出的一种新方法.应用科技.2003(3):25-32
27 Omar Aitsab and Raxnesh Pyndiah,Performances of Concatenated Reed-Solomon code and convolution code with interleaved coding. IEEE.PP:934-938,1997.
28徐志军,徐光辉. VHDL程序设计及应用.清华大学出版社,2000:20-22
29卢毅. VHDL与数字电路设计.科学出版社,2001:263-265
30张雅绮,李锵. Verilog HDL高级数字设计.电子工业出版社,2006.
31冷长奎,王建新.数字电路与逻辑设计.第l版.南京:南京理工大学
32王霞,张传生等.级联码结合交织技术的纠错性能研究.无线通信技术. 2000.2:P29~32
33吴克颖,李晖.基于卷积码的码交织器的设计.计算机学报. 2000(4):382-385
34毕成余,赵力.交织在信道编码中的应用.信息技术与信息化. 2005(2):P36-38
35阮铭,徐友云,宋文涛.基于FGPA的高速Viterbi译码器设计与实现.电讯技术.2001(l):96-99
36张绍军,王新智.用Verilog硬件描述语言实现Viterbi译码.空军雷达学院学报.2002(12):61-63
37 H.M.Shao, T.K.Truong, L.J.Deutsh.Reed.“A VLSI design of a pipeline Reed-Solomon decoder”IEEE Trans. Compute, vol C-34,pp.393-402, May1985
38 Jah-ming Hau and Chin-Liang Wang.“An Area-Efficient Pipelined VLSI architecture for decoding of Reed-Solomon Codes Based on a Time-Domain Algorithm”. IEEE Trans. Circuit and system for video technology vol.7 No. 6, December 1997
39 S.T.J.Femn, M.Beaissa and D.Taylor.“Improved algorithm for division over GF(2m)”. Electronics Letters 4th March 1993 vol.29 no.5
40 Howard M.shao and Irving S.“On the VLSI Desing of a Pipeline Reed-Solomon Decoder Using Systolic Arrays”, IEEE trans. vol.37 No.10, October 1988
41 GeogeC.Clark. Error-CorrectionCoding for Dig-Communications. New York: Plenum Press, 1981
42 Cay Dholakia. Introduetion to Convolutional Codes and With Applications. Kluwer Ahead Publisher, 1994
43侯伯亨,顾新. VHDL硬件描述语言与数字逻辑电路设计.西安:西安电子科技大学出版社, 2004
44褚振勇,翁木云. FPGA设计及应用.西安:西安电子科技大学出版社, 2002
45 J.Yuan, B.Vucetic, W.Feng. Combined turbo codes and interleave design. IEEE Trans Cormnun, 1999, 47:484-487