基于TTA架构的ESL建模和仿真
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摘要
随着数字多媒体技术的发展,需要在更便宜和通用性更强的产品中集成更多的功能。嵌入式处理器是多媒体SoC芯片的核心。可定制的传输触发体系结构(Transport Triggered Architecture, TTA)处理器,作为IP核的形式开发,允许用户实现总线宽度、寄存器数量、指令集等的可配置和定制执行单元,做到功耗面积性能的最佳折中,在多媒体SoC设计中具有广阔的应用市场前景。而指令集仿真器是当今处理器设计及软件工程领域非常重要的一部分。它在已有的计算机系统上为开发中的处理器构造一个模拟平台,验证处理器的正确性和有效性,支持目标程序的运行和调试。硬件设计者用仿真器来评估目标处理器的性能,修改体系结构中的瓶颈。系统开发者用仿真器来开发编译器和操作系统,开发和测试他们的应用程序,实现软硬件协同开发。所以,实现可重定向的指令集仿真器在体系结构开发、早期系统识别以及软件逆向分析方面更占据不可或缺的地位。
本论文详细介绍了在法国TIMA Lab提供的Soclib电子系统级(Electronic System Level,ESL)设计硬件仿真平台上对TTA架构处理器的指令集仿真器的设计。总结了基于TTA架构的处理器指令集仿真器事务级建模(Transaction Level Model, TLM)的一整套方法。采用面向对象的设计技术,用SystemC高级语言设计实现了面向TTA架构的可重构处理器的周期精确及比特精确的指令仿真器。本论文给出的指令集仿真器,是基于TTA架构处理器进行嵌入式ASIP(Application Specific Instruction-set Processor)设计过程中所需的一个非常重要的工具。通过读取系统架构描述文件并进行解析,在已有的硬件功能单元描述库中选取相应的功能单元描述,搭建成所对应的体系结构,并在此体系结构上对不同的应用程序进行周期精确炜精确的仿真模拟。对于用户自定义的指令及功能单元,也可以通过提供的宏定义接口加入到仿真器中。
最后,集成到soclib仿真平台上搭建了Soc平台,进行了测试和验证。实验结果证明了本论文给出指令集仿真器ESL设计方法的正确性,并且实验结果显示本论文设计的TTA架构处理器的指令集仿真器,对硬件设计者和系统开发者都有较强的实用性。
With the development of digital multimedia technology, the cheaper and more generic products need more integration functionally. Embedded processor is the central of multi-media SoC chips. Customizable TTA processor, developed as a form of IP, allows the user to configure the bus width, the number of registers, instruction set, etc, and allows the user to customize the function Unit as well to make area-power performance to achieve the best compromise. And in today's processor design and software engineering, instruction set simulator is a very important part of the field. It can construct a simulation platform for the development of the processor on the computer systems available, to verify the correctness and effectiveness of the processor and to support the run and debug procedures of the target program. Hardware designers make use of to simulator assess the performance of the target processor and modify the structure of the bottlenecks in the system. System developers exploit emulator to develop compilers and operating systems, develop and test of their applications to achieve synergy of hardware and software development.Therefore, the implementation of retargetable instruction set simulator occupy an indispensable position in the early system development, identification, and software reverse analysis.
In this paper, the design of TTA processor instruction set simulator, which based on the hardware simulation platform Soclib provided by TIMA lab in French, in detail.Summarized a whole set of design methodology for Transaction Level Modeling of TTA processor instruction set simulator.And implemented the cycle-accurate bit-accurate instruction set simulator of TTA reconfigurable processors designed with high-level language SystemC, using Object-oriented design techniques. The given instruction set simulator in this paper,is a very important tool for the design process of embedded processors ASIP based on TTA.By reading and analysising a architecture description document, select the corresponding functional unit description in the functional unit description library, then construct the corresponding architecture,and to carry one cycle-accurate for different applications simulation in this architecture. For user-defined unit can also add to the simulator in a simple way.
Finally, we built SoC platform on soclib simulation platform, and carried on testing and validation. The experimental results proved the validity of the given instruction set simulator, and experimental results show that the TTA processor instruction set simulator has a strong practicality not only for hardware designers but also for system developers.
本论文详细介绍了在法国TIMA Lab提供的Soclib电子系统级(Electronic System Level,ESL)设计硬件仿真平台上对TTA架构处理器的指令集仿真器的设计。总结了基于TTA架构的处理器指令集仿真器事务级建模(Transaction Level Model, TLM)的一整套方法。采用面向对象的设计技术,用SystemC高级语言设计实现了面向TTA架构的可重构处理器的周期精确及比特精确的指令仿真器。本论文给出的指令集仿真器,是基于TTA架构处理器进行嵌入式ASIP(Application Specific Instruction-set Processor)设计过程中所需的一个非常重要的工具。通过读取系统架构描述文件并进行解析,在已有的硬件功能单元描述库中选取相应的功能单元描述,搭建成所对应的体系结构,并在此体系结构上对不同的应用程序进行周期精确炜精确的仿真模拟。对于用户自定义的指令及功能单元,也可以通过提供的宏定义接口加入到仿真器中。
最后,集成到soclib仿真平台上搭建了Soc平台,进行了测试和验证。实验结果证明了本论文给出指令集仿真器ESL设计方法的正确性,并且实验结果显示本论文设计的TTA架构处理器的指令集仿真器,对硬件设计者和系统开发者都有较强的实用性。
With the development of digital multimedia technology, the cheaper and more generic products need more integration functionally. Embedded processor is the central of multi-media SoC chips. Customizable TTA processor, developed as a form of IP, allows the user to configure the bus width, the number of registers, instruction set, etc, and allows the user to customize the function Unit as well to make area-power performance to achieve the best compromise. And in today's processor design and software engineering, instruction set simulator is a very important part of the field. It can construct a simulation platform for the development of the processor on the computer systems available, to verify the correctness and effectiveness of the processor and to support the run and debug procedures of the target program. Hardware designers make use of to simulator assess the performance of the target processor and modify the structure of the bottlenecks in the system. System developers exploit emulator to develop compilers and operating systems, develop and test of their applications to achieve synergy of hardware and software development.Therefore, the implementation of retargetable instruction set simulator occupy an indispensable position in the early system development, identification, and software reverse analysis.
In this paper, the design of TTA processor instruction set simulator, which based on the hardware simulation platform Soclib provided by TIMA lab in French, in detail.Summarized a whole set of design methodology for Transaction Level Modeling of TTA processor instruction set simulator.And implemented the cycle-accurate bit-accurate instruction set simulator of TTA reconfigurable processors designed with high-level language SystemC, using Object-oriented design techniques. The given instruction set simulator in this paper,is a very important tool for the design process of embedded processors ASIP based on TTA.By reading and analysising a architecture description document, select the corresponding functional unit description in the functional unit description library, then construct the corresponding architecture,and to carry one cycle-accurate for different applications simulation in this architecture. For user-defined unit can also add to the simulator in a simple way.
Finally, we built SoC platform on soclib simulation platform, and carried on testing and validation. The experimental results proved the validity of the given instruction set simulator, and experimental results show that the TTA processor instruction set simulator has a strong practicality not only for hardware designers but also for system developers.
引文
[1]JAAKKO SERTAMO , Processor Generator For Transport Triggered Architectures:[Master of Science Thesis],Tampere;Tampere University,2003
[2]Silicon Hive, AVISPA,massively Parallel Reconfigurable Accelerator, IEEE 0-7803-8160-2/3, 2003
[3]Henk Corporaal, TTAs: Missing the ILP complexity wall, Journal of systems architecture , vol. 45, pp. 949-973, 1999
[4]王伯文,基于超长指令架构与传输触发运算架构的改良式内嵌微控制器指令集结构设计:[硕士学位论文],台湾:国立台湾科技大学,2006
[5]Henk Corporaal Hans(J.M.) Mulder, MOVE: A framework for high performance processor design, Conference on High Performance Networking and Computing, Proceedings of the 1991 ACM/IEEE conference on Supercomputing,1991, 692-701
[6]孙延萌,朱霞,适合软件无线电片上系统的可重构处理器,中国集成电路,2004,61:33~37
[7]冯鑫,郭炜,基于ESL的MEPG-4解码SoC软硬件协同设计,计算机仿真,2007,24(10):257~260
[8]严迎建,刘明业.ARMv4指令集模拟器设计及优化技术,小型微型计算机系统,2005,26:1~3
[9]严迎建,徐劲松,基于指令集模拟器的处理器建模与验证,计算机工程,2008,34(5):248~250
[10]何虎,孙义和,面向寄存器的流水线处理器建模及验证方法,半导体学报,2003,24(1):98~102
[11]王颖,邵作之,王赛字,基于快速ISS建模技术的研究,计算机与网络,2005,21:60~61
[12]薛勃,周玉洁,MIPS32指令集兼容的CPU模拟器设计,计算机工程,2009,35(1):263~265
[13]邢文峰,姚庆栋,史册等,一种高速灵活的指令仿真器,计算机工程,2004,30(22):74~76
[14]岳虹,王志英,面向TTA结构的可重定向周期精确模拟器的设计与实现,计算机工程,2007,33(12):259~261
[15]何海涛,罗克露等,一种ARM处理器仿真器的设计,四川理工学院学报,2006,18(2):26~29
[16]Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, An Efficient Retargetable Framework for Instruction-Set Simulation, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2003,13~18
[17]Mehrdad Reshadi, Prabhat Mishra, Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation, International Proceedings of the 40th conference on Design automation,2003,758~763
[18]韩小琨,蒋烈辉,可重用的指令集模拟器的设计与优化技术,计算机工程,2008,34(7):61~63
[19]王琦,顾瑜,汪东升,高性能可重构指令集架构模拟技术,清华大学学报,2006,46(1):90~93
[20]崔光佐,程旭,佟冬,面向处理器的系统级模拟、仿真及调试技术--基于软硬件协同设计的新方法, JOURNAL OF COMPUTER RESEARCH &DEVELOPMENT,华北电力大学,2001,38(3):361~367
[21]万寒,龙翔,高小鹏,指令集模拟器发展现状评述,中国科技论文在线,2006,1~7
[22]甘孝松,SOC设计需从ESL开始——CoWare公司在华举办ESL设计研讨会,中国集成电路,2006,10:79~80
[23]李晋文,谈民,邢座程等,基于ESL的SOC系统级设计方法研究,2006,第十届计算机工程与工艺全国学术年会
[24]郭炜,郭筝,谢憬等,SoC设计方法与实现,北京:电子工业出版社,2007,10~13,50~64
[25]陶峰峰,付宇卓,DSP指令集仿真器的设计与实现,计算机仿真,2005,22(9):225~228
[26]王志刚,李曦,周学海等,可重定向的定制指令集处理器(ASIP)仿真技术研究,系统仿真学报,2007,19(6):1249~1255
[27]李曦,仲力,高研研,周期精确ASIP仿真器生成环境的研究,计算机仿真,2008,25(5):290~294
[28]Pekka J??skel?inen , Instruction Set Simulator For Transport Triggered Architectures:[Master of Science Thesis],Tampere;Tamp
[29]金方其,可重配置的时钟精确嵌入式处理器仿真平台的研究:[硕士学位论文],浙江;浙江大学,2006
[30]Federico Angiolini, Jianjiang Ceng, Rainer Leupers, An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration, European Design and Automation Association, 2006, 1145~1150
[31]Grotker Thorsten.,System design with SystemC,Boston:Kluwer Academic Publishers,2002
[32]Yon Jun Shin , Sofiène Tahar, A SystemC Transaction Level Model for the MIPS R3000 Processor, IEEE 4th International Conference: Sciences of Electronic,Technologies of Information and Telecommunications, 2007,1~8
[33]周剑扬,李诗勤,蒋小刚等,基于SystemC的RISC CPU行为描述,厦门大学学报,2004,43(1):40~45
[34]陈曦,徐宁仪,SystemC片上系统设计,北京:科学出版社,2004
[35]刘昊,基于ESL的AVS视频SoC解码器帧内预测算法研究与设计:[硕士学位论文],上海,上海交通大学,2008
[36]Soheil Samii, Modeling and Simulation with SystemC, Dept. of Computer and Information Science,2007,1~18
[37]Emmanuel Viaud, Franc?ois P?echeux, Alain Greiner, An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles, European Design and Automation Association, 2006, 94~99
[38]贾晓力,基于8051的TLM系统级模型的初步研究:[硕士学位论文],北京;华北电力大学,2004
[39]石晓郁,片上系统设计中的事务级建模方法,微计算机信息,2002,02Z:191~193
[40]童琨,边计年,片上系统设计中事务级建模技术综述,计算机辅助设计与图形学学报,2007,19(11):1365~1372
[41]Henk Corporaal,MOVE32INT Architecture and Programmer’s Reference Manual, Delft;Delft University,1994
[2]Silicon Hive, AVISPA,massively Parallel Reconfigurable Accelerator, IEEE 0-7803-8160-2/3, 2003
[3]Henk Corporaal, TTAs: Missing the ILP complexity wall, Journal of systems architecture , vol. 45, pp. 949-973, 1999
[4]王伯文,基于超长指令架构与传输触发运算架构的改良式内嵌微控制器指令集结构设计:[硕士学位论文],台湾:国立台湾科技大学,2006
[5]Henk Corporaal Hans(J.M.) Mulder, MOVE: A framework for high performance processor design, Conference on High Performance Networking and Computing, Proceedings of the 1991 ACM/IEEE conference on Supercomputing,1991, 692-701
[6]孙延萌,朱霞,适合软件无线电片上系统的可重构处理器,中国集成电路,2004,61:33~37
[7]冯鑫,郭炜,基于ESL的MEPG-4解码SoC软硬件协同设计,计算机仿真,2007,24(10):257~260
[8]严迎建,刘明业.ARMv4指令集模拟器设计及优化技术,小型微型计算机系统,2005,26:1~3
[9]严迎建,徐劲松,基于指令集模拟器的处理器建模与验证,计算机工程,2008,34(5):248~250
[10]何虎,孙义和,面向寄存器的流水线处理器建模及验证方法,半导体学报,2003,24(1):98~102
[11]王颖,邵作之,王赛字,基于快速ISS建模技术的研究,计算机与网络,2005,21:60~61
[12]薛勃,周玉洁,MIPS32指令集兼容的CPU模拟器设计,计算机工程,2009,35(1):263~265
[13]邢文峰,姚庆栋,史册等,一种高速灵活的指令仿真器,计算机工程,2004,30(22):74~76
[14]岳虹,王志英,面向TTA结构的可重定向周期精确模拟器的设计与实现,计算机工程,2007,33(12):259~261
[15]何海涛,罗克露等,一种ARM处理器仿真器的设计,四川理工学院学报,2006,18(2):26~29
[16]Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, An Efficient Retargetable Framework for Instruction-Set Simulation, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2003,13~18
[17]Mehrdad Reshadi, Prabhat Mishra, Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation, International Proceedings of the 40th conference on Design automation,2003,758~763
[18]韩小琨,蒋烈辉,可重用的指令集模拟器的设计与优化技术,计算机工程,2008,34(7):61~63
[19]王琦,顾瑜,汪东升,高性能可重构指令集架构模拟技术,清华大学学报,2006,46(1):90~93
[20]崔光佐,程旭,佟冬,面向处理器的系统级模拟、仿真及调试技术--基于软硬件协同设计的新方法, JOURNAL OF COMPUTER RESEARCH &DEVELOPMENT,华北电力大学,2001,38(3):361~367
[21]万寒,龙翔,高小鹏,指令集模拟器发展现状评述,中国科技论文在线,2006,1~7
[22]甘孝松,SOC设计需从ESL开始——CoWare公司在华举办ESL设计研讨会,中国集成电路,2006,10:79~80
[23]李晋文,谈民,邢座程等,基于ESL的SOC系统级设计方法研究,2006,第十届计算机工程与工艺全国学术年会
[24]郭炜,郭筝,谢憬等,SoC设计方法与实现,北京:电子工业出版社,2007,10~13,50~64
[25]陶峰峰,付宇卓,DSP指令集仿真器的设计与实现,计算机仿真,2005,22(9):225~228
[26]王志刚,李曦,周学海等,可重定向的定制指令集处理器(ASIP)仿真技术研究,系统仿真学报,2007,19(6):1249~1255
[27]李曦,仲力,高研研,周期精确ASIP仿真器生成环境的研究,计算机仿真,2008,25(5):290~294
[28]Pekka J??skel?inen , Instruction Set Simulator For Transport Triggered Architectures:[Master of Science Thesis],Tampere;Tamp
[29]金方其,可重配置的时钟精确嵌入式处理器仿真平台的研究:[硕士学位论文],浙江;浙江大学,2006
[30]Federico Angiolini, Jianjiang Ceng, Rainer Leupers, An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration, European Design and Automation Association, 2006, 1145~1150
[31]Grotker Thorsten.,System design with SystemC,Boston:Kluwer Academic Publishers,2002
[32]Yon Jun Shin , Sofiène Tahar, A SystemC Transaction Level Model for the MIPS R3000 Processor, IEEE 4th International Conference: Sciences of Electronic,Technologies of Information and Telecommunications, 2007,1~8
[33]周剑扬,李诗勤,蒋小刚等,基于SystemC的RISC CPU行为描述,厦门大学学报,2004,43(1):40~45
[34]陈曦,徐宁仪,SystemC片上系统设计,北京:科学出版社,2004
[35]刘昊,基于ESL的AVS视频SoC解码器帧内预测算法研究与设计:[硕士学位论文],上海,上海交通大学,2008
[36]Soheil Samii, Modeling and Simulation with SystemC, Dept. of Computer and Information Science,2007,1~18
[37]Emmanuel Viaud, Franc?ois P?echeux, Alain Greiner, An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles, European Design and Automation Association, 2006, 94~99
[38]贾晓力,基于8051的TLM系统级模型的初步研究:[硕士学位论文],北京;华北电力大学,2004
[39]石晓郁,片上系统设计中的事务级建模方法,微计算机信息,2002,02Z:191~193
[40]童琨,边计年,片上系统设计中事务级建模技术综述,计算机辅助设计与图形学学报,2007,19(11):1365~1372
[41]Henk Corporaal,MOVE32INT Architecture and Programmer’s Reference Manual, Delft;Delft University,1994