嵌入式存储器测试算法的研究与实现
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摘要
随着深亚微米技术的发展,嵌入式存储器在片上系统芯片(SoC)上占有越来越多的比重。由于嵌入式存储器中晶体管密集,存在高布线密度、高复杂度和高工作频率等因素,很容易发生物理缺陷。因此,研究高效率的测试算法,建立有效地嵌入式存储器测试方法,对提高芯片成品率,降低芯片生产成本具有十分重要的意义。测试算法是存储器测试的核心内容。算法的推导需要在故障覆盖率和算法复杂度上进行折衷。因此,如何得到低复杂度、高故障覆盖率的算法,是算法研究的难点。同时,存储器内建自测试(MBIST)电路作为附加测试电路,要求具有尽可能小的面积及功耗,而且不能影响存储器电路的正常工作。
本文从单一单元故障和耦合故障的13种存储器故障类型的研究出发,针对每种故障原语提出对应的March测试算法,通过这些测试算法的优化合并,推导出65nm工艺要求下的新型March 28算法,新算法可以检测所有现实的连接性故障、单一单元故障、耦合故障和数据保持故障,并且复杂度减少12.5%。对于用户自定义March算法的研究有一定的理论参考价值。之后生成了针对新算法的MBIST电路,在进行了优化升级之后应用于SoC上84个嵌入式存储器的测试,最后对MBIST电路的模块级和芯片级仿真结果表明,在不引入I/O管脚的情况下,可实现对存储器的测试。测试结果表明,本文设计的测试算法和电路满足研究设计要求,对实际应用提供了重要参考。
With the development of the submicron technology, embedded memories have occupied more area on SoC (system on chip). Because of the high frequency, complexity and the high density of the transistors and layout, the physical defacts occur on the embedded memories easily. So an effective algorithm and test method are significant to the yield improvement and product cost saving. The test algorithm is the kernel of the memory test. The inference of test algorithm must be tradeoff on the algorithm complexity and fault coverage. How to infer a low complexity and high fault coverage algorithm is the difficulty of algorithm reseach. Otherwise, the MBIST circuit is a additional test logic for chip, so area and power cost of the MBIST circuit must be limited properly.
This thesis researches the 13 kinds fault primitive of single-cell faults and coupling faults, develops the test algorithm for each fault primitive. The new test algorithm (March 28) has been infered based on the optimization of these algorithms for 65nm technology. The new algorithm can optimize the fault coverage and test time. It can detect all link-faults, all single-cell faults, all coupling faults and data retention fault. The algorithm complexity reduces 12.5%. Based on the March 28 algorithm, MBIST circuits are generated by EDA tool. The MBIST logic are optimized in chip level connecting and implemented in 84 memories on a chip which is based on Infineon 65nm technology. The simulation of the algorithm proves that the March 28 algorithm can detect more fault modes than March C+ and March LR. The simulation of the MBIST circuits in chip level proves that the MBIST logic can test embeded memory without increasing I/O pad. The test algorithm and MBIST circuit in this thesis satisfy all requirements in actual application.
本文从单一单元故障和耦合故障的13种存储器故障类型的研究出发,针对每种故障原语提出对应的March测试算法,通过这些测试算法的优化合并,推导出65nm工艺要求下的新型March 28算法,新算法可以检测所有现实的连接性故障、单一单元故障、耦合故障和数据保持故障,并且复杂度减少12.5%。对于用户自定义March算法的研究有一定的理论参考价值。之后生成了针对新算法的MBIST电路,在进行了优化升级之后应用于SoC上84个嵌入式存储器的测试,最后对MBIST电路的模块级和芯片级仿真结果表明,在不引入I/O管脚的情况下,可实现对存储器的测试。测试结果表明,本文设计的测试算法和电路满足研究设计要求,对实际应用提供了重要参考。
With the development of the submicron technology, embedded memories have occupied more area on SoC (system on chip). Because of the high frequency, complexity and the high density of the transistors and layout, the physical defacts occur on the embedded memories easily. So an effective algorithm and test method are significant to the yield improvement and product cost saving. The test algorithm is the kernel of the memory test. The inference of test algorithm must be tradeoff on the algorithm complexity and fault coverage. How to infer a low complexity and high fault coverage algorithm is the difficulty of algorithm reseach. Otherwise, the MBIST circuit is a additional test logic for chip, so area and power cost of the MBIST circuit must be limited properly.
This thesis researches the 13 kinds fault primitive of single-cell faults and coupling faults, develops the test algorithm for each fault primitive. The new test algorithm (March 28) has been infered based on the optimization of these algorithms for 65nm technology. The new algorithm can optimize the fault coverage and test time. It can detect all link-faults, all single-cell faults, all coupling faults and data retention fault. The algorithm complexity reduces 12.5%. Based on the March 28 algorithm, MBIST circuits are generated by EDA tool. The MBIST logic are optimized in chip level connecting and implemented in 84 memories on a chip which is based on Infineon 65nm technology. The simulation of the algorithm proves that the March 28 algorithm can detect more fault modes than March C+ and March LR. The simulation of the MBIST circuits in chip level proves that the MBIST logic can test embeded memory without increasing I/O pad. The test algorithm and MBIST circuit in this thesis satisfy all requirements in actual application.
引文
[1] Rajsuman R. System-on-a-chip: Design and Test. America: Advantest America R&D Center, Inc, 2000.
[2] Cheng WW. SOC testing methodology and practice. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2005.
[3] Semiconductor Industry Association. International Technology Roadmap for Semiconductors 1999 Edition Test and Test Equipment. 1999 : 16-18.
[4] Bardell PH, McAnney WH, Savir J. Built-in Test for VLSI: Pseudorandom Techniques. John Wiley&Sons, 1987: 10-12.
[5] Semiconductor Industry Association. International Technology Roadmap for Semiconductors 1999 Edition Test and Test Equipment. 1999 : 30-33.
[6] Michael L.Bushnell, D.Vishwani Agrawal.“Essentials of Electronic Testing for Digital ,Memory and Mixed-Signal VLSI Circuits”,USA:Kluwer Academic Publishers,2000.
[7] IEEE Standard 1149.1 IEEE Standard Test Access Port and Boundary Scanner Architecture。IEEE Press. 1990.
[8] Semiconductor Industry Association (SIA),“International Technology Roadmap for Semiconduct ors”2001 Edition.
[9]雷绍充,邵志标,梁峰,VLSI测试方法学和可测性设计,电子工业出版社,2005
[10] Mentor Graphics Corp., Scan and ATPG Process Guide V8.2007_3,2007
[11]王晓琴,黑勇,吴斌等,嵌入式存储器MBIST设计中内建自诊断功能研究,电子器件,Vol28,No.4,2005.
[12] Michael L. Bushnell, Vishwani D. Agrawal,超大规模集成电路测试——数字、存储器和混合信号系统,蒋安平,冯建华,王新安译,电子工业出版社,2005
[13] Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, et al.,“Full-Speed Field Programmable Memory BIST Supporting Multi-level Looping”, in Proc. IEEE International Workshop on Memory Technology, Design, and Testing , pp. 67-71,2005.
[14] A.J. van de Goor,“Testing Semiconductor Memories: Theory and Practice”, Chichester, UK: John Wiley & Sons,Inc.,1991.
[15]许伟达, IC测试原理-存储器和逻辑芯片的测试,半导体技术,vol.31,No.5,2006
[16] Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic,数字集成电路——电路、系统与设计,周润德等译,电子工业出版社,2004.
[17] Kim I, Zorian Y, Komoriya G. Built-in self-repair for embedded high density SRAM. Proceedings of International Test Conference. Washington DC: IEEE Computer Society Press, 1998: 1112-1119.
[18] Tehranipour MH, Navabi Z. An Effieient BIST method for testing of embedded SRAMs. Proceedings of IEEE International Symp on Circuits and System. Sydney: IEEE Computer Society Press, 2001: 56-61.
[19] Schanstra, Goor A. Industrial evaluation of stress combination for March tests applied to SRAMs. Proceedings of International Test Conference. Washington DC: IEEE Computer Society Press, 1999: 983-992.
[20] Hamdioui S, March SS. Test for all static simple RAM faults. Proceedings of IEEE International Workshop on Memory Technology, Design and Testing. Washington DC: IEEE Computer Society Press, 2002: 95-100.
[21] Ad J. van de Goor , Zaid Al-Ars,“Functional Memory Faults: A Formal Notation and aTaxonomy”, in Proc. IEEE VLSI Test Symposium (VTS) ,2000, pp. 281-290.
[22] R. D. Adams and E. S. Cooley,“Analysis of a deceptive read destructive memory fault model and recommended testing”, in Proc. IEEE North Atlantic Test Workshop, 1996, pp. 27–32.
[23] R. Dekker, F. Beenaker, and L. Thijssen,“A realistic fault model and test algorithm for static random access memories,”IEEE Trans. Computer- Aided Design, vol. 9, 1990,pp. 567–572.
[24] S. Hamdioui, A.J. van de Goor,“Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests”, in Proc. of Ninth Asian Test Symposium(ATS), 2000, pp. 131-138.
[25] A. Benso, S.Carlo,G.Natale ,et al.“Memory read faults:Taxonomy and automatic test generation”, in Proc of the 10th Asian Test Symposium. IEEE Computer Society Press, 2001, pp.157-163.
[26] Z. Al-Ars,A.J. van de Goor ,Braun J,et al.,“A memory specific notation for fault modeling”, in Proc of the 10th Asian Test Symposium.IEEE Computer Society Press, 2001, pp.43-48.
[27] S. Hamdioui, A.J. van de Goor and M. Rodgers,“March SS: A Test for All Static Simple RAM Faults”, In Proc. of IEEE International Workshop on Memory Technology, Design, and Testing, 2002, pp. 95-100.
[28] Z Al-Ars, A.J. van de Goor,“Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs”, in Proc. Design Automation Test Eur., 2001, pp. 496–503.
[29] S. Hamdioui, A.J. van de Goor,“Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests”, in Proc. of Ninth Asian Test Symposium, 2000, pp. 131-138.
[30] Goor VD. Testing Semiconductor Memories. New York: John Wiley, 1996.
[31] Prince B. Semiconductor Memories. New York: John Wilry, 1991.
[32] Sharma AK. Semiconductor Memories. New York: IEEE Press, 1997.
[33] Mentor Graphics Corp, MBISTArchitect Process Guide V8.2007_3,2007,pp.124-125.
[34] J Knaizuk Jr, CRP Hartmann,“An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories”, IEEE Transactions on Computers Vol 26 , No.11, 1977, pp.1141-1144
[35] R.Nair,“Comments on‘An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories”, IEEE Transactions on Computers ,Vol 28 , No.3 ,1979 ,pp258-261.
[36] MS. Abadir, HK. Reghbati,“Functional Testing of Semiconductor Random Access Memories”, ACM Computing Surveys, Vol15, No. 3, 1983, pp. 175– 198.
[37] Suk, D.S. Reddy, S.M.,“A March Test for Functional Faults in Semiconductor Random Access Memories”,IEEE Transactions on Computers, Vol. C-30, No. 12, 1981,pp. 982-985
[38] M. Marinescu,“Simple and efficient algorithms for functional RAM testing”, in Proc. IEEE International Test Conference, 1982, pp. 236–239.
[39] A.J. van de Goor and G. Gaydadjiev,“March LR: A Memory Test for Realistic Linked Faults”, in Proc. IEEE VLSI Test Symposium, 1996, pp. 272-280.
[40] Sultan M. Al-Harbi, Sandeep K. Gupta,“An Efficient Methodology for Generating Optimal and Uniform March Tests”, 19th IEEE VLSI Test Symposium, 2001, pp231.
[41] Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor,et al.,“Linked Faults in Random Access Memories: Concept,Fault Models, Test Algorithms, and Industrial Results”, IEEE trans. On Computer-Aided Design of Iintegated Circuits and Systems, Vol. 23, No.5,2004.
[2] Cheng WW. SOC testing methodology and practice. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2005.
[3] Semiconductor Industry Association. International Technology Roadmap for Semiconductors 1999 Edition Test and Test Equipment. 1999 : 16-18.
[4] Bardell PH, McAnney WH, Savir J. Built-in Test for VLSI: Pseudorandom Techniques. John Wiley&Sons, 1987: 10-12.
[5] Semiconductor Industry Association. International Technology Roadmap for Semiconductors 1999 Edition Test and Test Equipment. 1999 : 30-33.
[6] Michael L.Bushnell, D.Vishwani Agrawal.“Essentials of Electronic Testing for Digital ,Memory and Mixed-Signal VLSI Circuits”,USA:Kluwer Academic Publishers,2000.
[7] IEEE Standard 1149.1 IEEE Standard Test Access Port and Boundary Scanner Architecture。IEEE Press. 1990.
[8] Semiconductor Industry Association (SIA),“International Technology Roadmap for Semiconduct ors”2001 Edition.
[9]雷绍充,邵志标,梁峰,VLSI测试方法学和可测性设计,电子工业出版社,2005
[10] Mentor Graphics Corp., Scan and ATPG Process Guide V8.2007_3,2007
[11]王晓琴,黑勇,吴斌等,嵌入式存储器MBIST设计中内建自诊断功能研究,电子器件,Vol28,No.4,2005.
[12] Michael L. Bushnell, Vishwani D. Agrawal,超大规模集成电路测试——数字、存储器和混合信号系统,蒋安平,冯建华,王新安译,电子工业出版社,2005
[13] Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, et al.,“Full-Speed Field Programmable Memory BIST Supporting Multi-level Looping”, in Proc. IEEE International Workshop on Memory Technology, Design, and Testing , pp. 67-71,2005.
[14] A.J. van de Goor,“Testing Semiconductor Memories: Theory and Practice”, Chichester, UK: John Wiley & Sons,Inc.,1991.
[15]许伟达, IC测试原理-存储器和逻辑芯片的测试,半导体技术,vol.31,No.5,2006
[16] Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic,数字集成电路——电路、系统与设计,周润德等译,电子工业出版社,2004.
[17] Kim I, Zorian Y, Komoriya G. Built-in self-repair for embedded high density SRAM. Proceedings of International Test Conference. Washington DC: IEEE Computer Society Press, 1998: 1112-1119.
[18] Tehranipour MH, Navabi Z. An Effieient BIST method for testing of embedded SRAMs. Proceedings of IEEE International Symp on Circuits and System. Sydney: IEEE Computer Society Press, 2001: 56-61.
[19] Schanstra, Goor A. Industrial evaluation of stress combination for March tests applied to SRAMs. Proceedings of International Test Conference. Washington DC: IEEE Computer Society Press, 1999: 983-992.
[20] Hamdioui S, March SS. Test for all static simple RAM faults. Proceedings of IEEE International Workshop on Memory Technology, Design and Testing. Washington DC: IEEE Computer Society Press, 2002: 95-100.
[21] Ad J. van de Goor , Zaid Al-Ars,“Functional Memory Faults: A Formal Notation and aTaxonomy”, in Proc. IEEE VLSI Test Symposium (VTS) ,2000, pp. 281-290.
[22] R. D. Adams and E. S. Cooley,“Analysis of a deceptive read destructive memory fault model and recommended testing”, in Proc. IEEE North Atlantic Test Workshop, 1996, pp. 27–32.
[23] R. Dekker, F. Beenaker, and L. Thijssen,“A realistic fault model and test algorithm for static random access memories,”IEEE Trans. Computer- Aided Design, vol. 9, 1990,pp. 567–572.
[24] S. Hamdioui, A.J. van de Goor,“Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests”, in Proc. of Ninth Asian Test Symposium(ATS), 2000, pp. 131-138.
[25] A. Benso, S.Carlo,G.Natale ,et al.“Memory read faults:Taxonomy and automatic test generation”, in Proc of the 10th Asian Test Symposium. IEEE Computer Society Press, 2001, pp.157-163.
[26] Z. Al-Ars,A.J. van de Goor ,Braun J,et al.,“A memory specific notation for fault modeling”, in Proc of the 10th Asian Test Symposium.IEEE Computer Society Press, 2001, pp.43-48.
[27] S. Hamdioui, A.J. van de Goor and M. Rodgers,“March SS: A Test for All Static Simple RAM Faults”, In Proc. of IEEE International Workshop on Memory Technology, Design, and Testing, 2002, pp. 95-100.
[28] Z Al-Ars, A.J. van de Goor,“Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs”, in Proc. Design Automation Test Eur., 2001, pp. 496–503.
[29] S. Hamdioui, A.J. van de Goor,“Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests”, in Proc. of Ninth Asian Test Symposium, 2000, pp. 131-138.
[30] Goor VD. Testing Semiconductor Memories. New York: John Wiley, 1996.
[31] Prince B. Semiconductor Memories. New York: John Wilry, 1991.
[32] Sharma AK. Semiconductor Memories. New York: IEEE Press, 1997.
[33] Mentor Graphics Corp, MBISTArchitect Process Guide V8.2007_3,2007,pp.124-125.
[34] J Knaizuk Jr, CRP Hartmann,“An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories”, IEEE Transactions on Computers Vol 26 , No.11, 1977, pp.1141-1144
[35] R.Nair,“Comments on‘An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories”, IEEE Transactions on Computers ,Vol 28 , No.3 ,1979 ,pp258-261.
[36] MS. Abadir, HK. Reghbati,“Functional Testing of Semiconductor Random Access Memories”, ACM Computing Surveys, Vol15, No. 3, 1983, pp. 175– 198.
[37] Suk, D.S. Reddy, S.M.,“A March Test for Functional Faults in Semiconductor Random Access Memories”,IEEE Transactions on Computers, Vol. C-30, No. 12, 1981,pp. 982-985
[38] M. Marinescu,“Simple and efficient algorithms for functional RAM testing”, in Proc. IEEE International Test Conference, 1982, pp. 236–239.
[39] A.J. van de Goor and G. Gaydadjiev,“March LR: A Memory Test for Realistic Linked Faults”, in Proc. IEEE VLSI Test Symposium, 1996, pp. 272-280.
[40] Sultan M. Al-Harbi, Sandeep K. Gupta,“An Efficient Methodology for Generating Optimal and Uniform March Tests”, 19th IEEE VLSI Test Symposium, 2001, pp231.
[41] Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor,et al.,“Linked Faults in Random Access Memories: Concept,Fault Models, Test Algorithms, and Industrial Results”, IEEE trans. On Computer-Aided Design of Iintegated Circuits and Systems, Vol. 23, No.5,2004.