CMOS射频正交振荡器设计
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摘要
近年来,随着无线通信网络的飞速发展,近十年来,人们对射频前端收发机研究进入白热化的状态。目前国内外提出了许多射频前端收发机结构,如超外差式收发机、零中频收发机、低中频收发机等。射频正交振荡器是射频前端收发机的最重要组成部分,所以对其的研究自然具有重要的意义。在深刻地了解了振荡器在国内外的发展现状,仔细研究了振荡器的相位噪声理论、正交信号产生的原理以及低电压低功耗设计方法的基础上。作者设计了两个新型的正交差分式振荡器,然后利用ADS和Cadence软件对这些电路进行仿真验证和版图设计。本文主要的研究工作如下:
1)提出了一种新型的2.4-GHz CMOS正交差分式压控振荡器,在该电路中,两个完全相同的负阻振荡器通过电容进行耦合,从而达到产生正交差分信号的目的。由于是通过电容耦合,因此不会对振荡器引入额外的噪声和功耗,采用CMOS工艺仿真结果表明:电源电压为1.6V,功耗为7.2mW,相位噪声低至-128.4dBc/Hz@1MHz,能够满足零中频接收机苛刻的相位噪声要求。
2)提出了一种新型的高频低电压低功耗的正交差分式电容电感压控振荡器,在该电路中,两个完全相同的负阻振荡器是通过二极管耦合来实现产生正交差分信号的目的。其电源电压可以低至0.8V,功耗仅为2mW,相位噪声为-111.4dBc/Hz@1MHz。该电路能够满足超宽带频率合成器的性能要求,可应用于超宽带频率合成器。
3)本文提出的电路由ADS软件仿真,采用TSMC 0.18μm CMOS工艺,并利用Candence软件进行版图设计和后仿真,验证了电路的可行性。
In recent years, with the rapid development of wireless correspondence network, the research to the radio frequency transceiver enters the superheating condition. At present, many radio frequency transceiver structures are proposed in domestic & foreign area, like superheterodyne transceiver, zero-intermediate frequency transceiver, low-intermediate frequency transceiver and so on. The radio frequency quadrature oscillator is the most important constituent of radio frequency transceiver, therefore we will have the vital significance to research on it. In the foundation of profoundly understanding the present development situation of the oscillator in domestic and foreign area, carefully studying the oscillator phase noise theory、principle that quadrature signal produces as well as low voltage & low power loss design method, the author designs two new quadrature difficult oscillators, with the characteristic of low phase noise, low voltage & low power loss,then uses ADS and Cadence to carry on the simulation confirmation and layout design for these circuits. The main research work of this article is as follow:
1) In the proposed new 2.4-GHz CMOS quadrature difficult Voltage-controlled oscillator, two identical negative-resistance oscillators are coupled to each other via two capacitors in such a way that quadrature differential signals are generated. Since capacitor is used as coupling device, the proposed circuit has the advantage that no extra noise sources and power consumption are introduced to the circuit in the coupling process. Simulation results are presented for circuits designed with CMOS technology. The simulation result indicates: the circuit draws 7.2 mW from a 1.6-V supply. It can satisfy the harsh phase noise request of zero-intermediate frequency receiver if the phase noise lowers to - 128.4dBc/Hz@1MHz.
2) Proposes one kind of new high frequency,low voltage & low power comsuption quadrature difficult LC Voltage-controlled oscillator, in this proposed circuit, two identical negative-resistance oscillators are coupled to each other via diode, in such a way that quadrature differential signals are generated . Its voltage supply may lower to 0.8V, the power consumption is only 2mW, and the phase noise is - 111.4dBc/Hz@1MHz, this proposed circuit can be applied in the ultra-wide band frequency synthesizer, which can satisfy the performance requirement of the ultra-wide band frequency synthesizer.
3) The proposed circuits are simulated in TSMC RF CMOS 0.18μm technology by ADS2006, and Cadence is applied to the layout design and post-layout simulation, which confirms the feasibility of proposed circuit.
1)提出了一种新型的2.4-GHz CMOS正交差分式压控振荡器,在该电路中,两个完全相同的负阻振荡器通过电容进行耦合,从而达到产生正交差分信号的目的。由于是通过电容耦合,因此不会对振荡器引入额外的噪声和功耗,采用CMOS工艺仿真结果表明:电源电压为1.6V,功耗为7.2mW,相位噪声低至-128.4dBc/Hz@1MHz,能够满足零中频接收机苛刻的相位噪声要求。
2)提出了一种新型的高频低电压低功耗的正交差分式电容电感压控振荡器,在该电路中,两个完全相同的负阻振荡器是通过二极管耦合来实现产生正交差分信号的目的。其电源电压可以低至0.8V,功耗仅为2mW,相位噪声为-111.4dBc/Hz@1MHz。该电路能够满足超宽带频率合成器的性能要求,可应用于超宽带频率合成器。
3)本文提出的电路由ADS软件仿真,采用TSMC 0.18μm CMOS工艺,并利用Candence软件进行版图设计和后仿真,验证了电路的可行性。
In recent years, with the rapid development of wireless correspondence network, the research to the radio frequency transceiver enters the superheating condition. At present, many radio frequency transceiver structures are proposed in domestic & foreign area, like superheterodyne transceiver, zero-intermediate frequency transceiver, low-intermediate frequency transceiver and so on. The radio frequency quadrature oscillator is the most important constituent of radio frequency transceiver, therefore we will have the vital significance to research on it. In the foundation of profoundly understanding the present development situation of the oscillator in domestic and foreign area, carefully studying the oscillator phase noise theory、principle that quadrature signal produces as well as low voltage & low power loss design method, the author designs two new quadrature difficult oscillators, with the characteristic of low phase noise, low voltage & low power loss,then uses ADS and Cadence to carry on the simulation confirmation and layout design for these circuits. The main research work of this article is as follow:
1) In the proposed new 2.4-GHz CMOS quadrature difficult Voltage-controlled oscillator, two identical negative-resistance oscillators are coupled to each other via two capacitors in such a way that quadrature differential signals are generated. Since capacitor is used as coupling device, the proposed circuit has the advantage that no extra noise sources and power consumption are introduced to the circuit in the coupling process. Simulation results are presented for circuits designed with CMOS technology. The simulation result indicates: the circuit draws 7.2 mW from a 1.6-V supply. It can satisfy the harsh phase noise request of zero-intermediate frequency receiver if the phase noise lowers to - 128.4dBc/Hz@1MHz.
2) Proposes one kind of new high frequency,low voltage & low power comsuption quadrature difficult LC Voltage-controlled oscillator, in this proposed circuit, two identical negative-resistance oscillators are coupled to each other via diode, in such a way that quadrature differential signals are generated . Its voltage supply may lower to 0.8V, the power consumption is only 2mW, and the phase noise is - 111.4dBc/Hz@1MHz, this proposed circuit can be applied in the ultra-wide band frequency synthesizer, which can satisfy the performance requirement of the ultra-wide band frequency synthesizer.
3) The proposed circuits are simulated in TSMC RF CMOS 0.18μm technology by ADS2006, and Cadence is applied to the layout design and post-layout simulation, which confirms the feasibility of proposed circuit.
引文
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[2] Maeda T, Matsuno N, Hori S, et al. A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver. IEEE Journal of Solid-State Circuits 2006, 41(11): 2481-2490
[3] Jayaraman A, Terry B, Fransis B, et al. A fully integrated broadband direct- conversion receiver for DBS applications. In:IEEE International Solid-State Circuits Conference. San Francisco, 2000, 140-141
[4] Leeuwenburgh A J, Ter Laak J, Mulders A G, et al. A 1.9GHz fully integrated CMOS DECT transceiver. In: IEEE International Solid-State Circuits Conference. San Francisco, 2003. 450-507
[5] Porret A, Melly T, Python D, et al. An ultra low-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver. IEEE Journal of Solid-State Circuits, 2001, 36(3): 452-466
[6] Batra A, Balakrishnan J, Dabak A. Multi-band OFDM physical layer proposal for IEEE 802.15Task Group 3a. UTI, 2004, 8-11
[7]王春光,周正.超宽带无线通信标准的演进与展望.电信技术,2004,3(6):28-30
[8] Phillip EAllen, Douglas R, Holberg. CMOS Analog Circuit Design. London: Oxford University Press,2005,92-130
[9] Kiat Seng Yeo, Samir S.Rofail, Wang Ling Goh.低压低功耗CMOS/ Bi-CMOS超大规模集成电路.北京:电子工业出版社, 2003: 13-14
[10] Alfio Zanchi, Carlo Samori, Salvatore Levantino, et al. A 2-V 2.5-GHz 104-DbC/Hz at 100 KHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop. IEEE Journal of Solid-State Circuits, 2001, 36(4): 611-618
[11] Nestoras Tzartzanis, William W Walker. A Reversible Poly-Phase Distributed VCO. In: IEEE International Solid-State Circuits Conference. San Francisco, 2006, 2452-2461
[12] Alan W L Ng, Howard C Luong. A 1V 17GHz 5mW Quadrature CMOS VCO based on Transformer Coupling. IEEE International Solid-State Circuits Conference, 2006, 198-199
[13] Ren-Chieh Liu, Hong-Yeh Chang, Chi-Hsueh Wang, et al. A 63 GHz VCO Using a Standard 0.15μm CMOS Process. IEEE International Solid-State Circuits Conference, 2004, 446-447
[14] Jean-Olivier Plouchart, Noah Zamdmer, et al. A 44GHz Differentially Tuned VCO with 4GHz Tuning Range in 0.12μm SOI CMOS. In: IEEE International Solid-State Circuits Conference. San Francisco, 2002, 416-418
[15] Frank Zhang, Peter R Kinget. Design of Components and Circuits Underneath Integrated Inductors. IEEE Journal of Solid-State Circuits, 2006, 41(10): 2265-2271
[16] Sang-Woong Yoon, Stephan Pinel, Joy Laskar. High-Performance 2-GHz CMOS LC VCO with High-Q Embedded Inductors Using Wiring Metal Layer in a Package. IEEE Transactions on Advanced Packaging, 2006, 29(3): 639-646
[17] Wallace Ming, Yip Wong, Ping Shing Hui, et al. A Wide Tuning Range Gated Varactor. IEEE Journal of Solid-State Circuits, 2000, 35(5): 773-779
[18] Scott A Wartenberg, John R Hauser. Substrate voltage and accumulation-mode MOS varactor capacitance. IEEE Transactions on Electron Devices, 2005, 52(7): 1563-1567
[19] Ali Hajimiri, Thomas H Lee. A General Theory of Phase Noise in Electrical Oscillators. IEEE Journal of Solid-State Circuits, 1998, 33(2): 179-194
[20] Radu Fetche, Cristina Fetche. Analysis of the Effects of Supply Noise Coupling on Phase Noise in Integrated LC CMOS Oscillators. In: IEEE Radio and Wireless Conference. Denver, 2000, 199-202
[21] Pietro Andreani, Ali Fard. A 2.3 GHz LC-Tank CMOS VCO with Optimal Phase Noise Performance. In: IEEE International Solid-State Circuits Conference. San Francisco, 2006, 691-700
[22]池保勇,余志平,石秉学. CMOS射频集成电路分析与设计.北京:清华大学出版社,2006,153-154
[23]王志华,昊恩德. CMOS射频集成电路的现状与进展.电子学报. 2001, 29(2): 233-238
[24] Kiss P, Prodanov V. One-tap wideband I/Q compen-sation for zero-IF filters. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2004, 51(6):1062-1074
[25] Byun S, Park C-H, Song Y, et a1.A low-power CMOS bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. IEEE Journal of Solid State Circuits, 2003, 38(10): 1609-1618
[26]张国艳,黄如,张兴. CMOS射频集成电路的研究进展.微电子学, 2004,34(4):277-283
[27]拉扎维.模拟CMOS集成电路设计.西安:西安交通大学出版社,2002,391-393
[28]池保勇,余志平,石秉学. CMOS射频集成电路分析与设计.北京:清华大学出版社,2006,379-386
[29] Andreani P, Bonfanti A, Romano L, et al. Analysis and design of a 1.8-GHz CMOS LC quadrature VCO.IEEE Journal of Solid-State Circuits, 2002, 37(12): 1737-1747
[30] Maligeorgos J P, long J R. A low voltage 5.1-5.8 GHz image reject receiver with wide dynamic range. IEEE Journal of solid-state circuits, 2000, 35(7):1917-1926
[31] A Mazzanti, P Uggetti, F Svelto. Analysis and design of injection-locked LC dividers for quadrature generation. IEEE Journal of Solid-State Circuits, 2004,39(3):1425-1433
[32] Sheng-Lyang Jang, Huang S S, Chien-Feng Lee, et al. CMOS Quadrature VCO Implemented With Two First-Harmonic Injection-Locked Oscillators. IEEE microwave and wireless components letters, 2008, 18(10): 695-697
[33] Chamas I R, Raman S. Analysis and Design of a CMOS Phase-Tunable Injection- Coupled LC Quadrature VCO (PTIC-QVCO). IEEE Journal of Solid-State Circuits, 2009, 44(3): 784-796
[34] Wu Xiushan, Wang Zhigong, Li Zhiqun, et al. Design of a 4.6 GHz high performance quadrature CMOS VCO using transformer couple. Journal of Semiconductors, 2009, 30(2): 1-4
[35] Thomas H Lee, Ali Hajimiri. Oscillator Phase Noise: A Tutorial. IEEE Journal of Solid-State Circuits, 2000, 35(3): 326- 336
[36] Leeson D B. A simple model of feedback oscillator noise pectrum. Proceedings of the IEEE, 1966, 54(2): 329-330
[37] Ali Hajimiri, Thomas H Lee. Design Issues in CMOS LC Oscillators. IEEE Journal Solid-State Circuits, 1999,34(5): 717-724
[38] Ali Hajimiri, Thomas H Lee. A General Theory of Phase Noise. IEEE Journal Solid-State Circuits, 1998, 33(2): 179-193
[39] Brandolini G D, Rossi P, Manstretta D, et al. Toward Multistandard mobile terminals-Fully Integrated Receivers Requirements and Architectures. IEEE Transactions on Microwave Theory and Techniques, 2005, 53(3): 1026-1038
[40] Rofougaran A, Rael J, Rofougaran M, et al. A 900 MHz CMOS LC-oscillatorwith quadrature outputs. In: IEEE International Solid-State Circuits Conference, 1996, San Francisco, 392-393
[41] Frioui O, Zaid L, ahajandraibe w, et al. A very low phase noise fully integrated CMOS quadrature LC oscillator for 2.4 GHz bluetooth/WLAN applications. In: International Symposium on Communications and Information Technologies. Sydney, 2007, 55-60
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