实时时钟RTC的IP研究
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摘要
随着集成电路向着深亚微米的制造、设计技术的发展,集成电路已经步入高速发展的SOC时代。顺应信息产业的发展和市场需求,人们对芯片系统的性能提出了更高的要求,片上系统的规模越来越大。此时的设计问题已不再是单个芯片是否有能力容纳系统设计,而是设计如何跟上芯片设计复杂性的增长步伐,以及如何满足激烈的市场竞争对产品上市时间越来越苛刻的要求。在片上系统设计变得异常复杂的今天,基于芯核的设计已经成为EDA发展的必然趋势。开发具有自主知识产权的IP核则更具有广泛的应用前景。
本文在智能监控SOC系统芯片平台下,对该SOC中的一个子IP模块实时时钟的IP核设计进行了深入研究。在介绍IP核的特点及可复用型IP核的设计方法及设计中的关键技术的基础上,对RTC模块进行了可复用IP软核的设计。将整个实时时钟系统划分为多个功能模块,介绍了各个子模块各自要实现的功能和部分模块的算法。通过对SOC设计中低功耗设计方法和可综合代码编写规则的研究,采用IP核重用技术和当前流行的VerilogHDL硬件描述语言设计,使用高层综合的方法对各个模块进行设计描述,利用EDA工具对系统进行了仿真综合,完成了RTC模块的软IP核的设计。
本文研究的重点是基于该RTC IP软核设计的基础,结合设计中出现的相关问题,对RTC模块设计中的关键技术方法即多时钟域设计技术的研究。详细介绍了数字电路设计中的各种时钟和多时钟系统中常常碰到的亚稳态问题及解决方案。考虑到系统的稳定性和避免多时钟域中亚稳态现象的产生,重点研究了异步控制信号和数据通路的同步技术,给出了多种同步的电路设计方法和RTL实现方法,对不同时钟域信号做了分类描述并比较了各自特点,归纳总结了SOC设计中的时钟设计策略。这成为本文的创新点。
As the development of the design and manufacture technology of nano-meter Integrated Circuit(IC), IC has come into the high-speed SOC (System On Chip) age. Higher request has been brought forward to the capability of the chip system, and scale of SOC is increasing for the demand of the information industry and market. The design problem is not whether a chip is able to accommodate to the system design, but whether the design can catch up with the increasing speed of complexity for a chip and meet the requirements that the market competition is strict with the time that produces come into market. Nowadays, a design based on chip cores has become a trend towards the EDA development. It is promising to develop IP (Intellectual Property) cores with independent intellectual property right.
We have done some research on an IP core design of real time clock RTC based upon the intelligent monitor system SOC. A reused IP soft core is designed for the RTC module under the key design method and technology of the reused IP core. Firstly, the total clock system was divided into several function modules, whose functions and arithmetic were introduced. And then, through discussing the way of low power design in SOC and synthesizable coding, we used the IP core reuse technology and VerilogHDL, described the design of the modules by the high-level synthesis and simulated the system by the EDA. The design of RTC module’s IP soft core was finished.
The key problem of the paper is the research of the multi-clock system and technology design, plus the problems during the design. The basic is the RTC IP soft core design. We introduced the clocks in the digital circuit design and presented some met-stable state phenomenon of the multi-clock system and how to solve. Considering the stability of the system and the met-stable state phenomenon in multiple clock system, the synchronous way of asynchronous control signal and the data path are researched, and we did some research on the design method of many synchronous circuits design and RTL, compared some kinds of clock system signals and summarized the clock design of the SOC. All above are the creative points of the paper.
本文在智能监控SOC系统芯片平台下,对该SOC中的一个子IP模块实时时钟的IP核设计进行了深入研究。在介绍IP核的特点及可复用型IP核的设计方法及设计中的关键技术的基础上,对RTC模块进行了可复用IP软核的设计。将整个实时时钟系统划分为多个功能模块,介绍了各个子模块各自要实现的功能和部分模块的算法。通过对SOC设计中低功耗设计方法和可综合代码编写规则的研究,采用IP核重用技术和当前流行的VerilogHDL硬件描述语言设计,使用高层综合的方法对各个模块进行设计描述,利用EDA工具对系统进行了仿真综合,完成了RTC模块的软IP核的设计。
本文研究的重点是基于该RTC IP软核设计的基础,结合设计中出现的相关问题,对RTC模块设计中的关键技术方法即多时钟域设计技术的研究。详细介绍了数字电路设计中的各种时钟和多时钟系统中常常碰到的亚稳态问题及解决方案。考虑到系统的稳定性和避免多时钟域中亚稳态现象的产生,重点研究了异步控制信号和数据通路的同步技术,给出了多种同步的电路设计方法和RTL实现方法,对不同时钟域信号做了分类描述并比较了各自特点,归纳总结了SOC设计中的时钟设计策略。这成为本文的创新点。
As the development of the design and manufacture technology of nano-meter Integrated Circuit(IC), IC has come into the high-speed SOC (System On Chip) age. Higher request has been brought forward to the capability of the chip system, and scale of SOC is increasing for the demand of the information industry and market. The design problem is not whether a chip is able to accommodate to the system design, but whether the design can catch up with the increasing speed of complexity for a chip and meet the requirements that the market competition is strict with the time that produces come into market. Nowadays, a design based on chip cores has become a trend towards the EDA development. It is promising to develop IP (Intellectual Property) cores with independent intellectual property right.
We have done some research on an IP core design of real time clock RTC based upon the intelligent monitor system SOC. A reused IP soft core is designed for the RTC module under the key design method and technology of the reused IP core. Firstly, the total clock system was divided into several function modules, whose functions and arithmetic were introduced. And then, through discussing the way of low power design in SOC and synthesizable coding, we used the IP core reuse technology and VerilogHDL, described the design of the modules by the high-level synthesis and simulated the system by the EDA. The design of RTC module’s IP soft core was finished.
The key problem of the paper is the research of the multi-clock system and technology design, plus the problems during the design. The basic is the RTC IP soft core design. We introduced the clocks in the digital circuit design and presented some met-stable state phenomenon of the multi-clock system and how to solve. Considering the stability of the system and the met-stable state phenomenon in multiple clock system, the synchronous way of asynchronous control signal and the data path are researched, and we did some research on the design method of many synchronous circuits design and RTL, compared some kinds of clock system signals and summarized the clock design of the SOC. All above are the creative points of the paper.
引文
[1]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.1-2.
[2]皇甫红军.多功能实时时钟的ASIC设计.成都:电子科技大学,2002.12.1-2.
[3]电子产品世界.IP、SOC与设计技术.1999.
[4]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.7-8.
[5]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.68
[6]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.69
[7] Lionel Bening,Harry Foster. Principles of Verifiable RTL Design.Kluwer Academic Publishers.2000.
[8]王志华,邓仰东.数字集成系统的结构化设计与高层次综合.北京:清华大学出版社,2000.
[9]杨之廉,申明.超大规模集成电路设计方法学导论.第二版。北京:清华大学出版社,2000.
[10] HISYS.DSP2160 Reference Manual.
[11] MOTOROLA.MC9328MX1 Reference Manual.
[12]皇甫红军.多功能实时时钟的ASIC设计.成都:电子科技大学,2002.12.12-16.
[13]夏宇闻.Verilog HDL与逻辑系统设计.电子技术应用.1997.9.
[14]夏宇闻.复杂数字电路与系统的Verilog HDL设计技术.北京:北京航空航天大学出版社.1998.8.
[15]牛风举,刘元成,朱明程.基于IP复用的数字IC设计技术.北京:电子工业出版社,2003.
[16] IEEE Standard for Verilog Register Transfer Level Synthesis.IEEE Std,364.1.2002.
[17] Design Compiler Reference Manual: Constraints and Timing, Version U-2003.06.
[18] J.Bhasker.Verilog HDL综合实用教程.北京:清华大学出版社,2004.
[19] Darren Jones.How To Successfully Use Gated Clocking in an ASIC Design.SUNG Boston.2002.
[20]朱永峰,陆生礼,茆邦琴.SOC设计中的多时钟域处理.电子工程师.2003,29(11).60-63.
[21] Clifford E.Cummings.Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs.SUNG San Jose 2001.
[22]詹文法,张溯,周干民等.芯片设计中时钟问题的探讨.自动化理论、技术与应用.472-473.
[23]朱永峰,陆生礼,茆邦琴.SOC设计中的多时钟域处理.电子工程师.2003,29(11).60-70.
[24]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.109-113.
[25]谢修祥,王广生.异步多时钟系统的同步设计技术.电子工程师.2005.5,31(5).
[26]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.115.
[27]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.117-118.
[28]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.118-122.
[29] Mike Stein, Paradigm Works.跨越鸿沟:同步世界中的异步信号.EDA CHINA电子设计技术.2004.
[30]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.122-124.
[31]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.219-220.
[32]钟涛,王豪材.ASIC功耗估计和分析技术.微电子学.1999,29(6).395-401.
[33] B.Moyer. Low-power design for embedded processors.Proceedings of the IEEE.2001,89(11).1576-1587.
[34] Chandrakasan, Anantha,Brodersen. Low Power Digital CMOS Design.Kluwer Academic Publishers.1995.
[35] H.Li,S.Bhunia, Y.Chen,K.Roy, and T.N.Vijaykumar, DCG. Deterministic Clock-Gating for Low-Power Microprocessor Design. Very Large Scale Integration(VLSI) Systems.IEEE Transactions on .2004,12(3).245-254.
[36] Qing Wu,M.Pedram,and Xunwei Wu, Clock-gating and its application to low power design of sequential circuits.Circuits and Systems I.Fundamdental Theory and Applications.IEEE Transactions on [see also Circuits and Systems I:Regular Papers.IEEE Transactions on].2000,47(3).32-39.
[37] A.Mukheijee and M.Marek-Sadowska.Clock and power gating with timing closure. Design & Test of Computers.IEEE.2003,20(3).32-39.
[38] Qi Wang and S.Roy.Power minimization by clock root gating.Design Automation Conference.2003.Proceedings of the ASP-DAC 2003.Asia and South Pacific 2003.
[39] Darren Jones. How to successfully use gated clocking in an ASIC design. SUNG report.
[40]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.227-228.
[2]皇甫红军.多功能实时时钟的ASIC设计.成都:电子科技大学,2002.12.1-2.
[3]电子产品世界.IP、SOC与设计技术.1999.
[4]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.7-8.
[5]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.68
[6]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.69
[7] Lionel Bening,Harry Foster. Principles of Verifiable RTL Design.Kluwer Academic Publishers.2000.
[8]王志华,邓仰东.数字集成系统的结构化设计与高层次综合.北京:清华大学出版社,2000.
[9]杨之廉,申明.超大规模集成电路设计方法学导论.第二版。北京:清华大学出版社,2000.
[10] HISYS.DSP2160 Reference Manual.
[11] MOTOROLA.MC9328MX1 Reference Manual.
[12]皇甫红军.多功能实时时钟的ASIC设计.成都:电子科技大学,2002.12.12-16.
[13]夏宇闻.Verilog HDL与逻辑系统设计.电子技术应用.1997.9.
[14]夏宇闻.复杂数字电路与系统的Verilog HDL设计技术.北京:北京航空航天大学出版社.1998.8.
[15]牛风举,刘元成,朱明程.基于IP复用的数字IC设计技术.北京:电子工业出版社,2003.
[16] IEEE Standard for Verilog Register Transfer Level Synthesis.IEEE Std,364.1.2002.
[17] Design Compiler Reference Manual: Constraints and Timing, Version U-2003.06.
[18] J.Bhasker.Verilog HDL综合实用教程.北京:清华大学出版社,2004.
[19] Darren Jones.How To Successfully Use Gated Clocking in an ASIC Design.SUNG Boston.2002.
[20]朱永峰,陆生礼,茆邦琴.SOC设计中的多时钟域处理.电子工程师.2003,29(11).60-63.
[21] Clifford E.Cummings.Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs.SUNG San Jose 2001.
[22]詹文法,张溯,周干民等.芯片设计中时钟问题的探讨.自动化理论、技术与应用.472-473.
[23]朱永峰,陆生礼,茆邦琴.SOC设计中的多时钟域处理.电子工程师.2003,29(11).60-70.
[24]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.109-113.
[25]谢修祥,王广生.异步多时钟系统的同步设计技术.电子工程师.2005.5,31(5).
[26]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.115.
[27]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.117-118.
[28]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.118-122.
[29] Mike Stein, Paradigm Works.跨越鸿沟:同步世界中的异步信号.EDA CHINA电子设计技术.2004.
[30]郭炜,郭筝,谢憬.SOC设计方法与实现.北京:电子工业出版社,2007.6.122-124.
[31]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.219-220.
[32]钟涛,王豪材.ASIC功耗估计和分析技术.微电子学.1999,29(6).395-401.
[33] B.Moyer. Low-power design for embedded processors.Proceedings of the IEEE.2001,89(11).1576-1587.
[34] Chandrakasan, Anantha,Brodersen. Low Power Digital CMOS Design.Kluwer Academic Publishers.1995.
[35] H.Li,S.Bhunia, Y.Chen,K.Roy, and T.N.Vijaykumar, DCG. Deterministic Clock-Gating for Low-Power Microprocessor Design. Very Large Scale Integration(VLSI) Systems.IEEE Transactions on .2004,12(3).245-254.
[36] Qing Wu,M.Pedram,and Xunwei Wu, Clock-gating and its application to low power design of sequential circuits.Circuits and Systems I.Fundamdental Theory and Applications.IEEE Transactions on [see also Circuits and Systems I:Regular Papers.IEEE Transactions on].2000,47(3).32-39.
[37] A.Mukheijee and M.Marek-Sadowska.Clock and power gating with timing closure. Design & Test of Computers.IEEE.2003,20(3).32-39.
[38] Qi Wang and S.Roy.Power minimization by clock root gating.Design Automation Conference.2003.Proceedings of the ASP-DAC 2003.Asia and South Pacific 2003.
[39] Darren Jones. How to successfully use gated clocking in an ASIC design. SUNG report.
[40]马光胜,冯刚.SOC设计与IP核重用技术.北京:国防工业出版社,2006.8.227-228.