16位高速CMOS流水线模数转换器关键技术研究
|
摘要
模数转换器（ADC）已广泛应用于无线通信系统、雷达等电子信息系统。随着新一代无线移动通信时代的到来，通信系统中数字中频接收机对模数转换器的性能提出了更高的要求，而兼顾了速度和精度的流水线（Pipelined）模数转换器是适应这种需求的较好选择。论文针对无线通信领域对ADC转换精度、速度以及动态性能的要求，研究并优化流水线模数转换器的系统结构和关键单元模块，设计了一种16位100MHz采样率的CMOS流水线模数转换器。
基于流水线模数转换器系统噪声限制、主要功耗单元分析，利用参数建模并结合级间递减（Scaling down）技术，获得了优化的16位流水线模数转换器系统级精度分布，并根据系统噪声的要求确定了各级电路中采样电容的大小。依据上述系统设计方案提出了如下优化设计技术：
提出了一种改进的冗余位流水线校正算法，采用平均分配量化区间和压缩输出范围等技术，不仅保持了传统数字校正算法的功能，而且提高了输出信号的线性度。同时，新算法在编码中引入负向冗余码和正向冗余码，实现溢出判断功能。
基于延迟锁相环原理提出了一种快速锁定的高精度低抖动时钟稳定电路。采用输入时钟单边沿的延迟控制，实现调节输出时钟占空比，降低了电路复杂度和输出时钟抖动。
提出了一种能自动校零、多级前置放大的锁存比较器，解决了流水线子转换器对比较器低输入失调电压、高转换速度的要求。
采用改进的栅压自举开关和增益自举的伪差分共源共栅运算放大器，实现了高速、高精度和高动态范围的采样保持电路。
针对实际工艺中电容失配引入的误差，提出了一种前台模拟校准方法。该方法可以对流水线子DAC中电容失配引起的非线性误差进行校准且具有较高的校准精度。
基于上述设计方法，采用SMIC0.18μm1P6M CMOS数模混合工艺设计了一款16位100MHz流水线模数转换器。仿真结果表明，在3.3V电源供电下，输入量化电压范围为2.5V，电路功耗为750mW，芯片有效面积16mm2。在采样时钟频率为100MHz，输入信号频率为50MHz时，SFDR为98.25dB，SNDR为87.78dB，ENOB为14.25位，已达到同类设计的优秀水平。
The analog-to-digital converters (ADC) have been widely used in wirelesscommunication system, radar and other electronic information systems. Along with thearrival of the new generation of wireless mobile communication, the digital IF receiverof the communication system requires a higher performance of ADC. The PipelinedADC, which gives consideration to both speed and precision, is good choice to adapt tothis requirement.
Pointing at the high requirement for ADC by wireless communication field interms of switching precision, speed and dynamic performance, this research hasdesigned a16-bit100-MS/s sampling rate CMOS pipelined ADC through the studiesand the optimization of Pipelined ADC system construction and key modules.
Based on the analysis and parameter modeling of system noise limitation and mainpower blocks, this research acquired the systematic precision distribution of optimized16-bit pipelined ADC. Meanwhile, in accordance to the requirement of system noise,this research also determines the size of the sampling capacitor for each stage.According to the above system structure, some optimization design methods areproposed as follow:
An improved digital redundancy has been proposed, which uses the technologiesof averaging sub-quantization and scaling down the output of stages, in order to bothkeep the function of traditional digital correction algorithm and also to improve thelinearity in conversion. In addition, the new algorithm also introduces negative andpositive redundant bit so as to determine overflow.
A new fast-locking, low-jitter and high-precision CMOS pulsewidth control looprealized by delay locked loop is designed. By using the single edge of clock, theproposed circuit achieves the modulation of duty cycle, and also substantially reducesthe complex of the circuit and the clock jitter.
Amulti-stage pre-amp comparator with offset-cancellation is proposed, which meetsthe requirement of low input offset voltage and high conversion rate.
A sample-and-hold circuit of high speed, high resolution and high spurious freedynamic range is designed by using an improved bootstrap sample switch and again-boosted pseudo differential operational amplifier.
An analog calibration is proposed. In this calibration, a post-production capacitormismatch extraction method is designed. Then the non-linearity error caused by capacitor mismatch in multi-bit sub-DAC would be calibrated with a high correctingprecision.
Based on above designs, a16-bit100-MS/s pipelined ADC is realized in SMIC0.18μm1P6M CMOS process. The active area of the ADC is16mm2. Simulationresults show that under3.3V supply voltage, the power dissipation is750mW. At100MS/s, the ADC achieves98.25dB of SFDR,87.78dB of SNDR and14.25bits of ENOBfor an input signal of50MHz. The proposed converter is the advanced level in thisdirection.
基于流水线模数转换器系统噪声限制、主要功耗单元分析，利用参数建模并结合级间递减（Scaling down）技术，获得了优化的16位流水线模数转换器系统级精度分布，并根据系统噪声的要求确定了各级电路中采样电容的大小。依据上述系统设计方案提出了如下优化设计技术：
提出了一种改进的冗余位流水线校正算法，采用平均分配量化区间和压缩输出范围等技术，不仅保持了传统数字校正算法的功能，而且提高了输出信号的线性度。同时，新算法在编码中引入负向冗余码和正向冗余码，实现溢出判断功能。
基于延迟锁相环原理提出了一种快速锁定的高精度低抖动时钟稳定电路。采用输入时钟单边沿的延迟控制，实现调节输出时钟占空比，降低了电路复杂度和输出时钟抖动。
提出了一种能自动校零、多级前置放大的锁存比较器，解决了流水线子转换器对比较器低输入失调电压、高转换速度的要求。
采用改进的栅压自举开关和增益自举的伪差分共源共栅运算放大器，实现了高速、高精度和高动态范围的采样保持电路。
针对实际工艺中电容失配引入的误差，提出了一种前台模拟校准方法。该方法可以对流水线子DAC中电容失配引起的非线性误差进行校准且具有较高的校准精度。
基于上述设计方法，采用SMIC0.18μm1P6M CMOS数模混合工艺设计了一款16位100MHz流水线模数转换器。仿真结果表明，在3.3V电源供电下，输入量化电压范围为2.5V，电路功耗为750mW，芯片有效面积16mm2。在采样时钟频率为100MHz，输入信号频率为50MHz时，SFDR为98.25dB，SNDR为87.78dB，ENOB为14.25位，已达到同类设计的优秀水平。
The analog-to-digital converters (ADC) have been widely used in wirelesscommunication system, radar and other electronic information systems. Along with thearrival of the new generation of wireless mobile communication, the digital IF receiverof the communication system requires a higher performance of ADC. The PipelinedADC, which gives consideration to both speed and precision, is good choice to adapt tothis requirement.
Pointing at the high requirement for ADC by wireless communication field interms of switching precision, speed and dynamic performance, this research hasdesigned a16-bit100-MS/s sampling rate CMOS pipelined ADC through the studiesand the optimization of Pipelined ADC system construction and key modules.
Based on the analysis and parameter modeling of system noise limitation and mainpower blocks, this research acquired the systematic precision distribution of optimized16-bit pipelined ADC. Meanwhile, in accordance to the requirement of system noise,this research also determines the size of the sampling capacitor for each stage.According to the above system structure, some optimization design methods areproposed as follow:
An improved digital redundancy has been proposed, which uses the technologiesof averaging sub-quantization and scaling down the output of stages, in order to bothkeep the function of traditional digital correction algorithm and also to improve thelinearity in conversion. In addition, the new algorithm also introduces negative andpositive redundant bit so as to determine overflow.
A new fast-locking, low-jitter and high-precision CMOS pulsewidth control looprealized by delay locked loop is designed. By using the single edge of clock, theproposed circuit achieves the modulation of duty cycle, and also substantially reducesthe complex of the circuit and the clock jitter.
Amulti-stage pre-amp comparator with offset-cancellation is proposed, which meetsthe requirement of low input offset voltage and high conversion rate.
A sample-and-hold circuit of high speed, high resolution and high spurious freedynamic range is designed by using an improved bootstrap sample switch and again-boosted pseudo differential operational amplifier.
An analog calibration is proposed. In this calibration, a post-production capacitormismatch extraction method is designed. Then the non-linearity error caused by capacitor mismatch in multi-bit sub-DAC would be calibrated with a high correctingprecision.
Based on above designs, a16-bit100-MS/s pipelined ADC is realized in SMIC0.18μm1P6M CMOS process. The active area of the ADC is16mm2. Simulationresults show that under3.3V supply voltage, the power dissipation is750mW. At100MS/s, the ADC achieves98.25dB of SFDR,87.78dB of SNDR and14.25bits of ENOBfor an input signal of50MHz. The proposed converter is the advanced level in thisdirection.
引文
[1] Razavi B. Design of Analog CMOS Integrated Circuits. International Edition2005.McGraw-Hill Higher Eucation.2005.1-3.
[2] Gregorian R, Temes G C. Analog MOS Integrted Circuits for Signal Processing.New York: Jotn Wiley and Sons,1986.2-3.
[3]陈贵灿,邵志标,程军,等. CMOS集成电路设计.西安:西安交通大学出版社,1999.1-5.
[4] Cho T. Low-power, Low-Voltage Analog to Digital Conversion Techniques usingPipelined Architecture. PhD Thesis, University of Califomia, Berkeley.1995.2-5.
[5]杨银堂,朱樟明,朱臻.高速CMOS数据转换器.北京:科学出版社,2006.3-7.
[6] Shaker M O, Gosh S, Bayoumi M A. A1-GS/s6-bit flash ADC in90nm CMOS.IEEE MWSCAS2009.2009.144-147.
[7] Pernillo J, Flynn M P. A1.5-GS/s Flash ADC With57.7-dB SFDR and6.4-BitENOB in90nm Digital CMOS. IEEE Circuits and System II: Express Briefs.2011,58(12).837-841.
[8] Pieter J A, Cui Z, Yu B et al. A26μW8bit10MS/s Asynchronous SAR ADC forLow Energy Radios. IEEE Journal of Solid-State Circuits.2011,46(7).1585-1595.
[9] Huang G Y, Chang S J, Liu C C. A1-μW10-bit200-kS/s SAR ADC with a BypassWindow for Biomedical Applications. IEEE Journal of Solid-State Circuits.2012,47(11).2783-2795.
[10]Lee C C, Flynn M P. A14b23MS/s48Mw Resetting Σ-Δ ADC. IEEE Circuits andSystem I: Regular Papers.2011,58(6).1167-1177.
[11]Wu J Y, Zhang Z Y, Subramoniam R, et al. A107.4dB SNR Multi-Bit Sigma DeltaADC With1PPM THD at0.12dB From Full Scale Input. IEEE Journal ofSolid-State Circuits.2011,44(11).3060-3066.
[12]Yoo S M, Park J B, Lee S H. A2.5-V10-b120-MSample/s CMOS Pipelined ADCbased on merged-capacitor switching. IEEE Circuits and System II: Express Briefs.2004,51(5).269-275.
[13]Grace C R, Hurst P J, Lewis S H. A12-bit80-MSample/s pipelined ADC withbootstrapped digital calibration. IEEE Journal of Solid-State Circuits.2005,40(5).1038-1046.
[14]Kush G, Mark S P, Anurag P, et al. A Highly Integrated CMOS Analog BasebandTransceiver with180MSPS13-bit Pipelined CMOS ADC and Dual12-bit DACs.IEEE Journal of Solid-State Circuits.2006,41(8).1856-1866.
[15]Li J, Leboeuf R, Courcy M, Manganaro G. A1.8V10b210MS/s CMOS PipelinedADC Featuring86dB SFDR without Calibration. IEEE CICC2007.2007.317-320.
[16]Ryu S T, Song B S, Bacrania K. A10-bit50-MS/s Pipelined ADC With OpampCurrent Reuse. IEEE Journal of Solid-State Circuits.2007,42(3).475-485.
[17]Jiang S, Do AV, Yeo K S, Lim W M. An8-bit200-MSample/s Pipelined ADC WithMixed Mode Front-End S/H Circuit. IEEE Circuits and System I: Regular Papers.2008,55(6).1430-1440.
[18]Lee B G, Tsang R M. A10-bit50MS/s Pipelined ADC With Capacitor-Sharing andVariable-gm Opamp. IEEE Journal of Solid-State Circuits.2009,44(3).883-890.
[19]Davide V, Jan M, Frank M L, et al. An800MS/s Dual-Residue Pipeline ADC in40nm CMOS. IEEE Journal of Solid-State Circuits.2011,46(12).2834-2844.
[20]Jie Y, Fung S W, Chan K Y, Xu R. A12-bit20MS/s56.3mW Pipelined ADC WithInterpolation-Based Nonlinear Calibration. IEEE Circuits and System I: RegularPapers.2008,59(3).555-565.
[21]Kim S W, Cho Y J, Lee K H, et al. An8b240MS/s1.36mm2104mW0.18μmCMOS ADC for DVDs with dual-mode inputs. IEEE ISCAS2005.2005.4054-4057.
[22]Lee S C, Jeon Y D, Kwon J K, et al. A10-bit205-MS/s1.0-mm290-nm CMOSPipelined ADC for Flat Panel Display Applicatons. IEEE Journal of Solid-StateCircuits.2007,42(12).2688-2695.
[23]Arias J, Boccuzzi V, Quintanilla L, et al. Low-power pipeline ADC for wirelessLANs. IEEE Journal of Solid-State Circuits.2004,39(8).1338-1340.
[24]Jalali B, Meruva A. A comprehensive calibration scheme for a14-b50MSPSpipeline ADC for multi-mode wireless receivers. IEEE MWSCAS2007.2007.140-143.
[25]Huang C C, Wang C Y, Wu J T. A CMOS6-Bit16-GS/s Time-Interleaved ADCUsing Digital Background Calibration Techniques. IEEE Journal of Solid-StateCircuits.2010,46(4).848-858.
[26]Manar E C, Boris M. A12-GS/s81-mW5-bit Time-Interleaved Flash ADC WithBackground Time Skew Calibration. IEEE Journal of Solid-State Circuits.2011,46(4).838-847.
[27]Ahmed M A, Andrew M, Christopher D, et al. A16-bit250-MS/s IF SamplingPipelined ADC With Background Calibration. IEEE Journal of Solid-State Circuits.2010,45(12).2602-2612.
[28]Robert Payne, Marco Corsi，A16-Bit100to160MS/s SiGe BiCMOS PipelinedADC With100dBFS SFDR, IEEE Journal of Solid-State Circuits.2010,45(12).2613-2622.
[29]Cai X B, Li F L, Zhang C, Wang Z H. A12bit100MS/s pipelined analog to digitalconverter without calibration. Journal of Semiconductors.2010,31(11).115007-5.
[30]董在望,李冬梅,王志华,等.高等模拟集成电路.北京:清华大学出版社,2006.113-116.
[31]Van R J, Plassche D. Integrated Analog to Digital and Digital to Analog Converters.Kluwer Academic Publishers.1994.20-55.
[32]Guo X W, Cheng C, Ren J Y. An8-bit125MHz Folding and Interpolating Analogto Digital Converter. IEEE ASICP2001.2001.293-295.
[33]Lin J F, Chang S J, Liu C C, et al. A10bit60MS/s Low power Pipelined ADC withSplit-capacitor CDS Technique. IEEE Trans. Circuits and Systems II.2010,57(3).163-167.
[34]Imran A. Pipelined ADC Design and Enhancement Techniques. New York:Springer,2010.3-20.
[35]McCall K J, Demler M J, Plante M W. A6-bit125MHz CMOS A/D Converter.IEEE Custom Integrated Circuit Conference.1992,1681-1684.
[36]Erdopgan O E, Hurst P J, Lewis S H. A12-b Digital background calibratedalgorithmic ADC with90-dB THD. IEEE Journal of Solid-State Circuits.1999,34(12).1812-1820.
[37]Dalton D, Spalding G, Reyhani H, et al. A200MSPS6bit Flash ADC in0.6μmCMOS. IEEE Trans. Circuits and Systems II.1998,45(11).1433-1444.
[38]Cline D, Gray P R. A power optimized13-b5-Msample/s pipelined analog todigital converter in1.2μm CMOS. IEEE Journal of Solid-State Circuits.1996,31(3).294-303.
[39]Chang H C. A Power Optimized Pipelined Analog-to-Digital Converter Design inDeep Sub-Micron CMOS Technology. PhD Thesis, Georgia Institute ofTechnology, Altanta.2005.73-119.
[40]Han S R, Liu S I. A Single-Path Pulsewidth Control Loop with a Built-InDelay-Locked Loop. IEEE Journal of Solid-State Circuits.2005,40(5).1130-1135.
[41]Cheng K H, Su C W. AHigh Linearity, Fast-Locking Pulsewidth Control Loop withDigitally Programmable Duty Cycle Correction for Wide Range Operation. IEEEJournal of Solid-State Circuits.2008,43(2).399-413.
[42]Chen Y G, Tsao H W, Hwang C S. A Fast-Locking All-Digital Deskew Buffer WithDuty-Cycle Correction, IEEE. Trans. Very Large Scale Integrated Circuits (VLSI)System.2012,21(2).270-280.
[43]Huang H Y, Chiu W M. Wide-Range High-Precision Pulse width Control Loop.IEEE Journal of Solid-Sate Circuit.2009,40(5).719-725.
[44]Shin D, Kim C, Song J, Chae H. A7ps jitter0.053mm fast lock all-digital DLL witha wide range and high resolution DCC. IEEE Journal of Solid-Sate Circuit.2009,44(9).2437–2451.
[45]Derek R, Eric T, Alison S. Understanding the Effect of Clock Jitter on High SpeedADCs. Design Note1013, Linear Technology Corporation.2007.
[46]Shu K. CMOS PLL SYNTHESIZERS:Analysis and Design. Springer.2005.185-189.
[47]George W, Eric A V, Fouad R. Charge Injection in Analog MOS Switches. IEEEJournal of Solid-Sate Circuit.1987,22(6).1091–1097.
[48]Christoph E, Walter G. On Charge Injection in Analog MOS Switches and DummySwitch Compensation Techniques. IEEE Trans. Circuits and Systems II.1990,37(20).257-264.
[49]Chen M J, Gu Y B, Wu T, et al. Weak Inversion Charge Injection in Analog MOSSwitches. IEEE Journal of Solid-Sate Circuit.1995,30(5).604–606.
[50]Patrick J. Accuracy Limitations of Pipelined ADCs. IEEE Journal of Solid-SateCircuit.2005,3(1).1956–1959.
[51]Zhian T E, Kamarei M, Ashtiani S J.1.5-bit mismatch-insensitive MDAC withreduced input capacitive loading. Electronics Letters.2009,45(23).1157–1158.
[52]Siragusa E J, Galton I. Gain error correction technique for pipelined analog todigital converters. Electronics Letters.2000,36(7).617–618.
[53]Scott B, Christopher D, Ravi K, et al. A100-dB SFDR80-MSPS14-Bit0.35-μmBiCMOS Pipeline ADC. IEEE Journal of Solid-Sate Circuit.2006,41(9).2144–2153.
[54]Chang D Y. Design Techniques for a Pipelined ADC Without Using a Front-EndSample-and-Hold Amplifier. IEEE Trans. Circuits and Systems I.2004,51(11).2123-2132.
[55]Wen X K, Wang R, Peng R G, et al. A12b60MS/s SHA-less opamp-sharingpipelined A/D with switch-embedded dual input OTAs. IEEE ISCAS2012.2012.802-805.
[56]Zhao X X, Li F L, Wu B. ASHA-less12-bit200-MS/s pipelined ADC. IEEE ASID2011.2011.161-164.
[57]Shu C, Shu G H, Xu J, et al. A12-bit50-MSPS SHA-less opamp-sharingAnalog-to-Digital converter in65nm CMOS. IEEE ASICON2011.2011.894-897.
[58]Ahmed M A, Christopher D, Robert S, et al. A14-bit125MS/s IF/RF SamplingPipelined ADC With100dB SFDR and50fs Jitter. IEEE Journal of Solid-SateCircuit.2006,41(8).1846–1855.
[59]Zhao L, Yang Y T, Zhu Z M, Liu L X. SHA-Less architecture with enhancedaccuracy for pipelined ADC. Journal of Semiconductors.2012,33(2).025010-5.
[60]Huang P L, Hsien S K, Lu V, et al. SHA-Less Pipelined ADC With In SituBackground Clock-Skew Calibration. IEEE Journal of Solid-Sate Circuit.2011,46(8).1–11.
[61]Xu J L, Chen C X, Cai S C, et al. Digital background skew calibration fortime-interleaved shared-front-end SHA-less pipelined ADCs. IEEE ICSICT2012.2012.1-3.
[62]Yang W. A3-V340-mW14-b75-Msample/s CMOS ADC with85-dB SFDR atNyquist Input. IEEE Journal of Solid-Sate Circuit.2001,36(12).1931–1936.
[63]Ginetti B, Jespers P G A. A1.5MS/s8-Bit Pipelined RSD A/D Converter.ESSCIRC1990.1990.137-140.
[64]Jang Y C, Bae S J, Park H J. A Digital CMOS PWCL with Fixed-Delay RisingEdge and Digital Stability Control. IEEE Trans. Circuits and Systems II.2006,53(10).1063-1067.
[65]Lin T H, Chi C C, Chiu W H. A Synchronous50%Duty-Cycle Clock Generator in0.35-μm CMOS. IEEE Trans. Very Large Scale Integrated Circuits System.2011,19(4).585–591.
[66]Chung C C, Sheng D, Shen S E. A wide-range all-digital duty-cycle corrector withoutput clock phase alignment in65nm CMOS technology. IEICE ElectronicsExpress.2011,8(15).1245-1251.
[67]Zhao L, Yang Y T, Zhu Z M and Liu L X. A Clock Generator for High-SpeedHigh-Resolution Pipelined A/D Converter. Journal of Semiconductors.2013,34(2).025003-6.
[68]Mike P L. Jitter, Noise, and Signal Integrity at High-Speed. Bostan: PearsonEucation.2008.4-5.
[69]Chandrakasan A, Bowhill W J, Fox F. Design of High-Performance MicroprocessorCircuit. New York: IEEE Press,2001.240-245.
[70]He J, Zhan S Y, Chen D G, Geiger R L. Analyses of Static and Dynamic RandomOffset Voltage in Dynamic Comparators. IEEE Trans. Circuits and Systems I.2009,56(5).911-919.
[71]Achim G. A methodology for the offset-simulation of comparators. The Designer’sGuide Community.2006.
[72]Daliri M, Maymandi M, Mafinezhad K. Distortion analysis of bootstrap switchusing volterra series. IET Circuits Devices and Systems.2009,3(6).359-364.
[73]Fayomi C J B, Roberts G W, Sawan M. Low-voltage CMOS analog bootstrappedswitch for sample-and-hold circuit: design and chip characterization, IEEE ISCAS2005.2005.2200-2203.
[74]Wang L, Yin W J, Xu J, et al. Dual-Channel Bootstrapped Switch for High-SpeedHigh-Resolution Sampling. Electronics Letters,2006,42(22).1275-1276.
[75]Yang C Y, Hung C C. A low-voltage low-distortion MOS sampling switch. IEEEISCAS2005.2005.3131-3134.
[76]Yao L, Michiel S, Willy S. Fast-settling CMOS Two-stage OperationalTransconductance Amplifiers and their Systematic Design. IEEE ISCAS2002.2002.839-842.
[77]Hati M K, Bhattacharyya T K. Design of a low Power High Speed ComplementaryInput Folded Regulated Cascode OTA for a Parallel Pipeline ADC. IEEE ISVLSI2011.2011.114-119.
[78]Gulati K, Lee H S. A high-swing CMOS telescopic operational amplifier. IEEEJournal of Solid-Sate Circuit.1998,33(12).2010–2019.
[79]Grasso A D, Pennisi S. High-performance CMOS pseudo-differential amplifier.IEEE ISCAS2005.2005.1569-1572.
[80]Kulshreshtha T, Bhadaura V. A highly linear CMOS pseudo differentialtransconductor using active attenuator. IEEE ICPCES2010.2010.1-4.
[81]Mohieldin AN, Sinencio E S, Martinez S. Afully balanced pseudo-differential OTAwith common-mode feedforward and inherent common-mode feedback detector.IEEE Journal of Solid-Sate Circuit.2003,38(4).663–668.
[82]Lujan M C, Torralba A, Carvajal R G, et al. A-72db@2MHz IM3CMOS tunablepseudo-differential transconductor. IEEE ISCAS2008.2008.73-76.
[83]Shen M H, Lan P H, Huang P C. A1-V CMOS Pseudo-Differential Amplifier WithMultiple Common-Mode Stabilization and Frequency Compensation Loops. IEEETrans. Circuits and Systems II.2008,55(5).409-413.
[84]Broyde F, Clavelier E. A pseudo-differential transmitting circuit causing reducedcommon-mode current variations. IEEE ICECS2008.2008.17-20.
[85]Mohieldin A N, Sanchez S E, Silva M J. Nonlinear effects in pseudo differentialOTAs with CMFB. IEEE Trans. Circuits and Systems II.2003,50(10).762-770.
[86]Chang Y S, Wu H C, Shiau M S, et al. Pseudo differential operationaltransconductance amplifier using common mode feed forward and HD3feedforward. IEEE ISIC2011.2011.250-253.
[87]Bult K, Geelen G J. A fast-settling CMOS op amp for SC circuits with90-dB DCgain. IEEE Journal of Solid-Sate Circuit.1990,25(6).1379–1384.
[88]Das M. Improved Design Criteria of Gain-Boosted CMOS OTA with High-SpeedOptimizations. IEEE Trans. Circuits and Systems II.2002,49(3).204-207.
[89]Choksi O, Richard L. Analysis of Switched-Capacitor Common-Mode FeedbackCircuit. IEEE Trans. Circuits and Systems II.2003,50(12).906-917.
[90]Yun C. Inherently linear capacitor error-averaging techniques for pipelined A/Dconversion. IEEE Trans. Circuits and Systems II.2000,47(3).229-232.
[91]Chuang S Y, Sculley T L. A digitally self-calibrating14-bit10-MHz CMOSpipelined A/D converter. IEEE Journal of Solid-Sate Circuit.2002,37(6).674–683.
[92]Ray S, Song B S. A13-b Linear40-MS/s Pipelined ADC With Self-configuredCapacitor Matching. IEEE Journal of Solid-Sate Circuit.2007,42(3).463–474.
[93]Alan Hastings. TheArt ofAnalog Layout. New Jersey: Prentice Hall.2001.1-10.
[94]Christopher S, Judy S. IC Mask Design: Essential Layout Techniques.English:McGraw Hill.2002.141-160.
[95]Maxim. Dynamic Testing of High-Speed ADC. Application Note729of Maxim.Jan2001.1-15.
[96]Lee B G, Min B M, Manganaro G, et al. A14-b100-MS/s Pipelined ADC With aMerged SHA and First MDAC. IEEE Journal of Solid-Sate Circuit.2008,43(12).2613–2619.
[97]Luo L, Lin K H, Cheng L, et al. A digitally calibrated14-bit linear100-MS/spipelined ADC with wideband sampling frontend. IEEE ESSCIRC2009.2009.472-475.
[98]Siddharth D, Larry S, Dan K, et al. A16-bit125MS/s385mW78.7dB SNR CMOSPipeline ADC. IEEE Journal of Solid-Sate Circuit.2009,44(12).3305–3313.
[2] Gregorian R, Temes G C. Analog MOS Integrted Circuits for Signal Processing.New York: Jotn Wiley and Sons,1986.2-3.
[3]陈贵灿,邵志标,程军,等. CMOS集成电路设计.西安:西安交通大学出版社,1999.1-5.
[4] Cho T. Low-power, Low-Voltage Analog to Digital Conversion Techniques usingPipelined Architecture. PhD Thesis, University of Califomia, Berkeley.1995.2-5.
[5]杨银堂,朱樟明,朱臻.高速CMOS数据转换器.北京:科学出版社,2006.3-7.
[6] Shaker M O, Gosh S, Bayoumi M A. A1-GS/s6-bit flash ADC in90nm CMOS.IEEE MWSCAS2009.2009.144-147.
[7] Pernillo J, Flynn M P. A1.5-GS/s Flash ADC With57.7-dB SFDR and6.4-BitENOB in90nm Digital CMOS. IEEE Circuits and System II: Express Briefs.2011,58(12).837-841.
[8] Pieter J A, Cui Z, Yu B et al. A26μW8bit10MS/s Asynchronous SAR ADC forLow Energy Radios. IEEE Journal of Solid-State Circuits.2011,46(7).1585-1595.
[9] Huang G Y, Chang S J, Liu C C. A1-μW10-bit200-kS/s SAR ADC with a BypassWindow for Biomedical Applications. IEEE Journal of Solid-State Circuits.2012,47(11).2783-2795.
[10]Lee C C, Flynn M P. A14b23MS/s48Mw Resetting Σ-Δ ADC. IEEE Circuits andSystem I: Regular Papers.2011,58(6).1167-1177.
[11]Wu J Y, Zhang Z Y, Subramoniam R, et al. A107.4dB SNR Multi-Bit Sigma DeltaADC With1PPM THD at0.12dB From Full Scale Input. IEEE Journal ofSolid-State Circuits.2011,44(11).3060-3066.
[12]Yoo S M, Park J B, Lee S H. A2.5-V10-b120-MSample/s CMOS Pipelined ADCbased on merged-capacitor switching. IEEE Circuits and System II: Express Briefs.2004,51(5).269-275.
[13]Grace C R, Hurst P J, Lewis S H. A12-bit80-MSample/s pipelined ADC withbootstrapped digital calibration. IEEE Journal of Solid-State Circuits.2005,40(5).1038-1046.
[14]Kush G, Mark S P, Anurag P, et al. A Highly Integrated CMOS Analog BasebandTransceiver with180MSPS13-bit Pipelined CMOS ADC and Dual12-bit DACs.IEEE Journal of Solid-State Circuits.2006,41(8).1856-1866.
[15]Li J, Leboeuf R, Courcy M, Manganaro G. A1.8V10b210MS/s CMOS PipelinedADC Featuring86dB SFDR without Calibration. IEEE CICC2007.2007.317-320.
[16]Ryu S T, Song B S, Bacrania K. A10-bit50-MS/s Pipelined ADC With OpampCurrent Reuse. IEEE Journal of Solid-State Circuits.2007,42(3).475-485.
[17]Jiang S, Do AV, Yeo K S, Lim W M. An8-bit200-MSample/s Pipelined ADC WithMixed Mode Front-End S/H Circuit. IEEE Circuits and System I: Regular Papers.2008,55(6).1430-1440.
[18]Lee B G, Tsang R M. A10-bit50MS/s Pipelined ADC With Capacitor-Sharing andVariable-gm Opamp. IEEE Journal of Solid-State Circuits.2009,44(3).883-890.
[19]Davide V, Jan M, Frank M L, et al. An800MS/s Dual-Residue Pipeline ADC in40nm CMOS. IEEE Journal of Solid-State Circuits.2011,46(12).2834-2844.
[20]Jie Y, Fung S W, Chan K Y, Xu R. A12-bit20MS/s56.3mW Pipelined ADC WithInterpolation-Based Nonlinear Calibration. IEEE Circuits and System I: RegularPapers.2008,59(3).555-565.
[21]Kim S W, Cho Y J, Lee K H, et al. An8b240MS/s1.36mm2104mW0.18μmCMOS ADC for DVDs with dual-mode inputs. IEEE ISCAS2005.2005.4054-4057.
[22]Lee S C, Jeon Y D, Kwon J K, et al. A10-bit205-MS/s1.0-mm290-nm CMOSPipelined ADC for Flat Panel Display Applicatons. IEEE Journal of Solid-StateCircuits.2007,42(12).2688-2695.
[23]Arias J, Boccuzzi V, Quintanilla L, et al. Low-power pipeline ADC for wirelessLANs. IEEE Journal of Solid-State Circuits.2004,39(8).1338-1340.
[24]Jalali B, Meruva A. A comprehensive calibration scheme for a14-b50MSPSpipeline ADC for multi-mode wireless receivers. IEEE MWSCAS2007.2007.140-143.
[25]Huang C C, Wang C Y, Wu J T. A CMOS6-Bit16-GS/s Time-Interleaved ADCUsing Digital Background Calibration Techniques. IEEE Journal of Solid-StateCircuits.2010,46(4).848-858.
[26]Manar E C, Boris M. A12-GS/s81-mW5-bit Time-Interleaved Flash ADC WithBackground Time Skew Calibration. IEEE Journal of Solid-State Circuits.2011,46(4).838-847.
[27]Ahmed M A, Andrew M, Christopher D, et al. A16-bit250-MS/s IF SamplingPipelined ADC With Background Calibration. IEEE Journal of Solid-State Circuits.2010,45(12).2602-2612.
[28]Robert Payne, Marco Corsi，A16-Bit100to160MS/s SiGe BiCMOS PipelinedADC With100dBFS SFDR, IEEE Journal of Solid-State Circuits.2010,45(12).2613-2622.
[29]Cai X B, Li F L, Zhang C, Wang Z H. A12bit100MS/s pipelined analog to digitalconverter without calibration. Journal of Semiconductors.2010,31(11).115007-5.
[30]董在望,李冬梅,王志华,等.高等模拟集成电路.北京:清华大学出版社,2006.113-116.
[31]Van R J, Plassche D. Integrated Analog to Digital and Digital to Analog Converters.Kluwer Academic Publishers.1994.20-55.
[32]Guo X W, Cheng C, Ren J Y. An8-bit125MHz Folding and Interpolating Analogto Digital Converter. IEEE ASICP2001.2001.293-295.
[33]Lin J F, Chang S J, Liu C C, et al. A10bit60MS/s Low power Pipelined ADC withSplit-capacitor CDS Technique. IEEE Trans. Circuits and Systems II.2010,57(3).163-167.
[34]Imran A. Pipelined ADC Design and Enhancement Techniques. New York:Springer,2010.3-20.
[35]McCall K J, Demler M J, Plante M W. A6-bit125MHz CMOS A/D Converter.IEEE Custom Integrated Circuit Conference.1992,1681-1684.
[36]Erdopgan O E, Hurst P J, Lewis S H. A12-b Digital background calibratedalgorithmic ADC with90-dB THD. IEEE Journal of Solid-State Circuits.1999,34(12).1812-1820.
[37]Dalton D, Spalding G, Reyhani H, et al. A200MSPS6bit Flash ADC in0.6μmCMOS. IEEE Trans. Circuits and Systems II.1998,45(11).1433-1444.
[38]Cline D, Gray P R. A power optimized13-b5-Msample/s pipelined analog todigital converter in1.2μm CMOS. IEEE Journal of Solid-State Circuits.1996,31(3).294-303.
[39]Chang H C. A Power Optimized Pipelined Analog-to-Digital Converter Design inDeep Sub-Micron CMOS Technology. PhD Thesis, Georgia Institute ofTechnology, Altanta.2005.73-119.
[40]Han S R, Liu S I. A Single-Path Pulsewidth Control Loop with a Built-InDelay-Locked Loop. IEEE Journal of Solid-State Circuits.2005,40(5).1130-1135.
[41]Cheng K H, Su C W. AHigh Linearity, Fast-Locking Pulsewidth Control Loop withDigitally Programmable Duty Cycle Correction for Wide Range Operation. IEEEJournal of Solid-State Circuits.2008,43(2).399-413.
[42]Chen Y G, Tsao H W, Hwang C S. A Fast-Locking All-Digital Deskew Buffer WithDuty-Cycle Correction, IEEE. Trans. Very Large Scale Integrated Circuits (VLSI)System.2012,21(2).270-280.
[43]Huang H Y, Chiu W M. Wide-Range High-Precision Pulse width Control Loop.IEEE Journal of Solid-Sate Circuit.2009,40(5).719-725.
[44]Shin D, Kim C, Song J, Chae H. A7ps jitter0.053mm fast lock all-digital DLL witha wide range and high resolution DCC. IEEE Journal of Solid-Sate Circuit.2009,44(9).2437–2451.
[45]Derek R, Eric T, Alison S. Understanding the Effect of Clock Jitter on High SpeedADCs. Design Note1013, Linear Technology Corporation.2007.
[46]Shu K. CMOS PLL SYNTHESIZERS:Analysis and Design. Springer.2005.185-189.
[47]George W, Eric A V, Fouad R. Charge Injection in Analog MOS Switches. IEEEJournal of Solid-Sate Circuit.1987,22(6).1091–1097.
[48]Christoph E, Walter G. On Charge Injection in Analog MOS Switches and DummySwitch Compensation Techniques. IEEE Trans. Circuits and Systems II.1990,37(20).257-264.
[49]Chen M J, Gu Y B, Wu T, et al. Weak Inversion Charge Injection in Analog MOSSwitches. IEEE Journal of Solid-Sate Circuit.1995,30(5).604–606.
[50]Patrick J. Accuracy Limitations of Pipelined ADCs. IEEE Journal of Solid-SateCircuit.2005,3(1).1956–1959.
[51]Zhian T E, Kamarei M, Ashtiani S J.1.5-bit mismatch-insensitive MDAC withreduced input capacitive loading. Electronics Letters.2009,45(23).1157–1158.
[52]Siragusa E J, Galton I. Gain error correction technique for pipelined analog todigital converters. Electronics Letters.2000,36(7).617–618.
[53]Scott B, Christopher D, Ravi K, et al. A100-dB SFDR80-MSPS14-Bit0.35-μmBiCMOS Pipeline ADC. IEEE Journal of Solid-Sate Circuit.2006,41(9).2144–2153.
[54]Chang D Y. Design Techniques for a Pipelined ADC Without Using a Front-EndSample-and-Hold Amplifier. IEEE Trans. Circuits and Systems I.2004,51(11).2123-2132.
[55]Wen X K, Wang R, Peng R G, et al. A12b60MS/s SHA-less opamp-sharingpipelined A/D with switch-embedded dual input OTAs. IEEE ISCAS2012.2012.802-805.
[56]Zhao X X, Li F L, Wu B. ASHA-less12-bit200-MS/s pipelined ADC. IEEE ASID2011.2011.161-164.
[57]Shu C, Shu G H, Xu J, et al. A12-bit50-MSPS SHA-less opamp-sharingAnalog-to-Digital converter in65nm CMOS. IEEE ASICON2011.2011.894-897.
[58]Ahmed M A, Christopher D, Robert S, et al. A14-bit125MS/s IF/RF SamplingPipelined ADC With100dB SFDR and50fs Jitter. IEEE Journal of Solid-SateCircuit.2006,41(8).1846–1855.
[59]Zhao L, Yang Y T, Zhu Z M, Liu L X. SHA-Less architecture with enhancedaccuracy for pipelined ADC. Journal of Semiconductors.2012,33(2).025010-5.
[60]Huang P L, Hsien S K, Lu V, et al. SHA-Less Pipelined ADC With In SituBackground Clock-Skew Calibration. IEEE Journal of Solid-Sate Circuit.2011,46(8).1–11.
[61]Xu J L, Chen C X, Cai S C, et al. Digital background skew calibration fortime-interleaved shared-front-end SHA-less pipelined ADCs. IEEE ICSICT2012.2012.1-3.
[62]Yang W. A3-V340-mW14-b75-Msample/s CMOS ADC with85-dB SFDR atNyquist Input. IEEE Journal of Solid-Sate Circuit.2001,36(12).1931–1936.
[63]Ginetti B, Jespers P G A. A1.5MS/s8-Bit Pipelined RSD A/D Converter.ESSCIRC1990.1990.137-140.
[64]Jang Y C, Bae S J, Park H J. A Digital CMOS PWCL with Fixed-Delay RisingEdge and Digital Stability Control. IEEE Trans. Circuits and Systems II.2006,53(10).1063-1067.
[65]Lin T H, Chi C C, Chiu W H. A Synchronous50%Duty-Cycle Clock Generator in0.35-μm CMOS. IEEE Trans. Very Large Scale Integrated Circuits System.2011,19(4).585–591.
[66]Chung C C, Sheng D, Shen S E. A wide-range all-digital duty-cycle corrector withoutput clock phase alignment in65nm CMOS technology. IEICE ElectronicsExpress.2011,8(15).1245-1251.
[67]Zhao L, Yang Y T, Zhu Z M and Liu L X. A Clock Generator for High-SpeedHigh-Resolution Pipelined A/D Converter. Journal of Semiconductors.2013,34(2).025003-6.
[68]Mike P L. Jitter, Noise, and Signal Integrity at High-Speed. Bostan: PearsonEucation.2008.4-5.
[69]Chandrakasan A, Bowhill W J, Fox F. Design of High-Performance MicroprocessorCircuit. New York: IEEE Press,2001.240-245.
[70]He J, Zhan S Y, Chen D G, Geiger R L. Analyses of Static and Dynamic RandomOffset Voltage in Dynamic Comparators. IEEE Trans. Circuits and Systems I.2009,56(5).911-919.
[71]Achim G. A methodology for the offset-simulation of comparators. The Designer’sGuide Community.2006.
[72]Daliri M, Maymandi M, Mafinezhad K. Distortion analysis of bootstrap switchusing volterra series. IET Circuits Devices and Systems.2009,3(6).359-364.
[73]Fayomi C J B, Roberts G W, Sawan M. Low-voltage CMOS analog bootstrappedswitch for sample-and-hold circuit: design and chip characterization, IEEE ISCAS2005.2005.2200-2203.
[74]Wang L, Yin W J, Xu J, et al. Dual-Channel Bootstrapped Switch for High-SpeedHigh-Resolution Sampling. Electronics Letters,2006,42(22).1275-1276.
[75]Yang C Y, Hung C C. A low-voltage low-distortion MOS sampling switch. IEEEISCAS2005.2005.3131-3134.
[76]Yao L, Michiel S, Willy S. Fast-settling CMOS Two-stage OperationalTransconductance Amplifiers and their Systematic Design. IEEE ISCAS2002.2002.839-842.
[77]Hati M K, Bhattacharyya T K. Design of a low Power High Speed ComplementaryInput Folded Regulated Cascode OTA for a Parallel Pipeline ADC. IEEE ISVLSI2011.2011.114-119.
[78]Gulati K, Lee H S. A high-swing CMOS telescopic operational amplifier. IEEEJournal of Solid-Sate Circuit.1998,33(12).2010–2019.
[79]Grasso A D, Pennisi S. High-performance CMOS pseudo-differential amplifier.IEEE ISCAS2005.2005.1569-1572.
[80]Kulshreshtha T, Bhadaura V. A highly linear CMOS pseudo differentialtransconductor using active attenuator. IEEE ICPCES2010.2010.1-4.
[81]Mohieldin AN, Sinencio E S, Martinez S. Afully balanced pseudo-differential OTAwith common-mode feedforward and inherent common-mode feedback detector.IEEE Journal of Solid-Sate Circuit.2003,38(4).663–668.
[82]Lujan M C, Torralba A, Carvajal R G, et al. A-72db@2MHz IM3CMOS tunablepseudo-differential transconductor. IEEE ISCAS2008.2008.73-76.
[83]Shen M H, Lan P H, Huang P C. A1-V CMOS Pseudo-Differential Amplifier WithMultiple Common-Mode Stabilization and Frequency Compensation Loops. IEEETrans. Circuits and Systems II.2008,55(5).409-413.
[84]Broyde F, Clavelier E. A pseudo-differential transmitting circuit causing reducedcommon-mode current variations. IEEE ICECS2008.2008.17-20.
[85]Mohieldin A N, Sanchez S E, Silva M J. Nonlinear effects in pseudo differentialOTAs with CMFB. IEEE Trans. Circuits and Systems II.2003,50(10).762-770.
[86]Chang Y S, Wu H C, Shiau M S, et al. Pseudo differential operationaltransconductance amplifier using common mode feed forward and HD3feedforward. IEEE ISIC2011.2011.250-253.
[87]Bult K, Geelen G J. A fast-settling CMOS op amp for SC circuits with90-dB DCgain. IEEE Journal of Solid-Sate Circuit.1990,25(6).1379–1384.
[88]Das M. Improved Design Criteria of Gain-Boosted CMOS OTA with High-SpeedOptimizations. IEEE Trans. Circuits and Systems II.2002,49(3).204-207.
[89]Choksi O, Richard L. Analysis of Switched-Capacitor Common-Mode FeedbackCircuit. IEEE Trans. Circuits and Systems II.2003,50(12).906-917.
[90]Yun C. Inherently linear capacitor error-averaging techniques for pipelined A/Dconversion. IEEE Trans. Circuits and Systems II.2000,47(3).229-232.
[91]Chuang S Y, Sculley T L. A digitally self-calibrating14-bit10-MHz CMOSpipelined A/D converter. IEEE Journal of Solid-Sate Circuit.2002,37(6).674–683.
[92]Ray S, Song B S. A13-b Linear40-MS/s Pipelined ADC With Self-configuredCapacitor Matching. IEEE Journal of Solid-Sate Circuit.2007,42(3).463–474.
[93]Alan Hastings. TheArt ofAnalog Layout. New Jersey: Prentice Hall.2001.1-10.
[94]Christopher S, Judy S. IC Mask Design: Essential Layout Techniques.English:McGraw Hill.2002.141-160.
[95]Maxim. Dynamic Testing of High-Speed ADC. Application Note729of Maxim.Jan2001.1-15.
[96]Lee B G, Min B M, Manganaro G, et al. A14-b100-MS/s Pipelined ADC With aMerged SHA and First MDAC. IEEE Journal of Solid-Sate Circuit.2008,43(12).2613–2619.
[97]Luo L, Lin K H, Cheng L, et al. A digitally calibrated14-bit linear100-MS/spipelined ADC with wideband sampling frontend. IEEE ESSCIRC2009.2009.472-475.
[98]Siddharth D, Larry S, Dan K, et al. A16-bit125MS/s385mW78.7dB SNR CMOSPipeline ADC. IEEE Journal of Solid-Sate Circuit.2009,44(12).3305–3313.