基于高密度计算的多核芯片设计关键技术研究
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摘要
电子系统结构的高度集成化、功能的一体化给系统设计提出了挑战，体积、重量和功耗的约束使得电子系统小型化设计技术更具有挑战性。CMP（Chip Multiprocessor，单芯片多核处理器）、SiP (System in Package，系统封装)、MEMs（Micro-Electro Mechanical System，微电子机械系统）和NEMs（Nano-Electro Mechanical System，纳电子机械系统），3D（ThreeDimension，三维）集成等技术成为集成电路设计领域重要的研究方向。
人们对于便捷性和低碳性的追求，以前从不计较成本的HPC也开始关注单位空间、单位功耗、甚至单位资金投入所产生的计算速度等指标。使得高密度计算（High Density Computing，HDC）成为继高性能计算（High Performance Computing，HPC）之后又一个重要的研究方向。
从目前发展情况来看，CMP已经成为推动HPC和HDC继续进步的核心技术。本文依据HDC应用需求，研究CMP设计、评估和计算优化问题。主要内容包括：
（1）首先讨论了并行计算、高性能计算、多核计算等相关概念，以多核系统为支撑平台，提出了高密度计算（HDC）问题，给出了HDC的主要特征和所要研究的主要问题，提出了多核系统的评测问题。以数值计算中最具代表性的矩阵类任务作为研究对象，讨论了矩阵运算的一些基本问题，尤其是矩阵的分块运算和复杂度分析，分析了并行矩阵类任务的多核计算方法，为多核系统与矩阵类任务结合的问题研究给出了研究思路。
（2）在分析单芯片多核处理器结构和当前研究状况的基础上，给出了CMP的发展趋势和典型结构，即小核大数量处理器核、阵列和层次型簇结构，阐述了CMP体系结构的主要类型和基本设计原则，对并行计算模型、结构扩展和评估方法进行了理论分析；提出了“三维相邻码”概念和两种“扩展3D Gray码”的编码方法，即坐标扩展法和层扩展法，并分析了三维相邻码的特点和规律；提出了真正意义上的三维簇结构的3D NOC架构，即“三维星形簇（3DStar Cluster,简称3D SC）结构”。3D SC的NOC架构、节点编码和模型描述方法的提出和应用对于3D NOC的定量研究和分析具有重要的理论意义和使用价值。
（3）设计了兼容于MIPS指令集的单核RISC处理器，在此基础上实现了一种基于层次化AHB总线的四核处理器FPGA原型设计。探索了处理器结构的扩展性以及提高处理器整体性能的设计方法，利用多维矩阵相乘验证了系统性能和计算能力。实验结果表明，随着矩阵阶数的增加，多核处理器的加速比随之升高，印证了“处理器数的增加与问题规模的增加要保持平衡”的多核计算理论。
（4）随着核数量的增加，多核系统的任务调度与映射技术的重要性突显出来。本文在分析多核系统的并行调度技术和任务映射技术基础上，给出了层次化任务分解方法，重点讨论了矩阵类任务的等时间复杂度的分块计算，提出了基于嵌入式监控子网的动态任务调度技术。监视子网可以提供数据流信息，用于数据流的智能监控和处理，为提高控制过程可视化和自动化提供了可能。
（5）在3D NoC设计中，随着节点数量的增加，路由设计和低功耗设计是两个关键技术。本文在分析NoC及3D互连集成基本问题的基础上，给出了低功耗研究的基本思路，重点讨论了3D NoC的路由和3D NoC的低功耗模型，给出了3D NOC路由分析和低功耗分析方法。
（6）在多核平台上进行复杂信号处理是一个牵涉面很广的工程问题。本文针对并行计算和多核平台特点，对合成孔径雷达（SAR）信号处理的复杂性问题、任务分解方法、算法流程等问题进行了分析。主要分析了SAR回波信号模型和信号模拟算法，分析了回波模拟数值计算的计算量和存储量，给出了SAR回波模拟的几种并行计算和任务分解方法，以及在簇结构多核平台上进行计算的任务和流程分析。
本文的主要创新点及其意义：
（1）研究领域创新。提出了高密度计算的概念，将高密度计算与多核计算作为一个重要的研究领域。本文以此为切入点，对多核计算、多核系统评测和多核系统设计几个重要问题进行了研究。其意义在于，提升了多核系统设计和高速计算研究的针对性。
（2）理论创新。提出了真正意义的三维(3D)簇的NOC结构，即三维星型簇（3D SC）结构，针对该结构首次提出了三维相邻编码概念和两种扩展三维格雷（3D Gray）编码方法。其意义在于，可以将3D NOC的大数量节点的几何互连关系转换为数组关系，便于几何模型的数值化抽象。
（3）方法创新。提出了基于嵌入监控子网的动态任务调度方法，这个思路可望作为多核计算中智能调度和自动化控制的硬件基础。其意义在于，便于建立动态数据流采集和控制的闭环系统，使得现代控制论技术用于多核数据流分析和控制成为可能。
Electronic system design is being challenged by the high degree of integration and combinationof functionality. The restriction of volume, weight, and energy consumption is making theminimization of electronic system an challenge. CMP (chip multiprocessor), SiP (System inPackage), MEMs (Mirco-Electro Mechanical System), and NEMs (Nano-Electro MechanicalSystem),3D (Three Dimension) integration are becoming important areas of research in integratedcircuit design.
The pursuit of convenience and low-carbon is making high density computing (HDC) anotherimportant research area after high performance computing (HPC). Even HPC, which used to not careabout cost, is becoming more concerned about unit space, unit power consumption, and evencomputing speed per unit investment.
Based on the current development, CMP is becoming the key technology to advance HPC andHDC. This dissertation focuses on CMP design, evaluation, and optimization for the practical needsof HDC. It includes the following:
(1) The concepts of parallel computing, high performance computing and multi-core computing,etc. are discussed. Using the multi-core system as the base platform, HDC is presented, along withthe main features of HDC and the primary research topics, as well as the evaluation of multi-coresystems. Basic problems in matrix operations are discussed, especially matrix decompositionmethods and complexity analysis. The thesis analyzes multi-core computation methods of parallelmatrix operation, and gives thoughts on the combination of multi-core systems and matrixoperations.
(2) Based on the analysis of single chip multi-core processor structure and current research, thethesis presents the trend and typical structure of CMP: small core, big quantity, array andhierarchical clusters. It expounds the main types and basic design principles, and makes a theoreticalanalysis of parallel computation models, structure extension, and evaluation methods. The thesisproposes the concept of3D Neighbor Code and two types of coding methods to expand3D Graycode: coordinate expansion method and layer expansion method. It also analyzes the characteristicsand patterns of3D Neighbor Code, and proposes an3D NOC structure of real3D cluster structure:the3D Star Cluster (3D SC) structure. The NOC structure, node coding, and model descriptionmethod for3D SC are important contributions towards the quantitative research and analysis, forboth theoretical purpose and practical purpose.
(3) This thesis designs a single-core RISC processor compatible with MIPS instruction set, andaccomplishes a4-core processor FPGA prototype design based on hierarchical AHB bus. It explores extensibility of processor structure and design method to increase total processor functionality.Multi-dimension matrix multiplication is used to verify system functionality and computation power.Experiments show that multi-core processor performance increases with the increase of matrixdimensions. This corroborates the theory of “balance must be maintained between the increase ofnumber of processors and the increase of problem scale.”
(4) With the increase in number of cores, the scheduling and mapping of task are becomingevidently important. Based on the analysis of parallelization techniques and task mapping techniquesof multi-core systems, this thesis proposes a hierarchical task decomposition method and dynamictask scheduling technique based on embedded monitoring subnet. The decomposed calculation ofmatrix in same time complexity are discussed. Monitoring subnet provides data flow information, tobe used in intelligent control and processing of data flow. It also makes it possible to visualize andautomate the control process.
(5) In3D NOC design, with the increase in number of nodes, route design and low powerconsumption design are the two key techniques. This thesis analyzes the fundamental issue in NOCand3D interconnection and integration, discusses3D NOC route and3D NOC low powerconsumption model, and poses methods on route analysis and low power consumption analysis.
(6) To perform complicated signal processing on multi-core platforms is an engineeringproblem involving many disciplines. Based on the characteristics of parallel computing andmulti-core platforms, the thesis analyzes complexity issue of SAR signal processing, task schedulingmethods, and algorithm flow. SAR echo signal model and signal simulation algorithm are analyzed,along with echo simulation data calculation quantity and storage quantity. Several parallelcomputing and task decomposition methods on SAR echo simulation are proposed, as well as thetask and flow analysis on clustered multi-core platforms.
The main innovations and contributions include:
(1) Research field innovation. The concept of high density computing is proposed. High densitycomputing and multi-core computing is presented as an important research field. Multi-corecomputing, multi-core system evaluation, and multi-core system design are researched. Contributionis made to raise the research focus of multi-core system design and high-speed computing.
(2) Theoretical innovation. For the first time, real3D cluster NOC structure is proposed:3DStar Cluster (3D SC) structure. The thesis also raises the concept of3D Neighbor Code, and putsforth two3D Gray Code expansion methods. The contribution is to convert the geometricconnectivity relationship of the large number of3D NOC nodes into array relationship, whichfacilitates the numerical abstraction of the geometry model.
(3) Method innovation. Dynamic task scheduling technique based on embedded monitoringsubnet is proposed. This method could become the hardware foundation for the intelligentmanagement and automation control of multi-core computing. The contribution is to establish aclosed-loop system for dynamic data flow collection and control, and to enable the use of moderncontrol technique in multi-core data flow analysis and control.
人们对于便捷性和低碳性的追求，以前从不计较成本的HPC也开始关注单位空间、单位功耗、甚至单位资金投入所产生的计算速度等指标。使得高密度计算（High Density Computing，HDC）成为继高性能计算（High Performance Computing，HPC）之后又一个重要的研究方向。
从目前发展情况来看，CMP已经成为推动HPC和HDC继续进步的核心技术。本文依据HDC应用需求，研究CMP设计、评估和计算优化问题。主要内容包括：
（1）首先讨论了并行计算、高性能计算、多核计算等相关概念，以多核系统为支撑平台，提出了高密度计算（HDC）问题，给出了HDC的主要特征和所要研究的主要问题，提出了多核系统的评测问题。以数值计算中最具代表性的矩阵类任务作为研究对象，讨论了矩阵运算的一些基本问题，尤其是矩阵的分块运算和复杂度分析，分析了并行矩阵类任务的多核计算方法，为多核系统与矩阵类任务结合的问题研究给出了研究思路。
（2）在分析单芯片多核处理器结构和当前研究状况的基础上，给出了CMP的发展趋势和典型结构，即小核大数量处理器核、阵列和层次型簇结构，阐述了CMP体系结构的主要类型和基本设计原则，对并行计算模型、结构扩展和评估方法进行了理论分析；提出了“三维相邻码”概念和两种“扩展3D Gray码”的编码方法，即坐标扩展法和层扩展法，并分析了三维相邻码的特点和规律；提出了真正意义上的三维簇结构的3D NOC架构，即“三维星形簇（3DStar Cluster,简称3D SC）结构”。3D SC的NOC架构、节点编码和模型描述方法的提出和应用对于3D NOC的定量研究和分析具有重要的理论意义和使用价值。
（3）设计了兼容于MIPS指令集的单核RISC处理器，在此基础上实现了一种基于层次化AHB总线的四核处理器FPGA原型设计。探索了处理器结构的扩展性以及提高处理器整体性能的设计方法，利用多维矩阵相乘验证了系统性能和计算能力。实验结果表明，随着矩阵阶数的增加，多核处理器的加速比随之升高，印证了“处理器数的增加与问题规模的增加要保持平衡”的多核计算理论。
（4）随着核数量的增加，多核系统的任务调度与映射技术的重要性突显出来。本文在分析多核系统的并行调度技术和任务映射技术基础上，给出了层次化任务分解方法，重点讨论了矩阵类任务的等时间复杂度的分块计算，提出了基于嵌入式监控子网的动态任务调度技术。监视子网可以提供数据流信息，用于数据流的智能监控和处理，为提高控制过程可视化和自动化提供了可能。
（5）在3D NoC设计中，随着节点数量的增加，路由设计和低功耗设计是两个关键技术。本文在分析NoC及3D互连集成基本问题的基础上，给出了低功耗研究的基本思路，重点讨论了3D NoC的路由和3D NoC的低功耗模型，给出了3D NOC路由分析和低功耗分析方法。
（6）在多核平台上进行复杂信号处理是一个牵涉面很广的工程问题。本文针对并行计算和多核平台特点，对合成孔径雷达（SAR）信号处理的复杂性问题、任务分解方法、算法流程等问题进行了分析。主要分析了SAR回波信号模型和信号模拟算法，分析了回波模拟数值计算的计算量和存储量，给出了SAR回波模拟的几种并行计算和任务分解方法，以及在簇结构多核平台上进行计算的任务和流程分析。
本文的主要创新点及其意义：
（1）研究领域创新。提出了高密度计算的概念，将高密度计算与多核计算作为一个重要的研究领域。本文以此为切入点，对多核计算、多核系统评测和多核系统设计几个重要问题进行了研究。其意义在于，提升了多核系统设计和高速计算研究的针对性。
（2）理论创新。提出了真正意义的三维(3D)簇的NOC结构，即三维星型簇（3D SC）结构，针对该结构首次提出了三维相邻编码概念和两种扩展三维格雷（3D Gray）编码方法。其意义在于，可以将3D NOC的大数量节点的几何互连关系转换为数组关系，便于几何模型的数值化抽象。
（3）方法创新。提出了基于嵌入监控子网的动态任务调度方法，这个思路可望作为多核计算中智能调度和自动化控制的硬件基础。其意义在于，便于建立动态数据流采集和控制的闭环系统，使得现代控制论技术用于多核数据流分析和控制成为可能。
Electronic system design is being challenged by the high degree of integration and combinationof functionality. The restriction of volume, weight, and energy consumption is making theminimization of electronic system an challenge. CMP (chip multiprocessor), SiP (System inPackage), MEMs (Mirco-Electro Mechanical System), and NEMs (Nano-Electro MechanicalSystem),3D (Three Dimension) integration are becoming important areas of research in integratedcircuit design.
The pursuit of convenience and low-carbon is making high density computing (HDC) anotherimportant research area after high performance computing (HPC). Even HPC, which used to not careabout cost, is becoming more concerned about unit space, unit power consumption, and evencomputing speed per unit investment.
Based on the current development, CMP is becoming the key technology to advance HPC andHDC. This dissertation focuses on CMP design, evaluation, and optimization for the practical needsof HDC. It includes the following:
(1) The concepts of parallel computing, high performance computing and multi-core computing,etc. are discussed. Using the multi-core system as the base platform, HDC is presented, along withthe main features of HDC and the primary research topics, as well as the evaluation of multi-coresystems. Basic problems in matrix operations are discussed, especially matrix decompositionmethods and complexity analysis. The thesis analyzes multi-core computation methods of parallelmatrix operation, and gives thoughts on the combination of multi-core systems and matrixoperations.
(2) Based on the analysis of single chip multi-core processor structure and current research, thethesis presents the trend and typical structure of CMP: small core, big quantity, array andhierarchical clusters. It expounds the main types and basic design principles, and makes a theoreticalanalysis of parallel computation models, structure extension, and evaluation methods. The thesisproposes the concept of3D Neighbor Code and two types of coding methods to expand3D Graycode: coordinate expansion method and layer expansion method. It also analyzes the characteristicsand patterns of3D Neighbor Code, and proposes an3D NOC structure of real3D cluster structure:the3D Star Cluster (3D SC) structure. The NOC structure, node coding, and model descriptionmethod for3D SC are important contributions towards the quantitative research and analysis, forboth theoretical purpose and practical purpose.
(3) This thesis designs a single-core RISC processor compatible with MIPS instruction set, andaccomplishes a4-core processor FPGA prototype design based on hierarchical AHB bus. It explores extensibility of processor structure and design method to increase total processor functionality.Multi-dimension matrix multiplication is used to verify system functionality and computation power.Experiments show that multi-core processor performance increases with the increase of matrixdimensions. This corroborates the theory of “balance must be maintained between the increase ofnumber of processors and the increase of problem scale.”
(4) With the increase in number of cores, the scheduling and mapping of task are becomingevidently important. Based on the analysis of parallelization techniques and task mapping techniquesof multi-core systems, this thesis proposes a hierarchical task decomposition method and dynamictask scheduling technique based on embedded monitoring subnet. The decomposed calculation ofmatrix in same time complexity are discussed. Monitoring subnet provides data flow information, tobe used in intelligent control and processing of data flow. It also makes it possible to visualize andautomate the control process.
(5) In3D NOC design, with the increase in number of nodes, route design and low powerconsumption design are the two key techniques. This thesis analyzes the fundamental issue in NOCand3D interconnection and integration, discusses3D NOC route and3D NOC low powerconsumption model, and poses methods on route analysis and low power consumption analysis.
(6) To perform complicated signal processing on multi-core platforms is an engineeringproblem involving many disciplines. Based on the characteristics of parallel computing andmulti-core platforms, the thesis analyzes complexity issue of SAR signal processing, task schedulingmethods, and algorithm flow. SAR echo signal model and signal simulation algorithm are analyzed,along with echo simulation data calculation quantity and storage quantity. Several parallelcomputing and task decomposition methods on SAR echo simulation are proposed, as well as thetask and flow analysis on clustered multi-core platforms.
The main innovations and contributions include:
(1) Research field innovation. The concept of high density computing is proposed. High densitycomputing and multi-core computing is presented as an important research field. Multi-corecomputing, multi-core system evaluation, and multi-core system design are researched. Contributionis made to raise the research focus of multi-core system design and high-speed computing.
(2) Theoretical innovation. For the first time, real3D cluster NOC structure is proposed:3DStar Cluster (3D SC) structure. The thesis also raises the concept of3D Neighbor Code, and putsforth two3D Gray Code expansion methods. The contribution is to convert the geometricconnectivity relationship of the large number of3D NOC nodes into array relationship, whichfacilitates the numerical abstraction of the geometry model.
(3) Method innovation. Dynamic task scheduling technique based on embedded monitoringsubnet is proposed. This method could become the hardware foundation for the intelligentmanagement and automation control of multi-core computing. The contribution is to establish aclosed-loop system for dynamic data flow collection and control, and to enable the use of moderncontrol technique in multi-core data flow analysis and control.
引文
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