锁相环用新型全差分CMOS电荷泵设计
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摘要
随着无线通信技术的发展,锁相环(PLL,Phase-Locked Loop)被广泛应用于各种电子产品中,同时也对锁相环的性能提出了更高的要求。高频率、低电压、低功耗、低噪声、高稳定性锁相环的需求量越来越大。在各种锁相环结构中,电荷泵锁相环(CPPLL,Charge-Pump Phase-Locked Loop)以其锁定相差小和捕获范围大的优点成为当前锁相环产品的主流。
本文首先论述了锁相环基本原理和结构,叙述了鉴相器、环路滤波器和压控振荡器结构及原理,对锁相环进行了时域分析和频域分析,介绍了电荷泵基本结构和原理,并对各类电荷泵电路进行了讨论,对电荷泵设计中常见的问题进行了分析和讨论,如电荷泄漏、电荷失配以及电荷泵设计中的非理想因素等。本文重点分析了传统电荷泵电路的原理及其存在的问题,为了解决这个问题,将运放加入传统电荷泵电路中,以改进电路的性能。在分析单端电荷泵和差分电荷泵优缺点的基础上,将两者结合起来设计了差分输入单端输出型电荷泵,以提高电荷泵的开关速度、降低其功耗和降低其输出电压抖动,并对其电流开关进行了分析。接着在分析该电路中晶体管的沟道调制效应时发现其会影响充电电流的精确度,于是对该电路进行了进一步改进,采用共源共栅结构和大摆幅电流镜,使充放电电流波形保持基本对称,以提高镜像电流的精确度,把正反馈型的电流驱动型电荷泵和差分型电荷泵结合起来,设计了全差分型电荷泵。
基于TSMC 0.18μm CMOS工艺,利用Cadence Spectre仿真工具进行了仿真,当电源电压为1.8V,电荷泵电流为50μA,频率为500MHz时,输出电压范围是-1.8V～+1.8V,功耗为0.15mW。
With the development of wireless communication, PLL (Phase-Locked Loop) is widely used in various kinds of electronic productions, simultaneously which requests better performance PLL. What people need is the PLL with high-frequency, low-voltage, low-power dissipation, low-noise, high-stability. Among various PLLs, CPPLL (Charge-Pump Phase- Locked Loop) become current PLL products mostly for its little phase-offset and large acquisition range.
Charge pump is a kind of usage electric charge to produce the high-handed electric circuit at the backlog in the electric capacity( high in power supply electric voltage) . In lock mutually the wreath PLL electric circuit, the main function of the electric charge pump is to be PFD’s the numerical signal(the UP and DW) of the machine output's is converted in to imitate the signal to control to press to control to flap to concuss the machine(VCO) of frequency. When the PFD give a high accuracy mutually an error margin, the electric charge pump electric circuit has to the whole function of wreath road decisive function, namely the PLL target later even if pimping motions of the exportation electric voltage of the electric charge pumps all will cause the VCO exportation frequency to tremble to move, thus leading to go into the noise. The traditional electric charge pumps the electric circuit to exist the electric charge to reveal, the steady long exportation electric voltage scope does not greatly wait the blemish.A new novel fully-differential charge pump for PLL was designed in this paper, and differential input and differential output was used in this circuit. The way of differential input and differe- ntial output may eliminate the noise for leakage current and charge/discharge current mismat- ches, and increase the speed of circuit and the range of output voltage, and decrease and the power dissipation.
The circuit was simulated by the Spectre in Cadence with CMOS 0.18μm process. When the voltage source is 1.8V, together with the current of 50μA and the frequency of 500MHz, it is shown that the range of output voltage is -1.8V~+1.8V, and the power dissipation is 0.15mW.
本文首先论述了锁相环基本原理和结构,叙述了鉴相器、环路滤波器和压控振荡器结构及原理,对锁相环进行了时域分析和频域分析,介绍了电荷泵基本结构和原理,并对各类电荷泵电路进行了讨论,对电荷泵设计中常见的问题进行了分析和讨论,如电荷泄漏、电荷失配以及电荷泵设计中的非理想因素等。本文重点分析了传统电荷泵电路的原理及其存在的问题,为了解决这个问题,将运放加入传统电荷泵电路中,以改进电路的性能。在分析单端电荷泵和差分电荷泵优缺点的基础上,将两者结合起来设计了差分输入单端输出型电荷泵,以提高电荷泵的开关速度、降低其功耗和降低其输出电压抖动,并对其电流开关进行了分析。接着在分析该电路中晶体管的沟道调制效应时发现其会影响充电电流的精确度,于是对该电路进行了进一步改进,采用共源共栅结构和大摆幅电流镜,使充放电电流波形保持基本对称,以提高镜像电流的精确度,把正反馈型的电流驱动型电荷泵和差分型电荷泵结合起来,设计了全差分型电荷泵。
基于TSMC 0.18μm CMOS工艺,利用Cadence Spectre仿真工具进行了仿真,当电源电压为1.8V,电荷泵电流为50μA,频率为500MHz时,输出电压范围是-1.8V～+1.8V,功耗为0.15mW。
With the development of wireless communication, PLL (Phase-Locked Loop) is widely used in various kinds of electronic productions, simultaneously which requests better performance PLL. What people need is the PLL with high-frequency, low-voltage, low-power dissipation, low-noise, high-stability. Among various PLLs, CPPLL (Charge-Pump Phase- Locked Loop) become current PLL products mostly for its little phase-offset and large acquisition range.
Charge pump is a kind of usage electric charge to produce the high-handed electric circuit at the backlog in the electric capacity( high in power supply electric voltage) . In lock mutually the wreath PLL electric circuit, the main function of the electric charge pump is to be PFD’s the numerical signal(the UP and DW) of the machine output's is converted in to imitate the signal to control to press to control to flap to concuss the machine(VCO) of frequency. When the PFD give a high accuracy mutually an error margin, the electric charge pump electric circuit has to the whole function of wreath road decisive function, namely the PLL target later even if pimping motions of the exportation electric voltage of the electric charge pumps all will cause the VCO exportation frequency to tremble to move, thus leading to go into the noise. The traditional electric charge pumps the electric circuit to exist the electric charge to reveal, the steady long exportation electric voltage scope does not greatly wait the blemish.A new novel fully-differential charge pump for PLL was designed in this paper, and differential input and differential output was used in this circuit. The way of differential input and differe- ntial output may eliminate the noise for leakage current and charge/discharge current mismat- ches, and increase the speed of circuit and the range of output voltage, and decrease and the power dissipation.
The circuit was simulated by the Spectre in Cadence with CMOS 0.18μm process. When the voltage source is 1.8V, together with the current of 50μA and the frequency of 500MHz, it is shown that the range of output voltage is -1.8V~+1.8V, and the power dissipation is 0.15mW.
引文
[1] 敬小成.电荷泵锁相环的研究与设计[D] .广州:华南理工大学,2007: 2-10.
[2] 吴亮.1.25-GHz CMOS 集成低抖动电荷泵锁相环的设计与实现[D].上海:复旦大学,2007: 3-9.
[3] Armond Hairapitian, Jun Cao Afshin Momtaz. Fully differential CMOS Phase Locked Loop[J]. United States Patent, 2004, 4(13):22-24.
[4] 莫秉轩,陈钟鸣,鲁迎春. 一种可用于高性能锁相环的 CMOS 电荷泵[J].合肥工业工业大学学报(自然科学版), 2006, 29(3): 369-372.
[5] 楚 薇 .低 压 CMOS 电 荷 泵 的 设 计 及 应 用 [J].合 肥 工 业 大 学 学 报 , 2004, 5(2):69-73.
[6] 俞宏,韩雁.新型低压 ? 高速CMOS 电荷泵电路[J].电子器件, 2005, 28(2): 279-282.
[7] 杨运福,戴庆元,刘天伟.一种新型的低压高速 CMOS 锁相环电荷泵[J].微处理机,2006,1(3):11-13
[8] G. Kamoulakos, Y. T siatouhas. Management of charge pump circuit[J]. Integration the VLSI journal, 2000, 30(5):91-101.
[9] 彭颖,应建华,颜学超,李春霞. 一种用于锁相环的正反馈互补型电荷泵电路[J].华中科技大学学报(自然科学版) ,2005,5(2):57-60.
[10] 袁小云,张瑞智,王洪娜. 一种新型电荷泵电路的设计[J].微电子学与计算机 , 2003,8(9) :61-64
[11] P.E. 艾伦, D.R. 霍尔伯格.CMOS 拟电路设计 [M].北京 :科学出版社,1995:78-90.
[12] 阙金珍,刘红侠,郝跃.电荷泵电路功耗优化设计及改进[J].微电子学,2006, 36(3): 373-376.
[13] 朱正涌.半导体集成电路[M].北京:清华大学出版社,2001:112-115.
[14] 王洪魁,袁小云,张瑞智.低噪声 ? 低功耗CMOS 电荷泵锁相环设计[J].固体电子学研究与进展, 2004,24(1):81-85.
[15] 刘小燕,叶青.CMOS 电荷泵的结构设计与分析 [J].科学技术与工程,2006,16(13): 1794-1797.
[16] R.M. Ziazadeh, H. T. Ng, and D .J .Allstot. A Multistage Amplifier Topology with Embeded Tracking Compensation,CICC proc, 1998, 5(6):361-364
[17] 秦世才,高清远.现代模拟集成电子学[M]. 北京:科学出版社,2003: 48-56.
[18] Iasson F.Vassiliou. Top down Design of a Phase locked Loop For a Video Driver System [J]. Proceeding of the Custom Integrated Circuit Conference, 1999,5(6):21-23.
[19] 江玮,唐守龙,陆生礼. 一种快速锁定 PLL 的电荷泵设计[J]. 电子器件, 2007, 3(6): 23-26.
[20] 刘威,陈杰. 锁相环中低电流失配电荷泵的设计[J]. 科学技术与工程,2006,5(14): 33-35.
[21] Ching-Che Chung, Chen-Lee. An All-Digital Phase Locked Loop for High- Speed Clock Generation[J]. IEEE Journal of Solid-State Circuits, 2003, 8(2), 347-351.
[22] 王志功.光纤通信集成电路设计[M].北京:高等教育版社,2003:231-234
[23] B.Razavi. A study of phase noise in CMOS oscillators[J].IEEE J. Solid-State Circuits,1996,3(15):331-343.
[24] Behzad Razavi .Design of Analog CMOS Integrated Circuits[M]. America:McGraw-Hill, 2001: 412-418.
[25] Thomas H.Lee. The Design of CMOS Radio-Frequency Integrated Circuits[M]. Beijing: Publishing House of Electronics Industry,2004: 315 -344.
[26] 王福昌,鲁昆生.锁相技术[M].武汉:华中科技大学出版社,1999: 156-160.
[27] 陈文焕, 叶星宁. 三阶电荷泵锁相环系统级设计与仿真验证[J].电子设计应用, 2005,5(3): 51-54.
[28] 胡建赟,闵昊. 一种适用于 NRZ 数据的时钟数据恢复电路[J]. 微电子学,2005, 8(6): 42-45.
[29] Floyd M .Gardner. Charge-Pump Phase-Lock Loops[J]. IEEE Trans commun, 1980, 8(11),1849-1858
[30] 蒋召宇,李丽,徐诺.电荷泵锁相环中相位噪声的抑制和讨论[J].现代电子技术, 2004, 5(12) :46-49.
[31] Mark Van Paemel. Analysis of a Charge-Pump PLL[J]: IEEE Trans Com-mun, 1994, 6(8):2490-2498.
[32] 鲁昆生,王福昌.电荷泵锁相环设计方法研究[J].华中理工大学学报,2000, 5(1): 15-18.
[33] 刘晓燕, 叶青. CMOS 电荷泵的结构设计与分析[J].科学技术与工程, 2006, 5(13): 21-24.
[34] 黄水文,徐勇,黄颋.应用于 5GHz 无线局域网的频率合成器设计[J].电子工程师,2004,5(3): 32-36.
[35] 张丽,王洪魁,张瑞智.三阶电荷泵锁相环锁定时间的研究[J].固体电子学研究与进展, 2004,5(2) :69-72.
[36] Henrik O.Johansson. A Simple Precharged CMOS Phase Frequency Detector[J]. IEEE Solid-State Circuits, 1998,2(33):295-299.
[37] 温显光,解宁,何乐年. 高速 PLL 电路中的电荷泵电路设计[J]. 微电子学与计算机, 2004, 5(12): 58-62.
[38] Lin Yijing, Sheng Shimin. A Novel Charge Pump in PLL[J]. Acta Scientiarum Naturali-um Universitatis Pekinensis, 2002, 38(3),58-60.
[39] 吴宏,陈吉华,陈怒兴.高性能锁相环中电荷泵电路研究[J].计算机工程与科学, 2006,5(4): 52-55.
[40] Armond Hairapitian , Jun Cao , Afshin Momtaz . Fully differential CMOS Phase Locked Loop[J]. United States Patent, 2004, 13(5):65-68.
[2] 吴亮.1.25-GHz CMOS 集成低抖动电荷泵锁相环的设计与实现[D].上海:复旦大学,2007: 3-9.
[3] Armond Hairapitian, Jun Cao Afshin Momtaz. Fully differential CMOS Phase Locked Loop[J]. United States Patent, 2004, 4(13):22-24.
[4] 莫秉轩,陈钟鸣,鲁迎春. 一种可用于高性能锁相环的 CMOS 电荷泵[J].合肥工业工业大学学报(自然科学版), 2006, 29(3): 369-372.
[5] 楚 薇 .低 压 CMOS 电 荷 泵 的 设 计 及 应 用 [J].合 肥 工 业 大 学 学 报 , 2004, 5(2):69-73.
[6] 俞宏,韩雁.新型低压 ? 高速CMOS 电荷泵电路[J].电子器件, 2005, 28(2): 279-282.
[7] 杨运福,戴庆元,刘天伟.一种新型的低压高速 CMOS 锁相环电荷泵[J].微处理机,2006,1(3):11-13
[8] G. Kamoulakos, Y. T siatouhas. Management of charge pump circuit[J]. Integration the VLSI journal, 2000, 30(5):91-101.
[9] 彭颖,应建华,颜学超,李春霞. 一种用于锁相环的正反馈互补型电荷泵电路[J].华中科技大学学报(自然科学版) ,2005,5(2):57-60.
[10] 袁小云,张瑞智,王洪娜. 一种新型电荷泵电路的设计[J].微电子学与计算机 , 2003,8(9) :61-64
[11] P.E. 艾伦, D.R. 霍尔伯格.CMOS 拟电路设计 [M].北京 :科学出版社,1995:78-90.
[12] 阙金珍,刘红侠,郝跃.电荷泵电路功耗优化设计及改进[J].微电子学,2006, 36(3): 373-376.
[13] 朱正涌.半导体集成电路[M].北京:清华大学出版社,2001:112-115.
[14] 王洪魁,袁小云,张瑞智.低噪声 ? 低功耗CMOS 电荷泵锁相环设计[J].固体电子学研究与进展, 2004,24(1):81-85.
[15] 刘小燕,叶青.CMOS 电荷泵的结构设计与分析 [J].科学技术与工程,2006,16(13): 1794-1797.
[16] R.M. Ziazadeh, H. T. Ng, and D .J .Allstot. A Multistage Amplifier Topology with Embeded Tracking Compensation,CICC proc, 1998, 5(6):361-364
[17] 秦世才,高清远.现代模拟集成电子学[M]. 北京:科学出版社,2003: 48-56.
[18] Iasson F.Vassiliou. Top down Design of a Phase locked Loop For a Video Driver System [J]. Proceeding of the Custom Integrated Circuit Conference, 1999,5(6):21-23.
[19] 江玮,唐守龙,陆生礼. 一种快速锁定 PLL 的电荷泵设计[J]. 电子器件, 2007, 3(6): 23-26.
[20] 刘威,陈杰. 锁相环中低电流失配电荷泵的设计[J]. 科学技术与工程,2006,5(14): 33-35.
[21] Ching-Che Chung, Chen-Lee. An All-Digital Phase Locked Loop for High- Speed Clock Generation[J]. IEEE Journal of Solid-State Circuits, 2003, 8(2), 347-351.
[22] 王志功.光纤通信集成电路设计[M].北京:高等教育版社,2003:231-234
[23] B.Razavi. A study of phase noise in CMOS oscillators[J].IEEE J. Solid-State Circuits,1996,3(15):331-343.
[24] Behzad Razavi .Design of Analog CMOS Integrated Circuits[M]. America:McGraw-Hill, 2001: 412-418.
[25] Thomas H.Lee. The Design of CMOS Radio-Frequency Integrated Circuits[M]. Beijing: Publishing House of Electronics Industry,2004: 315 -344.
[26] 王福昌,鲁昆生.锁相技术[M].武汉:华中科技大学出版社,1999: 156-160.
[27] 陈文焕, 叶星宁. 三阶电荷泵锁相环系统级设计与仿真验证[J].电子设计应用, 2005,5(3): 51-54.
[28] 胡建赟,闵昊. 一种适用于 NRZ 数据的时钟数据恢复电路[J]. 微电子学,2005, 8(6): 42-45.
[29] Floyd M .Gardner. Charge-Pump Phase-Lock Loops[J]. IEEE Trans commun, 1980, 8(11),1849-1858
[30] 蒋召宇,李丽,徐诺.电荷泵锁相环中相位噪声的抑制和讨论[J].现代电子技术, 2004, 5(12) :46-49.
[31] Mark Van Paemel. Analysis of a Charge-Pump PLL[J]: IEEE Trans Com-mun, 1994, 6(8):2490-2498.
[32] 鲁昆生,王福昌.电荷泵锁相环设计方法研究[J].华中理工大学学报,2000, 5(1): 15-18.
[33] 刘晓燕, 叶青. CMOS 电荷泵的结构设计与分析[J].科学技术与工程, 2006, 5(13): 21-24.
[34] 黄水文,徐勇,黄颋.应用于 5GHz 无线局域网的频率合成器设计[J].电子工程师,2004,5(3): 32-36.
[35] 张丽,王洪魁,张瑞智.三阶电荷泵锁相环锁定时间的研究[J].固体电子学研究与进展, 2004,5(2) :69-72.
[36] Henrik O.Johansson. A Simple Precharged CMOS Phase Frequency Detector[J]. IEEE Solid-State Circuits, 1998,2(33):295-299.
[37] 温显光,解宁,何乐年. 高速 PLL 电路中的电荷泵电路设计[J]. 微电子学与计算机, 2004, 5(12): 58-62.
[38] Lin Yijing, Sheng Shimin. A Novel Charge Pump in PLL[J]. Acta Scientiarum Naturali-um Universitatis Pekinensis, 2002, 38(3),58-60.
[39] 吴宏,陈吉华,陈怒兴.高性能锁相环中电荷泵电路研究[J].计算机工程与科学, 2006,5(4): 52-55.
[40] Armond Hairapitian , Jun Cao , Afshin Momtaz . Fully differential CMOS Phase Locked Loop[J]. United States Patent, 2004, 13(5):65-68.