两种CMOS串行通信接口芯片的设计
摘要
随着信息化技术的发展，计算机之间的互联及数据传送愈发频繁，多种通信协议应运而生，符合规范的接口芯片对一个性能良好的电子系统的重要性日益凸现。本文针对分别适用于两种不同接口协议的芯片进行了深入系统的研究，完成了电路设计，并采用MPW(Multi Project Wafer，多项目晶圆)完成了代工流片制造。
首先，文章给出了两种目前较流行的通信接口协议的标准：RS-422和LVDS，并分析了二者的优缺点。前者的电气特性由TIA／EIA RS-422B规定，它是一种是利用差分传输方式提高通信距离和可靠性的通信标准，具有抗共模干扰能力强、传输距离远的特点，但数据传送速率相对较低。后者LVDS的全称为Low Voltage Differential Signal，即低电压差分信号。LVDS标准具有高速、低功耗、低误码率、低串扰和低辐射等特点，在对信号完整性、低抖动及共模特性要求较高的系统中得到了越来越广泛的应用。
其次，文章针对这TIA／EIA RS-422B和ANSI／TIA／EIA—644两种协议分别设计了符合规范的接口电路，其中RS-422接口芯片为四通道差分输出线驱动器，LVDS接口芯片为单通道差分输出。RS-422驱动器能够将一位CMOS信号转换为一对差分信号，差分输出电压为2.73V，传输速率可达10Mbps，具有上电复位功能和与TTL电平兼容的接口；LVDS驱动器可发送速率高达500Mbps的数据，输出电流3.4mA，差模输出电平300mV，内置高精度基准源及共模反馈电路，可将共模输出电平稳定在1.24V。
第三，在完成电路设计后，采用CSMC 6S05 DPTM-ST2100的设计规则，使用Cadence Virtuoso自主设计了芯片的版图。版图设计中特别强调了匹配性设计，将因器件失配引起的误差降到最低；通过特别添加的ESD保护使芯片具有良好的抗静电能力；精心设计的保护环与器件布局有效地避免了闩锁现象的发生。所设计的版图在通过DRC／LVS验证后，最终生成GDSⅡ格式的文件交付代工厂家流片。目前RS-422接口芯片已拿到样片，经测试功能基本达到了预期目标。
With the great development of information technology, the interconnection and data transmission between computers have become more frequent. Multiple communication protocols have emerged. The importance of a standardized interface chip for a well performanced electronic system has become more apparent. In-depth research on two kinds of interface chip is conducted in this paper.
First, the article gives two popular communication protocols: RS-422 and LVDS. The advantages and disadvantages of both are analysed. The former electrical characteristic is defined by TIA/EIA RS-422B, which employs differential transmission to improve the communication reliability and distance. RS-422 has strong common mode interference rejecting ability. But the data transmission rate is relatively low. The latter's full name is Low Voltage Differential Signal, which has many distinguish features such as high-speed, low-power, low bit error rate, low crosstalk, low radiation, and so on. So, LVDS is more widely used in systems that require high signal integrity, low jitter and strict common mode characteristic.
Second, two standardized interface ICs, respectively meet TIA/EIA RS-422B and ANSI/TIA/EIA-644 standard are developed. The RS-422 interface chip is a four-channel differential output line driver, which can transfer a CMOS/TTL signal to a pair of differential signal. The differential output voltage is 2.73V, and the date rate can reaches up to 10Mbps.Power-on reset and TTL compatible interface is featured. LVDS interface chip is a single-channel differential output line driver. The transmission rate of LVDS driver is up to 500Mbps, output current is 3.4mA, and differential output voltage is 300mV. The built-in precise bandgap reference and common-mode feedback circuit can restrict common mode output level steady at 1.24V.
Thirdly, after the completion of circuit design, CSMC 6S05 DPTM -ST2100 design rule is utilized to fulfill the layout. Device match is emphasized in layout design, which minimizes errors caused by mismatch; ESD protection circuit is added to enhance the antistatic capacity of whole chip; The guard ring and floorplan is carefully designed so that the latch-up can be avoid. Through DRC/LVS verifying, the final GDSII format date is generated and delivered to manufacturers to taped-out. Now, the sample of RS-422 interface chip has been received. It behaves well under test.
首先，文章给出了两种目前较流行的通信接口协议的标准：RS-422和LVDS，并分析了二者的优缺点。前者的电气特性由TIA／EIA RS-422B规定，它是一种是利用差分传输方式提高通信距离和可靠性的通信标准，具有抗共模干扰能力强、传输距离远的特点，但数据传送速率相对较低。后者LVDS的全称为Low Voltage Differential Signal，即低电压差分信号。LVDS标准具有高速、低功耗、低误码率、低串扰和低辐射等特点，在对信号完整性、低抖动及共模特性要求较高的系统中得到了越来越广泛的应用。
其次，文章针对这TIA／EIA RS-422B和ANSI／TIA／EIA—644两种协议分别设计了符合规范的接口电路，其中RS-422接口芯片为四通道差分输出线驱动器，LVDS接口芯片为单通道差分输出。RS-422驱动器能够将一位CMOS信号转换为一对差分信号，差分输出电压为2.73V，传输速率可达10Mbps，具有上电复位功能和与TTL电平兼容的接口；LVDS驱动器可发送速率高达500Mbps的数据，输出电流3.4mA，差模输出电平300mV，内置高精度基准源及共模反馈电路，可将共模输出电平稳定在1.24V。
第三，在完成电路设计后，采用CSMC 6S05 DPTM-ST2100的设计规则，使用Cadence Virtuoso自主设计了芯片的版图。版图设计中特别强调了匹配性设计，将因器件失配引起的误差降到最低；通过特别添加的ESD保护使芯片具有良好的抗静电能力；精心设计的保护环与器件布局有效地避免了闩锁现象的发生。所设计的版图在通过DRC／LVS验证后，最终生成GDSⅡ格式的文件交付代工厂家流片。目前RS-422接口芯片已拿到样片，经测试功能基本达到了预期目标。
With the great development of information technology, the interconnection and data transmission between computers have become more frequent. Multiple communication protocols have emerged. The importance of a standardized interface chip for a well performanced electronic system has become more apparent. In-depth research on two kinds of interface chip is conducted in this paper.
First, the article gives two popular communication protocols: RS-422 and LVDS. The advantages and disadvantages of both are analysed. The former electrical characteristic is defined by TIA/EIA RS-422B, which employs differential transmission to improve the communication reliability and distance. RS-422 has strong common mode interference rejecting ability. But the data transmission rate is relatively low. The latter's full name is Low Voltage Differential Signal, which has many distinguish features such as high-speed, low-power, low bit error rate, low crosstalk, low radiation, and so on. So, LVDS is more widely used in systems that require high signal integrity, low jitter and strict common mode characteristic.
Second, two standardized interface ICs, respectively meet TIA/EIA RS-422B and ANSI/TIA/EIA-644 standard are developed. The RS-422 interface chip is a four-channel differential output line driver, which can transfer a CMOS/TTL signal to a pair of differential signal. The differential output voltage is 2.73V, and the date rate can reaches up to 10Mbps.Power-on reset and TTL compatible interface is featured. LVDS interface chip is a single-channel differential output line driver. The transmission rate of LVDS driver is up to 500Mbps, output current is 3.4mA, and differential output voltage is 300mV. The built-in precise bandgap reference and common-mode feedback circuit can restrict common mode output level steady at 1.24V.
Thirdly, after the completion of circuit design, CSMC 6S05 DPTM -ST2100 design rule is utilized to fulfill the layout. Device match is emphasized in layout design, which minimizes errors caused by mismatch; ESD protection circuit is added to enhance the antistatic capacity of whole chip; The guard ring and floorplan is carefully designed so that the latch-up can be avoid. Through DRC/LVS verifying, the final GDSII format date is generated and delivered to manufacturers to taped-out. Now, the sample of RS-422 interface chip has been received. It behaves well under test.
引文
[1] 吴献．RS-422通信接口芯片在0.6μm工艺下的设计与实现：(硕士学位论文)．杭州：浙江大学，2006．
[2] 唐茂华．RS422通信接口卡的设计与实现．电讯技术．2004，(5)：161-165．
[3] 刘正，游轶雄，王健，许继衡．CMOS线驱动器输出信号压摆率控制的研究．微电子学．2003，33(4)：276-279．
[4] 张健，吴晓冰．LVDS技术原理和设计简介．电子技术应用．2000，35(5)：66-67．
[5] Rees J．单端PECL与差分PECL的互连．电子产品世界．2001，(10)：37-39．
[6] 刘祥远，陈书明．LVDS高速I／O接口单元的设计研究．计算机工程与科学．2001，23(4)：52-56．
[7] 万湘绮，张慧军．迈向21世纪的平板显示器．电子计算机与外部设备．2000，24(2)：16—18．
[8] Kang S M，Leblebici Y．CMOS数字集成电路—分析与设计．北京：电子工业出版社，2005．
[9] Phillip E．A，Holberg D R．CMOS模拟集成电路设计．北京：电子工业出版社，2005．
[10] 李伟华．VLSI设计基础．北京：电子工业出版社，2002．
[11] Hodges D A，Jackson H G，Saleh R A．Analysis and Design of Digital Integrated Circuits．北京：清华大学出版社，2004．
[12] 孙肖子，张健康，张犁等．专用集成电路设计基础．西安：西安电子科技大学出版社，2003．
[13] 高保嘉．MOS VLSI分析与设计．北京：电子工业出版社，2002．
[14] 高明伦，张红莉，徐诺．一种基于比较器的新型片内上电复位电路的实现．中国集成电路．2004，(63)：31-35
[15] 赵忠文，曾峦，熊伟．LVDS技术分析和应用设计．装备指挥技术学院学报，2001，12(6)：89-93．
[16] Gray P R, Hurst P J, Lewis S H et al. hnalysis and design of analog integrated circuits. Beijing:Higher Education Pr., 2003.
[17] 毕查德·拉扎维．模拟CMOS集成电路设计．西安：西安交通大学出版社，2003．
[18] Chen M D, Martinez J S, Michael, Nix M, Robinson E. Low-Voltage Low-Power LVDS driver. IEEE Journal of Solie-State Circuit. 2005,40(2):472-479.
[19] Boni A, Pierazzi A, Vecchi D. LVDS I/O interface for Gb/s-per-pin operation in 0.35μm CMOS. IEEE Journal of Solid-State Circuits, 36, (4):706-711.
[20] Chow H C, Sheen W W. Low Power LVDS Circuit for Serial Data Communications. Proceeding of 2005 International Symposium on Intelligent Signal Processing and Communication Systems. HongKong. 2005:293-296.
[21] 韩雁．专用集成电路设计技术基础．成都：电子科技大学出版社，1999．
[22] Young B. An SOI CMOS LVDS driver and receiver pair. Digest of Technical Papers Of VLSI Circuits. 2001:153-154.
[23] Malcovati P,Maloberti F, Fiocchi C et al. Curature-compensated BiCMOS bandgap with 1-V supply voltage. IEEE Journal of Solid-State Circuits. 2001,36:1076-1081.
[24] Bult K, Govet J G M.A fast settling CMOS Amp for SC circuits with 90dB Gain. IEEE Journal of Solid Circuit. 1990,25(6):1169-1184.
[25] Wang C C, Huang J M, Huang J F. 1. OGbps LVDS Transceiver design for LCD panels. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits. 2004:236-239.
[26] 朱正涌．半导体集成电路．北京：清华大学出版社，2001．
[27] Hast ings A．The Art of Analog Layout．北京：清华大学出版社，2004．
[28] 马仲发，庄奕琪，杜磊等，一种敏感MOSFET ESD潜在损伤检测方法．半导体学报，2002，23(11)：1211-1216．
[29] 臧佳锋，薛忠杰．深亚微米CMOS IC全芯片ESD保护技术．电子与封装．2005，6(5)：20-30．
[30] 姚维连，孙伟锋，吴建辉．CMOS集成电路中电源和地之间的ESD保护电路设计．接地防护技术．2004，(5)：12-15．
[31] 邓永孝．半导体器件失效分析．北京：宇航出版社，1991．
[32] Su D. Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. IEEE J. of Solid-State Circuits, 1993, 28(4):420～430
[33] 李志坚，周润德．ULSI器件电路与系统．北京：科学出版社，2001．
[34] 赵天麟．关于LSI／VLSI的设计规则检查．微处理机．1998，(1)：11-14．
[35] 薛耀国，韩继国，冯金初等．硅栅CMOS电路版图设计规则检查全面性探讨．微电子学与计算机．1994，(4)：4-7．
[2] 唐茂华．RS422通信接口卡的设计与实现．电讯技术．2004，(5)：161-165．
[3] 刘正，游轶雄，王健，许继衡．CMOS线驱动器输出信号压摆率控制的研究．微电子学．2003，33(4)：276-279．
[4] 张健，吴晓冰．LVDS技术原理和设计简介．电子技术应用．2000，35(5)：66-67．
[5] Rees J．单端PECL与差分PECL的互连．电子产品世界．2001，(10)：37-39．
[6] 刘祥远，陈书明．LVDS高速I／O接口单元的设计研究．计算机工程与科学．2001，23(4)：52-56．
[7] 万湘绮，张慧军．迈向21世纪的平板显示器．电子计算机与外部设备．2000，24(2)：16—18．
[8] Kang S M，Leblebici Y．CMOS数字集成电路—分析与设计．北京：电子工业出版社，2005．
[9] Phillip E．A，Holberg D R．CMOS模拟集成电路设计．北京：电子工业出版社，2005．
[10] 李伟华．VLSI设计基础．北京：电子工业出版社，2002．
[11] Hodges D A，Jackson H G，Saleh R A．Analysis and Design of Digital Integrated Circuits．北京：清华大学出版社，2004．
[12] 孙肖子，张健康，张犁等．专用集成电路设计基础．西安：西安电子科技大学出版社，2003．
[13] 高保嘉．MOS VLSI分析与设计．北京：电子工业出版社，2002．
[14] 高明伦，张红莉，徐诺．一种基于比较器的新型片内上电复位电路的实现．中国集成电路．2004，(63)：31-35
[15] 赵忠文，曾峦，熊伟．LVDS技术分析和应用设计．装备指挥技术学院学报，2001，12(6)：89-93．
[16] Gray P R, Hurst P J, Lewis S H et al. hnalysis and design of analog integrated circuits. Beijing:Higher Education Pr., 2003.
[17] 毕查德·拉扎维．模拟CMOS集成电路设计．西安：西安交通大学出版社，2003．
[18] Chen M D, Martinez J S, Michael, Nix M, Robinson E. Low-Voltage Low-Power LVDS driver. IEEE Journal of Solie-State Circuit. 2005,40(2):472-479.
[19] Boni A, Pierazzi A, Vecchi D. LVDS I/O interface for Gb/s-per-pin operation in 0.35μm CMOS. IEEE Journal of Solid-State Circuits, 36, (4):706-711.
[20] Chow H C, Sheen W W. Low Power LVDS Circuit for Serial Data Communications. Proceeding of 2005 International Symposium on Intelligent Signal Processing and Communication Systems. HongKong. 2005:293-296.
[21] 韩雁．专用集成电路设计技术基础．成都：电子科技大学出版社，1999．
[22] Young B. An SOI CMOS LVDS driver and receiver pair. Digest of Technical Papers Of VLSI Circuits. 2001:153-154.
[23] Malcovati P,Maloberti F, Fiocchi C et al. Curature-compensated BiCMOS bandgap with 1-V supply voltage. IEEE Journal of Solid-State Circuits. 2001,36:1076-1081.
[24] Bult K, Govet J G M.A fast settling CMOS Amp for SC circuits with 90dB Gain. IEEE Journal of Solid Circuit. 1990,25(6):1169-1184.
[25] Wang C C, Huang J M, Huang J F. 1. OGbps LVDS Transceiver design for LCD panels. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits. 2004:236-239.
[26] 朱正涌．半导体集成电路．北京：清华大学出版社，2001．
[27] Hast ings A．The Art of Analog Layout．北京：清华大学出版社，2004．
[28] 马仲发，庄奕琪，杜磊等，一种敏感MOSFET ESD潜在损伤检测方法．半导体学报，2002，23(11)：1211-1216．
[29] 臧佳锋，薛忠杰．深亚微米CMOS IC全芯片ESD保护技术．电子与封装．2005，6(5)：20-30．
[30] 姚维连，孙伟锋，吴建辉．CMOS集成电路中电源和地之间的ESD保护电路设计．接地防护技术．2004，(5)：12-15．
[31] 邓永孝．半导体器件失效分析．北京：宇航出版社，1991．
[32] Su D. Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. IEEE J. of Solid-State Circuits, 1993, 28(4):420～430
[33] 李志坚，周润德．ULSI器件电路与系统．北京：科学出版社，2001．
[34] 赵天麟．关于LSI／VLSI的设计规则检查．微处理机．1998，(1)：11-14．
[35] 薛耀国，韩继国，冯金初等．硅栅CMOS电路版图设计规则检查全面性探讨．微电子学与计算机．1994，(4)：4-7．