高速电路设计及其在板级电路中的应用
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摘要
近年来随着电子系统朝着大规模、小体积、高速度的方向不断发展,基于传统的电路设计理论设计出来的电路越来越多的遇到了诸如信号完整性和电源完整性之类的问题,严重的甚至会导致系统无法工作。要适应当前电子系统的发展,光靠设计完成后的修修补补是远远不能解决问题的,而且成品后期解决问题耗费的成本,要数百倍于产品设计阶段解决问题的成本,必须从设计阶段就应用一整套的高速电路设计理论来指导电路板的设计。在这样的背景下,各种各样的高速电路设计理论应运而生。
高速电路首先要解决信号完整性问题。本文在理想的无损传输线的基础上,利用传输线理论,分析研究高速印刷电路板走线的信号特性,发现影响信号完整性的原因并找出解决常用的几种解决方法及各方法的优缺点。其中特意介绍了一种格形图的方法对信号的波形进行推算,并将推算波形和仿真波形进行对比。基于实际的有损传输线,本文还进一步研究了高速信号的传输特性,分析了直流损耗、趋肤效应,并且研究了PCB布线中常用的蛇行线、直角走线的影响。数字电路系统中普遍存在着串扰,这种串扰也存在于芯片内部、封装,PCB板内、板间,连接器、线缆间等。通过对板级串扰产生的原因及串扰对传输时间和信号完整性的影响研究,可以找到两种终端匹配方法有效抑制串扰的影响。电源完整性是高速电路板级设计需要注意的另一个方面,它可分为电源系统完整性、返回路径(通常是非理想的)和同步开关噪声三个密切相关的问题。本文依次分析了这三个问题,并给出了解决这三个问题的指导性意见。
In recent years,advances in photolithography and IC manufacturing technology, which drive Moore’s Law, means the features sizes on-chip will always decrease. This has an important impact. As the gate channel length decrease, the switching time of each gate will decrease. Shorter switching time means shorter rise time for the output drivers and higher clock frequencies possible. Nearly all signal integrity and power integrity problems get worse with shorter rise time. In the worst situation, these problems may lead to system collapse.
When we entered the 21st century, we entered a new era for electronic products. Shrinking design cycle times means the product must work the first time. We do not have the luxury of multiple build-it, test-it, re-design-it loops. If signal integrity and power integrity effects are not taken into account right at the beginning and designed out, products will fail. Many kinds of high-speed circuit design theories come into being in this background.
The theory of transmission line with no resistive losses is the base of high-speed circuit design in board-level. Signal characteristics must be analyzed in high-speed PCBs. And the reasons to effect signal integrity problems, the methods to solve them are also researched at the very start. Crosstalk exists in digital circuits extensively. That how digital times and signal integrity are influenced by crosstalk and the methods to reduce the crosstalk is discussed in the nest charter. In reality, there are DC losses, dielectric losses, and skin effect in nonideal transmission lines. These nonideal factors are analyzed in charter 4. Power integrity is another important problem in high-speed circuit design area. The effects such as system integrity, simultaneous switching noise and nonideal current return path that can devastate a digital design are researched in the last charter.
高速电路首先要解决信号完整性问题。本文在理想的无损传输线的基础上,利用传输线理论,分析研究高速印刷电路板走线的信号特性,发现影响信号完整性的原因并找出解决常用的几种解决方法及各方法的优缺点。其中特意介绍了一种格形图的方法对信号的波形进行推算,并将推算波形和仿真波形进行对比。基于实际的有损传输线,本文还进一步研究了高速信号的传输特性,分析了直流损耗、趋肤效应,并且研究了PCB布线中常用的蛇行线、直角走线的影响。数字电路系统中普遍存在着串扰,这种串扰也存在于芯片内部、封装,PCB板内、板间,连接器、线缆间等。通过对板级串扰产生的原因及串扰对传输时间和信号完整性的影响研究,可以找到两种终端匹配方法有效抑制串扰的影响。电源完整性是高速电路板级设计需要注意的另一个方面,它可分为电源系统完整性、返回路径(通常是非理想的)和同步开关噪声三个密切相关的问题。本文依次分析了这三个问题,并给出了解决这三个问题的指导性意见。
In recent years,advances in photolithography and IC manufacturing technology, which drive Moore’s Law, means the features sizes on-chip will always decrease. This has an important impact. As the gate channel length decrease, the switching time of each gate will decrease. Shorter switching time means shorter rise time for the output drivers and higher clock frequencies possible. Nearly all signal integrity and power integrity problems get worse with shorter rise time. In the worst situation, these problems may lead to system collapse.
When we entered the 21st century, we entered a new era for electronic products. Shrinking design cycle times means the product must work the first time. We do not have the luxury of multiple build-it, test-it, re-design-it loops. If signal integrity and power integrity effects are not taken into account right at the beginning and designed out, products will fail. Many kinds of high-speed circuit design theories come into being in this background.
The theory of transmission line with no resistive losses is the base of high-speed circuit design in board-level. Signal characteristics must be analyzed in high-speed PCBs. And the reasons to effect signal integrity problems, the methods to solve them are also researched at the very start. Crosstalk exists in digital circuits extensively. That how digital times and signal integrity are influenced by crosstalk and the methods to reduce the crosstalk is discussed in the nest charter. In reality, there are DC losses, dielectric losses, and skin effect in nonideal transmission lines. These nonideal factors are analyzed in charter 4. Power integrity is another important problem in high-speed circuit design area. The effects such as system integrity, simultaneous switching noise and nonideal current return path that can devastate a digital design are researched in the last charter.
引文
[1] Douglas Brooks,刘雷波,赵岩译. 信号完整性问题和印制电路板设计[M].北京:机械工业出版社,2005
[2] 曾峰,巩海洪,曾波. 印刷电路板(PCB)设计与制作[M].北京:电子工业出版社,2005
[3] Howard Johnson,Martin Graham,高沈立,朱来文译.高速数字设计[M].北京:电子工业出版社,2004
[4] Rasid M.D. 电力电子学——电路、器件及应用(英文版第 3 版) [M].北京:人民邮电出版社,2007
[5] Paul C R.,Derivation of Common Impedance Coupling from the Transmission-Line Equations [J].IEEE Trans EMC,,34(3):352-358,1992
[6] Douglas Brooks,刘雷波,赵岩译.信号完整性问题和印制电路板设计[M].北京:机械工业出版社,2005
[7] 张磊,雷震,刘海波,林哲辉.高速电路设计合信号完整性分析.电子技术应用,2001.6:70-73
[8] Brian Young.Digital Signal Integrity-Modeling and Simulation with Interconnects and Package[M].Prentice Hall PTR,2001
[9] 陈飞.PCB 高速数字设计中的阻抗控制[J] .电子产品世界,2003,4:13-15
[10] Eric Bogatin, 李玉山,李丽平等译.信号完整性分析[M].北京:电子工业出版社,2005
[11] 路宏敏.短传输线的串扰响应分析[J].西安交通大学学报,2000,34(6):31-23
[12] 周润景. Cadence 高速电路板设计与仿真[M].北京:电子工业出版社,2006
[13] 李莉,李卫兵.二平行传输线间的串扰分析[J].电波科学学报,2001,16(2):56-58
[14] 朱滔.信号完整性原则在高速设计中的应用[J].现代有线传输,2003.6:58-62
[15] 黄娟,朱红.高速电路的印制板仿真[J],今日电子,2003,(9):36-38
[16] 沃尔夫,现代 VLSI 电路设计:芯片系统设计(第 3 版)[M].北京:科学出版社,2003
[17] Mark I.Montrose, 刘元安译.电磁兼容和印刷电路板理论、设计和布线[M].北京:人民邮电出版社,2002
[18] Y. Chen, Z. Chen, Z. Wu, D. Xue and J. Fang. A New Approach to signal Integrity Analysis of High-Speed Packaging [C].IEEE 0 Topical Meeting on Electrical Performance of Electronic Packaging,Conference Proe., pp. Portland,Oregon, 235-238,Oct. 2-4, 1995
[19] 李勇明,曾孝平.高频 PCB 设计中出现的干扰分析及对策[J] .电子工艺技术,2003,24(1):25-28
[20] 李贵山,高速印刷电路板设计技术研究[J].电子元件与材料,2003,22(6):23-26
[21] Stephen H .Hall, Garrett W .Hall, James A .McCall. High-Speed Digital System Design- a Handbook of Interconnect Theory and Design Practices [M].John Wiley Sons, Inc .2000
[22] 久保寺忠,冯杰等译. 高速数字电路设计与安装技巧[M].北京:科学出版社,2006
[23] 张海风,HyperLynx 仿真与 PCB 设计[M].北京:机械工业出版社,2005
[24] Heb Ross. IBIS Models for Signal Integrity Applications[M]. Electrical Engineering Times. September 2,1996
[25] 刘晓彬,朱可安等. 印刷电路设计标准手册[M].北京:宇航出版社,1993
[26] William R. Blood Jr. ECL Systems Design Handbook[M]. Motorola Semiconductor Products fnc.,Mesa, AZ, (Fourth Edition) Chapters 3 and 7,May,1983
[27] 李峰.混和信号电路板抗干扰能力和电磁兼容性[J].制导与引信,2003,24(3):42—46
[28] Stephen H,Garrett W,Janes. A High speed Digital System Design[M].New York:Wiley Sons,2000
[29] 姜雪松. 印制电路板设计[M].北京:机械工业出版社,2006
[30] Matick,Richard E. Transmission Lines for Digital and Communication Networks[M]. McGraw-Hill,Inc. 1996
[31] Donald Telian. High-Performance System Design Conference .1997
[32] Floyd,T.L.,余璆改编. 数字电子技术(第九版)(英文改编版)[M].北京:电子工业出版社,2006
[33] 顾海洲,马双武. PCB 电磁兼容技术——设计实践[M] .北京:清华大学出版社,2004
[34] 谢金明,谭博,王瑞林.高速数字电路设计与噪声控制技术[M].北京:电子工业出版社,2003
[2] 曾峰,巩海洪,曾波. 印刷电路板(PCB)设计与制作[M].北京:电子工业出版社,2005
[3] Howard Johnson,Martin Graham,高沈立,朱来文译.高速数字设计[M].北京:电子工业出版社,2004
[4] Rasid M.D. 电力电子学——电路、器件及应用(英文版第 3 版) [M].北京:人民邮电出版社,2007
[5] Paul C R.,Derivation of Common Impedance Coupling from the Transmission-Line Equations [J].IEEE Trans EMC,,34(3):352-358,1992
[6] Douglas Brooks,刘雷波,赵岩译.信号完整性问题和印制电路板设计[M].北京:机械工业出版社,2005
[7] 张磊,雷震,刘海波,林哲辉.高速电路设计合信号完整性分析.电子技术应用,2001.6:70-73
[8] Brian Young.Digital Signal Integrity-Modeling and Simulation with Interconnects and Package[M].Prentice Hall PTR,2001
[9] 陈飞.PCB 高速数字设计中的阻抗控制[J] .电子产品世界,2003,4:13-15
[10] Eric Bogatin, 李玉山,李丽平等译.信号完整性分析[M].北京:电子工业出版社,2005
[11] 路宏敏.短传输线的串扰响应分析[J].西安交通大学学报,2000,34(6):31-23
[12] 周润景. Cadence 高速电路板设计与仿真[M].北京:电子工业出版社,2006
[13] 李莉,李卫兵.二平行传输线间的串扰分析[J].电波科学学报,2001,16(2):56-58
[14] 朱滔.信号完整性原则在高速设计中的应用[J].现代有线传输,2003.6:58-62
[15] 黄娟,朱红.高速电路的印制板仿真[J],今日电子,2003,(9):36-38
[16] 沃尔夫,现代 VLSI 电路设计:芯片系统设计(第 3 版)[M].北京:科学出版社,2003
[17] Mark I.Montrose, 刘元安译.电磁兼容和印刷电路板理论、设计和布线[M].北京:人民邮电出版社,2002
[18] Y. Chen, Z. Chen, Z. Wu, D. Xue and J. Fang. A New Approach to signal Integrity Analysis of High-Speed Packaging [C].IEEE 0 Topical Meeting on Electrical Performance of Electronic Packaging,Conference Proe., pp. Portland,Oregon, 235-238,Oct. 2-4, 1995
[19] 李勇明,曾孝平.高频 PCB 设计中出现的干扰分析及对策[J] .电子工艺技术,2003,24(1):25-28
[20] 李贵山,高速印刷电路板设计技术研究[J].电子元件与材料,2003,22(6):23-26
[21] Stephen H .Hall, Garrett W .Hall, James A .McCall. High-Speed Digital System Design- a Handbook of Interconnect Theory and Design Practices [M].John Wiley Sons, Inc .2000
[22] 久保寺忠,冯杰等译. 高速数字电路设计与安装技巧[M].北京:科学出版社,2006
[23] 张海风,HyperLynx 仿真与 PCB 设计[M].北京:机械工业出版社,2005
[24] Heb Ross. IBIS Models for Signal Integrity Applications[M]. Electrical Engineering Times. September 2,1996
[25] 刘晓彬,朱可安等. 印刷电路设计标准手册[M].北京:宇航出版社,1993
[26] William R. Blood Jr. ECL Systems Design Handbook[M]. Motorola Semiconductor Products fnc.,Mesa, AZ, (Fourth Edition) Chapters 3 and 7,May,1983
[27] 李峰.混和信号电路板抗干扰能力和电磁兼容性[J].制导与引信,2003,24(3):42—46
[28] Stephen H,Garrett W,Janes. A High speed Digital System Design[M].New York:Wiley Sons,2000
[29] 姜雪松. 印制电路板设计[M].北京:机械工业出版社,2006
[30] Matick,Richard E. Transmission Lines for Digital and Communication Networks[M]. McGraw-Hill,Inc. 1996
[31] Donald Telian. High-Performance System Design Conference .1997
[32] Floyd,T.L.,余璆改编. 数字电子技术(第九版)(英文改编版)[M].北京:电子工业出版社,2006
[33] 顾海洲,马双武. PCB 电磁兼容技术——设计实践[M] .北京:清华大学出版社,2004
[34] 谢金明,谭博,王瑞林.高速数字电路设计与噪声控制技术[M].北京:电子工业出版社,2003