双修正归一化最小和LDPC译码算法及其部分并行结构研究
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摘要
在通信系统中，信道中的噪声会使传输的数据产生错误。信道编码技术可以发现和纠正这些错误，使通信系统具有一定的抗干扰和纠错的能力。低密度奇偶校验码（Low Density Parity Check Codes, LDPC codes）在AWGN信道下的性能接近香农极限，是近年来信道编码领域研究的热点。目前虽然LDPC码的理论研究发展迅速，但是在实际应用中，在改进适于硬件实现的译码算法的性能、在译码器的复杂度与吞吐率之间寻求更好的折衷等方面仍然存在许多待解决的问题。
本文首先论述了国内外关于LDPC码的研究现状，接下来对LDPC码的译码算法、译码器电路设计中的运算电路、存储方案等关键问题进行了一系列的研究，最后设计并实现了一个WiMAX系统中码长为2304比特的LDPC码译码器。本文的主要贡献如下：
1.最小和算法中的校验节点运算是对和积算法的简化近似，因此每次运算都会存在误差，导致译码性能变差。归一化最小和算法从均值的角度对最小和算法的误差进行修正，使最小和算法的BER（Bit Error Rate）性能得到了改进。本文对归一化最小和算法进行了改进，提出了双修正归一化最小和（DualNormalized Min-Sum, DN-MS）算法，该算法在校验节点运算中采用两个归一化修正因子分别对最小值和次小值进行修正。改进的算法在不增加运算复杂度的条件下，获得比归一化最小和算法更好的BER性能。对基于仿真的定点化方法进行了改进，减少了仿真的工作量；
2.最小和及其改进算法中核心的运算为校验节点的最小—次小运算，并行的最小—次小运算单元可以在一个时钟周期内计算出一组数据中的最小值与次小值，但一般电路面积比较大。本文设计了两种最小—次小运算方法：第一种方法对极少比较排序法（Minimum-Comparison Sorting, XS）进行改进，称为MXS（Modified Minimum-Comparison Sorting）方法，该方法简化了次小值运算，运算电路具有较小的面积，但是电路延迟比较大；第二种方法为一种新的树形运算（New Tree Structure, NTS）方法，与MXS方法相比，该方法的电路面积有少量增加，但却可以大幅减小运算的延迟，NTS方法可以在运算速度与电路面积之间实现比较好的折衷；
3.采用并行运算单元的译码器可以具有比串行运算单元更高的吞吐率，采用分层迭代的译码器迭代收敛速度较快并且占用的存储资源较少。本文将并行运算单元和分层迭代方法相结合，设计了一种新的部分并行译码器结构，与其它部分并行译码器结构相比，该译码器可以在吞吐率和面积之间实现比较好的折衷，并且可以在更大的范围内自由设计译码器的吞吐率。在译码器中重点设计了数据的存储方案和并行DN-MS运算单元。在数据的存储方案设计中主要对数据的存储顺序、读写控制电路进行了设计和优化，使其即具有较大的带宽，又有效的降低了读写控制结构和互联结构的复杂度，同时避免了在读写过程中的冲突。在该译码器结构的基础上，针对校验矩阵具有准下三角阵形式的QC-LDPC码进行了预译码设计，使译码器可以在接收码字的过程中完成第一次迭代中一部分层的译码运算，从而进一步提高了译码器的吞吐率；
4.基于以上对译码算法、并行最小—次小运算电路和译码器结构设计的研究，设计并实现了一个WiMAX系统中码长为2304比特的部分并行QC-LDPC码译码器。在进行了FPGA原型机验证后对该译码器进行了逻辑综合。实验结果表明，该译码器在硬件复杂度和译码吞吐率之间实现了比较好的折衷。
In communication systems, the noise of the channel introduces errors to the trans-mitted data, and channel coding can detect and correct errors in the transmitted data, sochannel coding can increase the reliability of the communication system. Low densi-ty parity check codes (LDPC codes) have been shown to approach Shannon’s limit inAWGN channel, and it is one of the most attractive field in channel coding. Though thetechniques of LDPC codes develop fast, many problems are still need to be solved suchas improving the decoding performance of fixed-point algorithms and make good tradeofamong decoder’s complexity and throughput.
In this dissertation, we firstly give a review of research on LDPC. Based on that, wediscussed the topics around the decoding algorithm of LDPC code, parallel algorithms offinding the two smallest values and their hardware implementation, data packing schemein partial parallel decoders. Finally, a LDPC decoder is proposed which supports all themodes of2304bit LDPC codes in WiMAX. The main contributions of this dissertationare listed as following:
1. The check node processing in Min-Sum algorithm is an approximation to thatin Sum Product algorithm, so Min-Sum algorithm has a performance loss. NormalizedMin-Sum algorithm can force the mean of check node results in Min-Sum algorithm e-qual to the mean of check node results in BP algorithm, so it has better BER performancethan Min-Sum algorithm. In this paper, we proposed a dual normalized min-sum algo-rithm which uses two normalized factors to further improve the BER performance ofthe Min-Sum algorithm, and the proposed algorithm has the same decoding complexi-ty as normalized Min-Sum algorithm. Simulation based LDPC wordlength optimizationmethod is improved, and the workload of simulation is saved.
2. Algorithms of finding the two smallest values in a group are very important inMin-Sum and Min-Sum based algorithms. Parallel algorithms can find the two smallestvalues in one cycle, but they consume more chip size. Two parallel algorithms are pro-posed, one is the modified minimum-comparison sorting (MXS) approach, and the otheris new tree structure (NTS) approach. MXS approach simplifies the process of finding thesecond minimum value in minimum-comparison sorting approach, and it has the samecomputing latency as minimum-comparison sorting approach but has less hardware cost. NTS approach has a little increase in the complexity than MXS approach, but has muchless latency, so it makes good tradeof among the complexity and the speed.
3. LDPC decoder using parallel processing unit can achieve high throughput. Lay-ered decoding approach saves the size of the memory bank and has higher decoding con-vergence speed. A new partial parallel LDPC decoder structure is proposed using parallelprocessing unit and layered approach. Compared to others, the proposed structure sup-ports larger range of throughput, and makes good tradeof between the complexity andthe throughput. A parallel DN-MS computing unit is also designed based on NTS ap-proach. In the proposed decoder, a new packing scheme for posterior probability data ofvariable node is proposed: the memory bank has several RAMs, and every RAM has onereading alignment unit and one connecting network. The proposed packing scheme haslarge bandwidth without accessing conflict, and its control unit and connecting networkhas low complexity. A pre-decoding decoder is proposed for the QC-LDPC codes whosebase matrix is an approximate lower triangular matrix. The proposed decoder could startthe decoding process before it gets the whole code word’s channel messages, and itachieves a high throughput.
4. At last, a multi rate partial parallel QC-LDPC decoder is designed for all coderates of2304bit LDPC codes in WiMAX. At last, FPGA implementation results andlogic synthesis results are provided for the proposed decoder, and the results show thatthe decoder achieves a good tradeof between the complexity and the throughput.
本文首先论述了国内外关于LDPC码的研究现状，接下来对LDPC码的译码算法、译码器电路设计中的运算电路、存储方案等关键问题进行了一系列的研究，最后设计并实现了一个WiMAX系统中码长为2304比特的LDPC码译码器。本文的主要贡献如下：
1.最小和算法中的校验节点运算是对和积算法的简化近似，因此每次运算都会存在误差，导致译码性能变差。归一化最小和算法从均值的角度对最小和算法的误差进行修正，使最小和算法的BER（Bit Error Rate）性能得到了改进。本文对归一化最小和算法进行了改进，提出了双修正归一化最小和（DualNormalized Min-Sum, DN-MS）算法，该算法在校验节点运算中采用两个归一化修正因子分别对最小值和次小值进行修正。改进的算法在不增加运算复杂度的条件下，获得比归一化最小和算法更好的BER性能。对基于仿真的定点化方法进行了改进，减少了仿真的工作量；
2.最小和及其改进算法中核心的运算为校验节点的最小—次小运算，并行的最小—次小运算单元可以在一个时钟周期内计算出一组数据中的最小值与次小值，但一般电路面积比较大。本文设计了两种最小—次小运算方法：第一种方法对极少比较排序法（Minimum-Comparison Sorting, XS）进行改进，称为MXS（Modified Minimum-Comparison Sorting）方法，该方法简化了次小值运算，运算电路具有较小的面积，但是电路延迟比较大；第二种方法为一种新的树形运算（New Tree Structure, NTS）方法，与MXS方法相比，该方法的电路面积有少量增加，但却可以大幅减小运算的延迟，NTS方法可以在运算速度与电路面积之间实现比较好的折衷；
3.采用并行运算单元的译码器可以具有比串行运算单元更高的吞吐率，采用分层迭代的译码器迭代收敛速度较快并且占用的存储资源较少。本文将并行运算单元和分层迭代方法相结合，设计了一种新的部分并行译码器结构，与其它部分并行译码器结构相比，该译码器可以在吞吐率和面积之间实现比较好的折衷，并且可以在更大的范围内自由设计译码器的吞吐率。在译码器中重点设计了数据的存储方案和并行DN-MS运算单元。在数据的存储方案设计中主要对数据的存储顺序、读写控制电路进行了设计和优化，使其即具有较大的带宽，又有效的降低了读写控制结构和互联结构的复杂度，同时避免了在读写过程中的冲突。在该译码器结构的基础上，针对校验矩阵具有准下三角阵形式的QC-LDPC码进行了预译码设计，使译码器可以在接收码字的过程中完成第一次迭代中一部分层的译码运算，从而进一步提高了译码器的吞吐率；
4.基于以上对译码算法、并行最小—次小运算电路和译码器结构设计的研究，设计并实现了一个WiMAX系统中码长为2304比特的部分并行QC-LDPC码译码器。在进行了FPGA原型机验证后对该译码器进行了逻辑综合。实验结果表明，该译码器在硬件复杂度和译码吞吐率之间实现了比较好的折衷。
In communication systems, the noise of the channel introduces errors to the trans-mitted data, and channel coding can detect and correct errors in the transmitted data, sochannel coding can increase the reliability of the communication system. Low densi-ty parity check codes (LDPC codes) have been shown to approach Shannon’s limit inAWGN channel, and it is one of the most attractive field in channel coding. Though thetechniques of LDPC codes develop fast, many problems are still need to be solved suchas improving the decoding performance of fixed-point algorithms and make good tradeofamong decoder’s complexity and throughput.
In this dissertation, we firstly give a review of research on LDPC. Based on that, wediscussed the topics around the decoding algorithm of LDPC code, parallel algorithms offinding the two smallest values and their hardware implementation, data packing schemein partial parallel decoders. Finally, a LDPC decoder is proposed which supports all themodes of2304bit LDPC codes in WiMAX. The main contributions of this dissertationare listed as following:
1. The check node processing in Min-Sum algorithm is an approximation to thatin Sum Product algorithm, so Min-Sum algorithm has a performance loss. NormalizedMin-Sum algorithm can force the mean of check node results in Min-Sum algorithm e-qual to the mean of check node results in BP algorithm, so it has better BER performancethan Min-Sum algorithm. In this paper, we proposed a dual normalized min-sum algo-rithm which uses two normalized factors to further improve the BER performance ofthe Min-Sum algorithm, and the proposed algorithm has the same decoding complexi-ty as normalized Min-Sum algorithm. Simulation based LDPC wordlength optimizationmethod is improved, and the workload of simulation is saved.
2. Algorithms of finding the two smallest values in a group are very important inMin-Sum and Min-Sum based algorithms. Parallel algorithms can find the two smallestvalues in one cycle, but they consume more chip size. Two parallel algorithms are pro-posed, one is the modified minimum-comparison sorting (MXS) approach, and the otheris new tree structure (NTS) approach. MXS approach simplifies the process of finding thesecond minimum value in minimum-comparison sorting approach, and it has the samecomputing latency as minimum-comparison sorting approach but has less hardware cost. NTS approach has a little increase in the complexity than MXS approach, but has muchless latency, so it makes good tradeof among the complexity and the speed.
3. LDPC decoder using parallel processing unit can achieve high throughput. Lay-ered decoding approach saves the size of the memory bank and has higher decoding con-vergence speed. A new partial parallel LDPC decoder structure is proposed using parallelprocessing unit and layered approach. Compared to others, the proposed structure sup-ports larger range of throughput, and makes good tradeof between the complexity andthe throughput. A parallel DN-MS computing unit is also designed based on NTS ap-proach. In the proposed decoder, a new packing scheme for posterior probability data ofvariable node is proposed: the memory bank has several RAMs, and every RAM has onereading alignment unit and one connecting network. The proposed packing scheme haslarge bandwidth without accessing conflict, and its control unit and connecting networkhas low complexity. A pre-decoding decoder is proposed for the QC-LDPC codes whosebase matrix is an approximate lower triangular matrix. The proposed decoder could startthe decoding process before it gets the whole code word’s channel messages, and itachieves a high throughput.
4. At last, a multi rate partial parallel QC-LDPC decoder is designed for all coderates of2304bit LDPC codes in WiMAX. At last, FPGA implementation results andlogic synthesis results are provided for the proposed decoder, and the results show thatthe decoder achieves a good tradeof between the complexity and the throughput.
引文
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