宽带ISAR实时干扰技术及实现
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摘要
目前逆合成孔径雷达(ISAR)成像在军事中的应用日显突出,它是目标分类与识别、精确制导等方面重要的手段,在未来防空和导弹防御领域中具有十分重要的作用。针对逆合成孔径雷达的干扰也成为电子对抗领域的一个热点问题。本文研究了基于数字图像合成的ISAR欺骗性干扰,设计了基于该方法的硬件处理系统。并在该系统平台上完成了DSP、FPGA软件。本文研究工作主要有:
分析了ISAR成像原理及算法流程,对目前ISAR的各种干扰方式进行了比较研究。论文首先介绍了几种噪声干扰方法,然后重点分析了基于数字图像合成(DIS)的ISAR欺骗性干扰技术,并给出了假目标ISAR成像的计算机仿真结果。详细研究了基于DIS的ISAR干扰机结构和特点,分析了各系统参数的量化位数,选取合适的硬件处理器完成相应运算,对各部分计算进行硬件编程实现。
提出了一种实时ISAR欺骗性干扰系统结构,设计并完成了ISAR成像欺骗性干扰的高速信号处理系统。该处理系统采用DSP+FPGA的结构,目标特性调制信息的生成主要由DSP完成,FPGA实现干扰目标特性信息在雷达信号上的调制,从而协同进行ISAR欺骗性干扰。本系统具有较强的计算和数据通信能力以及灵活的并行算法处理架构。实验结果证明本系统可以实现对宽带雷达的实时ISAR欺骗性干扰。
At present, Inverse Synthetic Aperture Radar (ISAR) imaging capability plays an important role in military applications, such as target classification, recognition and accurate weapon navigation. Jamming for ISAR is a hot topic in the field of electronic countermeasures. This paper focus on the method of deception jamming based on digital image synthesis (DIS). In allusion to the practicality method, the hardware system is designed. Deception jamming based on DIS is realized on the platform. The main works researched in this paper are as follows:
The basic principle of ISAR imaging and the processing flow of imaging algorithms are analyzed. Firstly, several methods of noise jamming are analyzed. Then, deception jamming based on DIS is analyzed and the simulation result of the false target image is given.
The structure and characteristics of ISAR jammer based on DIS are described in detail, and then the resolutions of system parameters are analyzed. In allusion to the characteristics of the method, we adopt processors which are fixable to the method and realize the method on the emulation mode of the hardware.
A real-time ISAR deception jamming system is proposed; the high-speed signal processing board are designed and implemented. The system adopts the structure of DSP+FPGA, in which DSP generates the modulation parameters of target characteristic and FPGA modulate the radar echo based on modulation parameters. The system is powerful on computing and data communication along with the convenient parallel arithmetic processing structure. Experimental results show that the system can achieve real-time ISAR deception jamming.
分析了ISAR成像原理及算法流程,对目前ISAR的各种干扰方式进行了比较研究。论文首先介绍了几种噪声干扰方法,然后重点分析了基于数字图像合成(DIS)的ISAR欺骗性干扰技术,并给出了假目标ISAR成像的计算机仿真结果。详细研究了基于DIS的ISAR干扰机结构和特点,分析了各系统参数的量化位数,选取合适的硬件处理器完成相应运算,对各部分计算进行硬件编程实现。
提出了一种实时ISAR欺骗性干扰系统结构,设计并完成了ISAR成像欺骗性干扰的高速信号处理系统。该处理系统采用DSP+FPGA的结构,目标特性调制信息的生成主要由DSP完成,FPGA实现干扰目标特性信息在雷达信号上的调制,从而协同进行ISAR欺骗性干扰。本系统具有较强的计算和数据通信能力以及灵活的并行算法处理架构。实验结果证明本系统可以实现对宽带雷达的实时ISAR欺骗性干扰。
At present, Inverse Synthetic Aperture Radar (ISAR) imaging capability plays an important role in military applications, such as target classification, recognition and accurate weapon navigation. Jamming for ISAR is a hot topic in the field of electronic countermeasures. This paper focus on the method of deception jamming based on digital image synthesis (DIS). In allusion to the practicality method, the hardware system is designed. Deception jamming based on DIS is realized on the platform. The main works researched in this paper are as follows:
The basic principle of ISAR imaging and the processing flow of imaging algorithms are analyzed. Firstly, several methods of noise jamming are analyzed. Then, deception jamming based on DIS is analyzed and the simulation result of the false target image is given.
The structure and characteristics of ISAR jammer based on DIS are described in detail, and then the resolutions of system parameters are analyzed. In allusion to the characteristics of the method, we adopt processors which are fixable to the method and realize the method on the emulation mode of the hardware.
A real-time ISAR deception jamming system is proposed; the high-speed signal processing board are designed and implemented. The system adopts the structure of DSP+FPGA, in which DSP generates the modulation parameters of target characteristic and FPGA modulate the radar echo based on modulation parameters. The system is powerful on computing and data communication along with the convenient parallel arithmetic processing structure. Experimental results show that the system can achieve real-time ISAR deception jamming.
引文
[1]刘永坦等著,雷达成像技术[M],哈尔滨:哈尔滨工业大学出版社, 2001
[2]冯德军,王雪松,肖顺平,王国玉.空间目标ISAR成像与识别对抗研究[J].系统工程与电子技术, 2005, 27 (1) : 43-45, 96.
[3]李源,刘建新,蔡英武.逆合成孔径雷达的干扰仿真[J].电子科技大学学报. 2006, 35 (1) : 9-12.
[4]甘建超,张德山,肖先赐.基于混沌相干调制的逆合成孔径雷达干扰技术[J].电子信息对抗技术. 2007, 21 (4) : 3-6, 10.
[5]李源,刘建新,陈惠连.基于正弦调相的ISAR干扰方法[J].信号处理. 2007, 23 (1) :101-105.
[6] P. Leducq, T.Landeau, P. Le Traon, et al. A Method to insert objects in a polarimetric SAR signal[C]. International Conference on Radar Systems, 2004.
[7] R.T. Ekestorm, C. Karow, "An All-Digital Image Synthesizer for Countering High-Resolution Imaging Radars", Master's thesis, Naval Postgraduate School, Monterey, 2000.
[8] P. E. Pace, D. J. Fouts, S. Ekestorm, etc. Digital false-target image synthesizer for countering ISAR[J]. IEE Proc. Radar Sonar Navig, 2002,149 (5) : 248– 257.
[9]邵兆宇.逆合成孔径雷达干扰技术研究[M].西安:西安电子科技大学, 2004.
[10] LI Yuan, Lv Gaohuan, Chen Huilian, A New Technology of Multi-false Targets Deception against Chirp Waveform Inverse Synthetic Aperture Radar[C]. The 9th International Conference on Signal Processing Proceedings, 2008, 2477-2480.
[11]李源,陈惠连.基于图像合成的ISAR欺骗干扰研究[J].现代雷达.2007,29(3):56-58
[12]李源,陈惠连.逆合成孔径雷达多假目标欺骗干扰研究[J].信息与电子工程.2008,6(6):405-408
[13]李源,陈惠连.用于欺骗的多两假目标合成技术研究[J].信号处理.2008,24(5):725-729
[14]保铮,邢孟道,王彤编著,雷达成像技术[M],北京:电子工业出版社, 2005
[15]黄雅静,非匀速旋转目标ISAR成像技术研究,硕士学位论文[D],长沙:国防科技大学,2008
[16]南航ISAR科研组,逆合成孔径雷达信号处理技术技术总结,1991
[17]王根原、保铮,逆合成孔径雷达运动补偿中包络对齐的新方法,电子学报,1998 .6
[18]董创业,基于DRFM的雷达干扰技术研究,硕士学位论文[D],西安:西安电子科技大学,2007
[19]富雷雷,基于数字射频存储器的干扰调制研究,硕士学位论文[D],成都:电子科技大学,2007
[20]赵国庆.雷达对抗原理[M].西安:西安电子科技大学出版社,1999.
[21]崔瑞,薛磊. ISAR压制式干扰仿真及效果评估[J].计算机仿真. 2008, 25 (3) : 9-11.
[22]马俊霞,蔡英武,陈惠连.SAR压制式干扰仿真及效果评估[J].信息与电子工程. 2004, 2 (2) : 109-112.
[23]曹爱华,雷达有源干扰技术研究,硕士学位论文[D],成都:电子科技大学,2009
[24]王影,赵国庆.基于幅相量化的数字射频存储技术[J].电子科技. 2005, 4 (187) :24-27.
[25]王影,基于幅相量化的DRFM技术研究,硕士学位论文[D],西安:西安电子科技大学,2005
[26] Xilinx Corp. LogiCORE IP Block Memory Generator v4.3[EB/OL], 2010
[27]夏宇闻等著, Verilog数字系统设计教程[M],北京航空航天大学出版社, 2003
[28]田耘,徐文波等著, Xilinx FPGA开发实用教程[M],清华大学出版社, 2008
[29] Xilinx Corp. LogiCORE IP Adder/Subtracter v11.0 [EB/OL], 2010
[30] Xilinx Corp. Virtex-6 Family Overview [EB/OL], 2010
[31]李蛟,基于多DSP并行系统的SAR干扰技术研究,硕士学位论文[D],长沙:国防科学技术大学,2010
[32] ADSP TS201 Tiger SHARC Processor Hardware Reference Analog Device, Inc. 2004
[33]魏圣楠, 1.5Gsps高速数据采集系统的设计.硕士学位论文[D],成都:电子科技大学,2009
[34] ADC08D1500 Data Sheet.National Semiconductor.Inc,October 2005
[35]余能顺,基于PXI Express总线的高速数字信号中和器设计与实现,硕士学位论文[D],长沙:国防科学技术大学,2009
[36] AD9736 Data Sheet.Analog Devices.Inc,2004
[37] National Semiconductor Corp. LMX2346/LM2347 PLLatinum Frequency Synthesizer for RF Personal Communications[EB/OL], 2004
[38]陈长林,超高速数据采集与实时处理系统的设计与实现,硕士学位论文[D],长沙:国防科学技术大学,2010
[39]刘书明等著, ADSP TS20XS系列DSP原理与应用设计[M],北京:电子工业出版社, 2006
[40]与非网. ADSP TS201链路口通信的FPGA实现[J]. www.eefocus.com.2009.5
[41] Xilinx Corp. xapp635-Interfacing Virtex-II Series FPGAs with Analog Devices TigerSHARC TS20x DSPs via LVDS Link Ports[EB/OL], 2005
[42] PCI9656 Data Sheet.PLX Technology.Inc,March 2003
[43] PCI9054 Data Sheet.PLX Technology.Inc,March 2003
[44] PLX SDK User’s Manual v5.10.PLX Technology.Inc,June 2007
[45] PLX SDK PLX9000 Legacy API Reference Manual v5.0.PLX Technology.Inc,June 2007
[46]李海强,邱兆坤.基于CPCI总线的多片ADSP-TS201引导设计[J].现代电子技术.2011,34(17):25-27
[47]王瑞君,高速目标实时ISAR成像系统设计与实现,硕士学位论文[D],长沙:国防科学技术大学,2010
[48]曾跃,欺骗式ISAR干扰技术研究,硕士学位论文[D],长沙:国防科学技术大学,2010
[49]黄雅静,非匀速旋转目标ISAR成像技术研究,硕士学位论文[D],长沙:国防科学技术大学,2008
[50]张兴敢,逆合成孔径雷达成像及目标识别[D],博士学位论文,南京:南京航空航天大学,2001
[51]李蛟,杨进,邱兆坤;基于ADSP-TS201S的多DSP并行系统设计[J],现代电子技术.2010,34(17):30-35
[52]魏云斐;张遂南;ADSP TS201链路口通信的FPGA实现[J],现代电子技术.2009-02-01
[2]冯德军,王雪松,肖顺平,王国玉.空间目标ISAR成像与识别对抗研究[J].系统工程与电子技术, 2005, 27 (1) : 43-45, 96.
[3]李源,刘建新,蔡英武.逆合成孔径雷达的干扰仿真[J].电子科技大学学报. 2006, 35 (1) : 9-12.
[4]甘建超,张德山,肖先赐.基于混沌相干调制的逆合成孔径雷达干扰技术[J].电子信息对抗技术. 2007, 21 (4) : 3-6, 10.
[5]李源,刘建新,陈惠连.基于正弦调相的ISAR干扰方法[J].信号处理. 2007, 23 (1) :101-105.
[6] P. Leducq, T.Landeau, P. Le Traon, et al. A Method to insert objects in a polarimetric SAR signal[C]. International Conference on Radar Systems, 2004.
[7] R.T. Ekestorm, C. Karow, "An All-Digital Image Synthesizer for Countering High-Resolution Imaging Radars", Master's thesis, Naval Postgraduate School, Monterey, 2000.
[8] P. E. Pace, D. J. Fouts, S. Ekestorm, etc. Digital false-target image synthesizer for countering ISAR[J]. IEE Proc. Radar Sonar Navig, 2002,149 (5) : 248– 257.
[9]邵兆宇.逆合成孔径雷达干扰技术研究[M].西安:西安电子科技大学, 2004.
[10] LI Yuan, Lv Gaohuan, Chen Huilian, A New Technology of Multi-false Targets Deception against Chirp Waveform Inverse Synthetic Aperture Radar[C]. The 9th International Conference on Signal Processing Proceedings, 2008, 2477-2480.
[11]李源,陈惠连.基于图像合成的ISAR欺骗干扰研究[J].现代雷达.2007,29(3):56-58
[12]李源,陈惠连.逆合成孔径雷达多假目标欺骗干扰研究[J].信息与电子工程.2008,6(6):405-408
[13]李源,陈惠连.用于欺骗的多两假目标合成技术研究[J].信号处理.2008,24(5):725-729
[14]保铮,邢孟道,王彤编著,雷达成像技术[M],北京:电子工业出版社, 2005
[15]黄雅静,非匀速旋转目标ISAR成像技术研究,硕士学位论文[D],长沙:国防科技大学,2008
[16]南航ISAR科研组,逆合成孔径雷达信号处理技术技术总结,1991
[17]王根原、保铮,逆合成孔径雷达运动补偿中包络对齐的新方法,电子学报,1998 .6
[18]董创业,基于DRFM的雷达干扰技术研究,硕士学位论文[D],西安:西安电子科技大学,2007
[19]富雷雷,基于数字射频存储器的干扰调制研究,硕士学位论文[D],成都:电子科技大学,2007
[20]赵国庆.雷达对抗原理[M].西安:西安电子科技大学出版社,1999.
[21]崔瑞,薛磊. ISAR压制式干扰仿真及效果评估[J].计算机仿真. 2008, 25 (3) : 9-11.
[22]马俊霞,蔡英武,陈惠连.SAR压制式干扰仿真及效果评估[J].信息与电子工程. 2004, 2 (2) : 109-112.
[23]曹爱华,雷达有源干扰技术研究,硕士学位论文[D],成都:电子科技大学,2009
[24]王影,赵国庆.基于幅相量化的数字射频存储技术[J].电子科技. 2005, 4 (187) :24-27.
[25]王影,基于幅相量化的DRFM技术研究,硕士学位论文[D],西安:西安电子科技大学,2005
[26] Xilinx Corp. LogiCORE IP Block Memory Generator v4.3[EB/OL], 2010
[27]夏宇闻等著, Verilog数字系统设计教程[M],北京航空航天大学出版社, 2003
[28]田耘,徐文波等著, Xilinx FPGA开发实用教程[M],清华大学出版社, 2008
[29] Xilinx Corp. LogiCORE IP Adder/Subtracter v11.0 [EB/OL], 2010
[30] Xilinx Corp. Virtex-6 Family Overview [EB/OL], 2010
[31]李蛟,基于多DSP并行系统的SAR干扰技术研究,硕士学位论文[D],长沙:国防科学技术大学,2010
[32] ADSP TS201 Tiger SHARC Processor Hardware Reference Analog Device, Inc. 2004
[33]魏圣楠, 1.5Gsps高速数据采集系统的设计.硕士学位论文[D],成都:电子科技大学,2009
[34] ADC08D1500 Data Sheet.National Semiconductor.Inc,October 2005
[35]余能顺,基于PXI Express总线的高速数字信号中和器设计与实现,硕士学位论文[D],长沙:国防科学技术大学,2009
[36] AD9736 Data Sheet.Analog Devices.Inc,2004
[37] National Semiconductor Corp. LMX2346/LM2347 PLLatinum Frequency Synthesizer for RF Personal Communications[EB/OL], 2004
[38]陈长林,超高速数据采集与实时处理系统的设计与实现,硕士学位论文[D],长沙:国防科学技术大学,2010
[39]刘书明等著, ADSP TS20XS系列DSP原理与应用设计[M],北京:电子工业出版社, 2006
[40]与非网. ADSP TS201链路口通信的FPGA实现[J]. www.eefocus.com.2009.5
[41] Xilinx Corp. xapp635-Interfacing Virtex-II Series FPGAs with Analog Devices TigerSHARC TS20x DSPs via LVDS Link Ports[EB/OL], 2005
[42] PCI9656 Data Sheet.PLX Technology.Inc,March 2003
[43] PCI9054 Data Sheet.PLX Technology.Inc,March 2003
[44] PLX SDK User’s Manual v5.10.PLX Technology.Inc,June 2007
[45] PLX SDK PLX9000 Legacy API Reference Manual v5.0.PLX Technology.Inc,June 2007
[46]李海强,邱兆坤.基于CPCI总线的多片ADSP-TS201引导设计[J].现代电子技术.2011,34(17):25-27
[47]王瑞君,高速目标实时ISAR成像系统设计与实现,硕士学位论文[D],长沙:国防科学技术大学,2010
[48]曾跃,欺骗式ISAR干扰技术研究,硕士学位论文[D],长沙:国防科学技术大学,2010
[49]黄雅静,非匀速旋转目标ISAR成像技术研究,硕士学位论文[D],长沙:国防科学技术大学,2008
[50]张兴敢,逆合成孔径雷达成像及目标识别[D],博士学位论文,南京:南京航空航天大学,2001
[51]李蛟,杨进,邱兆坤;基于ADSP-TS201S的多DSP并行系统设计[J],现代电子技术.2010,34(17):30-35
[52]魏云斐;张遂南;ADSP TS201链路口通信的FPGA实现[J],现代电子技术.2009-02-01