片上网络拓扑结构研究和交换节点设计
摘要
随着半导体技术、设计技术的飞速发展,可以在单个芯片上集成多个IP模块。在单个芯片上,由于被集成的IP模块数量的不断增多,IP模块间的通信量就不断的增大,导致基于总线结构的片上系统设计方法将逐渐无法满足系统通信性能的要求。为了解决这些问题,类似于计算机网络通信的片上网络技术被提了出来,并成了当前的研究热点。
片上网络技术主要体现在通信拓扑结构和路由技术两个方面,而路由技术又具体包含交换技术和路由算法。这些技术决定了片上网络中交换节点的功能和结构,因此,交换节点对片上网络IP模块间的通信起着非常重要的作用。本文的主要工作就是研究片上网络的拓扑结构和路由技术,并设计了交换节点。
本文首先详细分析了片上网络的多种拓扑结构,指出它们的优点和不足,同时总结出拓扑结构的性能参数。在分析了交换技术和经典路由算法之后,针对簇网状拓扑结构,结合码分多址技术和确定性XY路由技术,提出了一种路由算法,并给出了该算法的详细流程。经过对扩展星型拓扑结构研究分析之后,决定在该拓扑结构上采用码分多址技术进行通信,本文采用其作为交换节点设计的基础。
最后,设计了基于扩展星型拓扑结构、码分多址路由技术的交换节点。分析了调制和解调算法,阐述了各个模块的设计细节,给出了各个模块的仿真结果,证明了设计的正确性,同时,给出了关于平均吞吐量和平均延迟的仿真数据。
With rapid development of semiconductor technology and design technology, the technology which integrates IP modules on a single chip is becoming more and more mature. As the increasing number of IP modules and frequency of communication on one chip, traditional SoC design methodology which is based on buses will not meet the requirement of the system communication performance. In order to solve these problems, NoC technology which likes the computer network was proposed, and the research about NoC becomes a hotspot now.
The technology of NoC is characterized by two factors, the communication network topology and the routing technique. The routing technique includes routing algorithm and switch technique. These factors determine the function and architecture of the switch, so that the switch plays a important role on the communication of IP modules on one chip. In this thesis, we mainly research the NoC topology and routing technique, then follow the content of design the switch.
In this paper, we research many NoC topologies in detail and point out the advantages and shortcomings of each topology and summarize their performance parameters. After studying the switch technique and classic routing algorithms, we combine CDMA technique with deterministic XY routing technique, then design a new routing algorithm for the cluster mesh topology, and describe the algorithm in detail. Through studying extended star topology and comparing with other topologies, we determine that all IP modules communicate with each other by CDMA technique on this topology, the topology becomes the basis for design of switch in this paper.
Finally, we design a switch based on extended star topology and CDMA technique. After analyzing modulation algorithm and demodulation algorithm, we give the design details of each module and the results of simulation, the simulation results prove the correctness of the design. At the same time,we show the simulation data of the average throughput and the average delay.
片上网络技术主要体现在通信拓扑结构和路由技术两个方面,而路由技术又具体包含交换技术和路由算法。这些技术决定了片上网络中交换节点的功能和结构,因此,交换节点对片上网络IP模块间的通信起着非常重要的作用。本文的主要工作就是研究片上网络的拓扑结构和路由技术,并设计了交换节点。
本文首先详细分析了片上网络的多种拓扑结构,指出它们的优点和不足,同时总结出拓扑结构的性能参数。在分析了交换技术和经典路由算法之后,针对簇网状拓扑结构,结合码分多址技术和确定性XY路由技术,提出了一种路由算法,并给出了该算法的详细流程。经过对扩展星型拓扑结构研究分析之后,决定在该拓扑结构上采用码分多址技术进行通信,本文采用其作为交换节点设计的基础。
最后,设计了基于扩展星型拓扑结构、码分多址路由技术的交换节点。分析了调制和解调算法,阐述了各个模块的设计细节,给出了各个模块的仿真结果,证明了设计的正确性,同时,给出了关于平均吞吐量和平均延迟的仿真数据。
With rapid development of semiconductor technology and design technology, the technology which integrates IP modules on a single chip is becoming more and more mature. As the increasing number of IP modules and frequency of communication on one chip, traditional SoC design methodology which is based on buses will not meet the requirement of the system communication performance. In order to solve these problems, NoC technology which likes the computer network was proposed, and the research about NoC becomes a hotspot now.
The technology of NoC is characterized by two factors, the communication network topology and the routing technique. The routing technique includes routing algorithm and switch technique. These factors determine the function and architecture of the switch, so that the switch plays a important role on the communication of IP modules on one chip. In this thesis, we mainly research the NoC topology and routing technique, then follow the content of design the switch.
In this paper, we research many NoC topologies in detail and point out the advantages and shortcomings of each topology and summarize their performance parameters. After studying the switch technique and classic routing algorithms, we combine CDMA technique with deterministic XY routing technique, then design a new routing algorithm for the cluster mesh topology, and describe the algorithm in detail. Through studying extended star topology and comparing with other topologies, we determine that all IP modules communicate with each other by CDMA technique on this topology, the topology becomes the basis for design of switch in this paper.
Finally, we design a switch based on extended star topology and CDMA technique. After analyzing modulation algorithm and demodulation algorithm, we give the design details of each module and the results of simulation, the simulation results prove the correctness of the design. At the same time,we show the simulation data of the average throughput and the average delay.
引文
[1]Axel Jantsch, Hannu Tenhunen. Network on Chip [M]. Academic Publishers, June 2003,6.
[2]Semiconductor Industry Association.International Technology Roadmap for Semiconductors 2003 Edition Executive Summary,2003.
[3]W B Toms. Synthesis of Quasi-Delay-Insensitive Datapath Circuits. A thesis submitted to the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Science & Engineering,2006.
[4]L. Benini and G De Micheli. Network on chip:a new SoC paradigm [J], IEEE Computer, vol.35, no.1, Jan,2002.
[5]Tobias Bjerregaard, Shankar Mahadevan. "A Survey of Research and Practices of Network-on-Chip", ACM Computing Surveys, Vol.38, Issue 1,2006.
[6]Axel Jantsch, Johnny Qberg, Hannu Tenhunen. "Special issue on networks on chip ". Journal of Systems Architecure, February 2004, pp.61-63.
[7]Coppola M, Curaba S, OCCN:a network-on-chip modeling and simulation framework[C]. Proc. of the Design Automation and Test in Europe Conference and Exhibition,2004,3:174-179.
[8]Bertozzi D and Benini L. Xpipes:a network-on-chip architecture for gigascale systems-on-chip[J]. IEEE, Circuits and Systems Magazine,2004,4(2):18-31.
[9]Benini L and De Micheli G.. Networks on chip:a new paradigm for systems on chip design[C]. Proc. of the Design Automation and Test in Europe Conference and Exhibition,2002:418-419.
[10]荆元利,樊晓桠.网络互连多线程处理器[J].计算机工程与应用,2005,41(33)：51-53,78.
[11]荆元利.基于片上网络的系统芯片的研究[D].西安,西北工业大学.2005.
[12]周文彪,张岩,毛志刚.片上网络的低功耗自适应数据保护[J].计算机工程,2006,32(22)：28-30.
[13]周干民..NoC基础研究[D].合肥：合肥工业大学博士学位论文.2005.
[14]高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4)：416-466.
[15]David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza. "Architecture of the Scalable Communications Core's Network on Chip" IEEE Micro, vol.27, no.5, pp.62-74, Sep./Oct.2007.
[16]Antonio Pullini, Fedefico Angiolini, PaoloMeloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini. "NoC Design and Implementation in 65nm Technology" NoCs, PP.273-282, First International Symposium on Networks-on-Chip(NOCS'07),2007.
[17]Siebenborn A, Bringmann O and Rosenstiel W. Communication analysis for network-on-chip design[C]. International Conf. on Parallel Computing in Electrical Engineering,2004:315-320.
[18]Carara E, Mello A and Moraes F. Communication models in Networks-on-chip[C]. The 18th IEEE/IFIP International Workshop on Rapid System Prototyping,2007:57-60.
[19]SystemC homepage.http://www.systemc.org.
[20]SystemC version 2.0 User's Guide.
[21]徐宁仪,冷祥纶,周祖成.基于SystemC的支持异源通信实体的NoC仿真架构.半导体技术,2006,31(3)：305-309.
[22]徐宁仪,陈曦.SystemC片上系统设计.北京：科学出版社,2004.
[23]D.C.Blank and J. Donovan. SystemC:From The Ground Up.Eclectic Ally,2004.
[24]T.Grotker, S.Liao, G. Martin and S. Swan. System Design with SystemC. Kluwer Academic Publishers,2002.
[25]Soheil Samii. "Modeling and Simulation with SystemC", Dept. of Computer and Information Science,2007.
[26]Axel Jantsch. NoC Architecture. ESSCIRC. September 2001.
[27]Y Liu. Power-Efficient Embedded Processing. A thesis submitted the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Engineering and Physical Sciences, School of Computer Science,2005.
[28]S. Kumar et al. A Network on Chip Architecture and Design Methodology [A], IEEE Computer Society Annual Symposium on VLSI(ISVLSI'02)[C]. April 2002:105-124.
[29]C. A. Zeferino and A. A. Susin, SoCIN:a parametric and scalable network-on-chip[C], in Proc.16th Symposium on Integrated Circuits and System Design, pp.169-174, September 2003.
[30]W. J. Dally and B. Towles, Route Packets, Not Wires:On-Chip Interconnection Networks[C]. In Proc. Design Automation Conference, pp.684-689, June 2001.
[31]Resve Saleh, Steve Wilton, Mirabbasi. System-on-chip:reuse and integration[C]. Proceedings of the IEEE, Vol.94, no.6, June 2006.
[32]W. J. Dally and C.L.Seitz, "The Torus Routing Chip", Technical Report 5208: TR:86.Computer Science Dept., California Inst. of Technology, pp.1-19,1986.
[33]F. Karim et al. "An Interconnet Architecture for Networking Systems on Chips ", IEEE Micro, vol.22, no.5, pp.36-45, Oct.2002.
[34]Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia et al. Spidergon:a novel on-chip communication network, System-on-Chip,2004. Proceedings.2004 International Symposium on, pp.15-18, Nov.2004.
[35]M Dehyadgari, M Nickray, A Afzali-kusha, et al. Evaluation of pseudo adaptive XY routing using an object oriented model for NoC. The 17th International Conference on Microelectronics,2005.
[36]Tobias Bjerregaard and Shankar Mahadevan. "A Survey of Research and Practices of Network-on-Chip", ACM Computing Surveys, Vol.38:19-27, Issue 1,2006.
[37]J. M. Pavia. Design and implementation of a fat tree network on chip [D]. Master's thesis, Institute of Microelectronics and Information Technology, Royal Institute of Technology(KTH), Stockholm, Swedem, June 2004.
[38]Adriahantenaina.A., Charlery.H., Greiner, A.et al. SPIN:a scalable, packet switched, on-chip micro-network[D]. Design Automation and Test in Europe Conference and Exhibition,2003, pp.70-73.
[39]P. P. Pande, C. Grecu, A. Ivanov, R. Saleh. Design of a Switch for Network on Chip Applications[C]. Proceedings of International Symposium on Circuits and Systems(ISCAS), Bangkok, Vol.5, May 2003, pp.217-220.
[40]Zhonghai Lu. Using Wormhole Switching for Networks on Chip:Feasibility Analysis and Microarchitecture Adaptation. IEEE, June 2004.
[41]W. J. Dally, C. L. Seitz. Deadlock-free message routing in multiprocessor interconnection networks, IEEE Trans. Computers C36(5), pp.547-553,1987.
[42]H S Wang, X P Zhu, L S Peh, et al. Orion:a power-performance simulator for interconnection networks. Microarchitecture,2002. (MICRO-35). Nov2002: 294-305.
[43]E Rijpkcma, K Goossens, A Radulescu, et al. Trade-offs in the design of a router with both guaranteed and best-effort services for networks om chip. Computers and Digital Techniques, IEEE Proceedings. Sept 2003,150(5):294-302.
[44]E Bolotin, I Cidon, R Ginosar, et al. QNoC:QoS architecture and design process for network on chip. J.Syst.Architecture:EUROMICRO J. Feb 2004, vol.50:105-128.
[45]M Saneei, A Afzali-Kusha, and Z Navabi. Low-power and Low-latency Cluster Topology for Local Traffic NoCs, In Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos,Greece, vol.4 pp.1-5, May 2006.
[46]P Guerrier, A Greiner. A generic architecture for on-chip packet switched interconnections. Proc. Date, March 2000:250-256.
[47]孙立新,邢宁霞.CDMA移动通信技术.北京,人民邮电出版社,1997.
[48]R. H. Bell, Jr., et al. "CDMA as a Multiprocessor Interconnect Strategy", Conference Record of the 35th Asilomar Conference on Signals, Systems and Computers, vol.2,4-7 Nov.2001, pp.1246-1250.
[49]R. Yoshimura, T. B. Keat, et al."DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs", Digest of Technical Papers of International Solid-State Circuits Conference,7-9 Feb.2000, PP.370-371.
[50]Walsh, J. L. "A Closed Set of Normal Orthogonal Functions", American Journ. Mathe, vol.45, pp.5-24,1923.
[2]Semiconductor Industry Association.International Technology Roadmap for Semiconductors 2003 Edition Executive Summary,2003.
[3]W B Toms. Synthesis of Quasi-Delay-Insensitive Datapath Circuits. A thesis submitted to the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Science & Engineering,2006.
[4]L. Benini and G De Micheli. Network on chip:a new SoC paradigm [J], IEEE Computer, vol.35, no.1, Jan,2002.
[5]Tobias Bjerregaard, Shankar Mahadevan. "A Survey of Research and Practices of Network-on-Chip", ACM Computing Surveys, Vol.38, Issue 1,2006.
[6]Axel Jantsch, Johnny Qberg, Hannu Tenhunen. "Special issue on networks on chip ". Journal of Systems Architecure, February 2004, pp.61-63.
[7]Coppola M, Curaba S, OCCN:a network-on-chip modeling and simulation framework[C]. Proc. of the Design Automation and Test in Europe Conference and Exhibition,2004,3:174-179.
[8]Bertozzi D and Benini L. Xpipes:a network-on-chip architecture for gigascale systems-on-chip[J]. IEEE, Circuits and Systems Magazine,2004,4(2):18-31.
[9]Benini L and De Micheli G.. Networks on chip:a new paradigm for systems on chip design[C]. Proc. of the Design Automation and Test in Europe Conference and Exhibition,2002:418-419.
[10]荆元利,樊晓桠.网络互连多线程处理器[J].计算机工程与应用,2005,41(33)：51-53,78.
[11]荆元利.基于片上网络的系统芯片的研究[D].西安,西北工业大学.2005.
[12]周文彪,张岩,毛志刚.片上网络的低功耗自适应数据保护[J].计算机工程,2006,32(22)：28-30.
[13]周干民..NoC基础研究[D].合肥：合肥工业大学博士学位论文.2005.
[14]高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4)：416-466.
[15]David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza. "Architecture of the Scalable Communications Core's Network on Chip" IEEE Micro, vol.27, no.5, pp.62-74, Sep./Oct.2007.
[16]Antonio Pullini, Fedefico Angiolini, PaoloMeloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini. "NoC Design and Implementation in 65nm Technology" NoCs, PP.273-282, First International Symposium on Networks-on-Chip(NOCS'07),2007.
[17]Siebenborn A, Bringmann O and Rosenstiel W. Communication analysis for network-on-chip design[C]. International Conf. on Parallel Computing in Electrical Engineering,2004:315-320.
[18]Carara E, Mello A and Moraes F. Communication models in Networks-on-chip[C]. The 18th IEEE/IFIP International Workshop on Rapid System Prototyping,2007:57-60.
[19]SystemC homepage.http://www.systemc.org.
[20]SystemC version 2.0 User's Guide.
[21]徐宁仪,冷祥纶,周祖成.基于SystemC的支持异源通信实体的NoC仿真架构.半导体技术,2006,31(3)：305-309.
[22]徐宁仪,陈曦.SystemC片上系统设计.北京：科学出版社,2004.
[23]D.C.Blank and J. Donovan. SystemC:From The Ground Up.Eclectic Ally,2004.
[24]T.Grotker, S.Liao, G. Martin and S. Swan. System Design with SystemC. Kluwer Academic Publishers,2002.
[25]Soheil Samii. "Modeling and Simulation with SystemC", Dept. of Computer and Information Science,2007.
[26]Axel Jantsch. NoC Architecture. ESSCIRC. September 2001.
[27]Y Liu. Power-Efficient Embedded Processing. A thesis submitted the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Engineering and Physical Sciences, School of Computer Science,2005.
[28]S. Kumar et al. A Network on Chip Architecture and Design Methodology [A], IEEE Computer Society Annual Symposium on VLSI(ISVLSI'02)[C]. April 2002:105-124.
[29]C. A. Zeferino and A. A. Susin, SoCIN:a parametric and scalable network-on-chip[C], in Proc.16th Symposium on Integrated Circuits and System Design, pp.169-174, September 2003.
[30]W. J. Dally and B. Towles, Route Packets, Not Wires:On-Chip Interconnection Networks[C]. In Proc. Design Automation Conference, pp.684-689, June 2001.
[31]Resve Saleh, Steve Wilton, Mirabbasi. System-on-chip:reuse and integration[C]. Proceedings of the IEEE, Vol.94, no.6, June 2006.
[32]W. J. Dally and C.L.Seitz, "The Torus Routing Chip", Technical Report 5208: TR:86.Computer Science Dept., California Inst. of Technology, pp.1-19,1986.
[33]F. Karim et al. "An Interconnet Architecture for Networking Systems on Chips ", IEEE Micro, vol.22, no.5, pp.36-45, Oct.2002.
[34]Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia et al. Spidergon:a novel on-chip communication network, System-on-Chip,2004. Proceedings.2004 International Symposium on, pp.15-18, Nov.2004.
[35]M Dehyadgari, M Nickray, A Afzali-kusha, et al. Evaluation of pseudo adaptive XY routing using an object oriented model for NoC. The 17th International Conference on Microelectronics,2005.
[36]Tobias Bjerregaard and Shankar Mahadevan. "A Survey of Research and Practices of Network-on-Chip", ACM Computing Surveys, Vol.38:19-27, Issue 1,2006.
[37]J. M. Pavia. Design and implementation of a fat tree network on chip [D]. Master's thesis, Institute of Microelectronics and Information Technology, Royal Institute of Technology(KTH), Stockholm, Swedem, June 2004.
[38]Adriahantenaina.A., Charlery.H., Greiner, A.et al. SPIN:a scalable, packet switched, on-chip micro-network[D]. Design Automation and Test in Europe Conference and Exhibition,2003, pp.70-73.
[39]P. P. Pande, C. Grecu, A. Ivanov, R. Saleh. Design of a Switch for Network on Chip Applications[C]. Proceedings of International Symposium on Circuits and Systems(ISCAS), Bangkok, Vol.5, May 2003, pp.217-220.
[40]Zhonghai Lu. Using Wormhole Switching for Networks on Chip:Feasibility Analysis and Microarchitecture Adaptation. IEEE, June 2004.
[41]W. J. Dally, C. L. Seitz. Deadlock-free message routing in multiprocessor interconnection networks, IEEE Trans. Computers C36(5), pp.547-553,1987.
[42]H S Wang, X P Zhu, L S Peh, et al. Orion:a power-performance simulator for interconnection networks. Microarchitecture,2002. (MICRO-35). Nov2002: 294-305.
[43]E Rijpkcma, K Goossens, A Radulescu, et al. Trade-offs in the design of a router with both guaranteed and best-effort services for networks om chip. Computers and Digital Techniques, IEEE Proceedings. Sept 2003,150(5):294-302.
[44]E Bolotin, I Cidon, R Ginosar, et al. QNoC:QoS architecture and design process for network on chip. J.Syst.Architecture:EUROMICRO J. Feb 2004, vol.50:105-128.
[45]M Saneei, A Afzali-Kusha, and Z Navabi. Low-power and Low-latency Cluster Topology for Local Traffic NoCs, In Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos,Greece, vol.4 pp.1-5, May 2006.
[46]P Guerrier, A Greiner. A generic architecture for on-chip packet switched interconnections. Proc. Date, March 2000:250-256.
[47]孙立新,邢宁霞.CDMA移动通信技术.北京,人民邮电出版社,1997.
[48]R. H. Bell, Jr., et al. "CDMA as a Multiprocessor Interconnect Strategy", Conference Record of the 35th Asilomar Conference on Signals, Systems and Computers, vol.2,4-7 Nov.2001, pp.1246-1250.
[49]R. Yoshimura, T. B. Keat, et al."DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs", Digest of Technical Papers of International Solid-State Circuits Conference,7-9 Feb.2000, PP.370-371.
[50]Walsh, J. L. "A Closed Set of Normal Orthogonal Functions", American Journ. Mathe, vol.45, pp.5-24,1923.