面向高效NoC路由差错码设计
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摘要
片上网络系统(NoC)是目前研究的热点,它是更高层次更大规模的片上系统,其核心思想是将计算机网络技术移植到芯片设计中来,利用网络互连的方式来解决多IP核的体系结构问题。片上互连是NoC芯片的关键之一,它的正常通信关系到芯片的正常功能,但随着工艺尺寸的缩小,互连上的串扰噪声已经严重干扰了信号的传递,同时降低了芯片的工作频率。为了保证互连的传输的正确性,以及片上网络高吞吐量的需求,本文设计了整套片上网络可靠性传输方案。以四相双轨握手协议为桥梁,设计了一种纠错码,异步虫孔路由节点,以及以此为基础的4x4 mesh片上网络结构。利用简单的分组汉明编码使得信道传输的码字纠错能力可达10位,采用复制编码基本消除了串扰噪声带来的影响,通过简单的C单元逻辑电路将物理层的数据转换成高层协议数据便于路由节点转发数据。设计了一种低功耗,对延时不敏感,适合多时钟域的异步路由器,又利用通道分片和超前流水技术加速路由节点,使其吞吐量最高可达2.3GB/s。采用本文设计的包组织形式和发送规则,使得网络带宽利用率显著提高,对小数据包的效果最明显,约可提速三倍。
Network-on-Chip(NoC) is a hot-spot in research field and is considered as a reasonable solution for integrating plenty of IPs on a single chip. A reliable communication through connection wires is a must for the proper function of the whole chip. But as the rapid shrinking of the technology, crosstalk becomes one of the main noise sources of affecting signal integrity. In order to guarantee a reliable interconnection communication, as well as a high throughput, this paper presents a whole set of reliable transmission scheme for network-on-chip, including an error correcting code, an asynchronous router, 4-phase dual-rail protocol and 4x4 mesh NoC arch. The self-correct ability of our code can reach as high as 10-bit by using group hamming codes. Duplication can nearly eliminate crosstalk effects. Simple circuit based on C-element can translate physical data into higher protocol for routing. The asynchronous router, which is low power and qausi-delay-insensitive, is designed. This router is suitable for multi-clock-domain. By employing channel slicing and look ahead pipeline, the router’s highest throughput can reach up to 2.3GB/Node/sec. The novel frame format and transmitting rule makes full use of bandwidth. When the packet is small, the speed can be accelerated about 3 times.
Network-on-Chip(NoC) is a hot-spot in research field and is considered as a reasonable solution for integrating plenty of IPs on a single chip. A reliable communication through connection wires is a must for the proper function of the whole chip. But as the rapid shrinking of the technology, crosstalk becomes one of the main noise sources of affecting signal integrity. In order to guarantee a reliable interconnection communication, as well as a high throughput, this paper presents a whole set of reliable transmission scheme for network-on-chip, including an error correcting code, an asynchronous router, 4-phase dual-rail protocol and 4x4 mesh NoC arch. The self-correct ability of our code can reach as high as 10-bit by using group hamming codes. Duplication can nearly eliminate crosstalk effects. Simple circuit based on C-element can translate physical data into higher protocol for routing. The asynchronous router, which is low power and qausi-delay-insensitive, is designed. This router is suitable for multi-clock-domain. By employing channel slicing and look ahead pipeline, the router’s highest throughput can reach up to 2.3GB/Node/sec. The novel frame format and transmitting rule makes full use of bandwidth. When the packet is small, the speed can be accelerated about 3 times.
引文
[1].郭炜,郭筝,谢憬,SoC设计方法与实现,电子工业出版社,2007
[2]. L. Benini and G. De Micheli,“Networks on chips: A new SOC para-digm,”IEEE Comput., vol. 35, no. 1, pp. 70–78, Jan. 2002.
[3]. J.Davis,J.Meindl.Compact Distributed RLC Interconnect Models Part II:Coupled LineTransient Expressions and Peak Crosstalk in Multilevel Networks.IEEE trans.electron devices,Nov 2000,vol.479(11):2078-2087
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[8]. Y.Shin, S.Chae,K.Choi. Reduction of bus transitions with partial bus-invert coding.Electronics letters,Apr 1998,vol.34(7):642-643
[9]. P.Sotiriadis, A.Chandrakasan. A Bus Energy Model For Deep Sub-Micron Technology.IEEEtrans.VLSI Systems,June 2002,vol.10(3):341-350
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[12]. A.Kahng,S.Muddu.An Analytical Delay Model for RLC Interconnects.IEEE Trans.ComputAided Des Integr Circuits Syst,Dec 1997,vol.16(12):334-342
[13]. T.Sakurai.Closed-Form Expressions for Interconnect Delay,Coupling and Crosstalk in VLSIs.IEEE Trans.Electron Devices,Jan 1993,vol.40(1):415-523
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[17]. Kei Hirose, Hiroto Yasuura. A bus delay reduction technique considering crosstalk. Design, Automation and Test in Europe Conference and Exhibition.Paris,France:DATE,2000,441-445
[18]. C.G.Lyuh,T.Kim.Low power bus encoding with crosstalk delay elimination.IEEE Proc.Comput Digital Tech,2006,vol.153(2):93-100
[19]. B.Victor,K.Keutzer.Bus encoding to prevent crosstalk delay.International Conference on Computer-Aided Design 2001.San Jose,CA,United states:IEEE,2001,57-63
[20]. Ketan N.Patel,Igor L.Markov.Error-correction and crosstalk avoidance in DSM busses.IEEE Trans.VLSI Syst,2004,vol.12(10):1076-1080
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[22]. S. R. Sridhara and N. R. Shanbhag,“Coding for system-on-chip net-works: A uni?ed framework,”IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 13, no. 6, pp. 655–667, Jun. 2005
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[25]. Amlan Ganguly, Partha Pande, Benjamin Belzer,“Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects”, IEEE Transactions on VLSI (TVLSI) Vol. 17, No.11, pp. 1626-1639, November 2009.
[26]. P-T. Huang , W.-L. Fang , Y.-L. Wang and W. Hwang "Low power and reliable interconnection with self-corrected green coding scheme for network-on-chip", Proc. IEEE NoC Symp., pp. 77 2008
[27].都政.NoC关键技术研究与实现.[硕士论文].湖南,国防科学技术大学.2007
[28]. Axel Jantsch.NOC Architecture.ESSCIRC.September 2001.
[29].王峥,顾华玺,杨烨,乐天助.片上网络交换机制的研究.中国集成电路.2007,12.22-27
[30].李磊.片上网络NoC通信研究.[博士论文].杭州.浙江大学.2007
[31].刘毅,杨银堂,周东红.一种面向片上网络的多时钟路由器设计.西安电子科技大学学报(自然科学版).2011,4.146-150
[32]. A.Sheibanyrad, Asynchronous implementation of a distributed network-on-chip, Ph.D. thesis, University of Pierre et Marie Curie (2008)
[33]. J. Bainbridge, S. Furber, Chain: a delay-insensitive chip area interconnect, IEEE Micro 22 (2002) 16–23
[34]. T. Felicijan, S. B. Furber, An asynchronous on-chip network router with quality-of-service ( QoS ) support, in: Proc. Of IEEE International SOC Conference, 2004, pp. 274–277
[35]. E. Beign′e, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin, An asynchronous NOC architecture providing low latencyservice and its multi-level design framework, in: Proc. of ASYNC, 2005, pp. 54–63
[36]. Wei Song,Doug Edwards. Asynchronous Spatial Division Multiplexing Router,Ph.D. thesis.2011
[37]. http://en.wikipedia.org/wiki/Asynchronous_system
[38]. D. J. Kinniment, Synchronization and Arbitration in Digital Systems. John Wiley & Sons Inc., 2007
[39]. R. R. Dobkin, R. Ginosar, A. Kolodny, QNoC asynchronous router, Integration, the VLSI Journal 42 (2) (2009) 103–115.
[40]. K. S. Low and A. Yakovlev,“Token ring arbiters: An exercise in asynchronous logic design with Petri nets,”Newcastle University, Tech.Rep., 1995
[41]. M. B. Josephs and J. T. Yantchev,“CMOS design of the tree arbiter element,”IEEE Transactions on VLSI, vol. 4, no. 4, pp. 472–476,Dec 1996
[42]. S. Golubcovs, D. Shang, F. Xia, A. Mokhov, A. Yakovlev, Modular approach to multi-resource arbiter design, in: Proc.of ASYNC, 2009, pp. 107–116.
[43]. D. Shang, F. Xia, S. Golubcovs, A. Yakovlev, The magic rule of tiles: virtual delay insensitivity, in: Proc. of PATMOS,2009
[44]. http://en.wikipedia.org/wiki/C-element
[2]. L. Benini and G. De Micheli,“Networks on chips: A new SOC para-digm,”IEEE Comput., vol. 35, no. 1, pp. 70–78, Jan. 2002.
[3]. J.Davis,J.Meindl.Compact Distributed RLC Interconnect Models Part II:Coupled LineTransient Expressions and Peak Crosstalk in Multilevel Networks.IEEE trans.electron devices,Nov 2000,vol.479(11):2078-2087
[4]. P. P. Sotiriadis. Interconnect modeling and optimization in deep sub-micron technologies:[Ph.D.dissertation]. Cambridge, USA: Massachusetts Institute of Technology,May 2002,23-202
[5]. M.Stan,W.Burleson.Low-power encodings for global communication in cmos VLSI.IEEE Trans.VLSI Systems,Dec 1997,vol.5(4):49-58
[6]. M.Stan,W.Burleson.Two-dimensional codes for low-power. Proceedings of the 1996International Symposium on Low Power Electronics and Design.Monterey,CA,USA:IEEE,Aug 1996,335-340
[7]. P.Panda,N.Dull.Reducing address bus transitions for low power memory mapping.Proceedings of the 1996 European Design&Test Conference.Paris,France:IEEE,Mar 1996,63-37
[8]. Y.Shin, S.Chae,K.Choi. Reduction of bus transitions with partial bus-invert coding.Electronics letters,Apr 1998,vol.34(7):642-643
[9]. P.Sotiriadis, A.Chandrakasan. A Bus Energy Model For Deep Sub-Micron Technology.IEEEtrans.VLSI Systems,June 2002,vol.10(3):341-350
[10]. Miller effect(From Wikipedia).http://en.wikipedia.org/wiki/Miller_effect
[11]. P.Sotiriadis,A.Chandrakasan.Reducing Bus Delay in Submicron Technology Using Coding. IEEE Asia and South Pacific Design Automation Conf.Yokohama:ASPDAC,2001,109-114
[12]. A.Kahng,S.Muddu.An Analytical Delay Model for RLC Interconnects.IEEE Trans.ComputAided Des Integr Circuits Syst,Dec 1997,vol.16(12):334-342
[13]. T.Sakurai.Closed-Form Expressions for Interconnect Delay,Coupling and Crosstalk in VLSIs.IEEE Trans.Electron Devices,Jan 1993,vol.40(1):415-523
[14]. D.Bertozzi,L.Benini,G.D.Micheli.Low power error resilient encoding for on-chip databuses.Design,Automation and Test in Europe Conference andExhibition.Paris,France:DATE,2002,102–109
[15].谢国梁. NoC总线编码技术研究[硕士论文],成都,电子科技大学,2010
[16]. Chunjie Duan,Anup Tirumala,Sunil P.Khatri.Analysis and avoidance of cross-talk in on-chip bus. Proceedings of the 9th Symposium on High Performance Interconnects.Stanford,CA:HIS,2001,133-138
[17]. Kei Hirose, Hiroto Yasuura. A bus delay reduction technique considering crosstalk. Design, Automation and Test in Europe Conference and Exhibition.Paris,France:DATE,2000,441-445
[18]. C.G.Lyuh,T.Kim.Low power bus encoding with crosstalk delay elimination.IEEE Proc.Comput Digital Tech,2006,vol.153(2):93-100
[19]. B.Victor,K.Keutzer.Bus encoding to prevent crosstalk delay.International Conference on Computer-Aided Design 2001.San Jose,CA,United states:IEEE,2001,57-63
[20]. Ketan N.Patel,Igor L.Markov.Error-correction and crosstalk avoidance in DSM busses.IEEE Trans.VLSI Syst,2004,vol.12(10):1076-1080
[21]. http://en.wikipedia.org/wiki/Hamming_code
[22]. S. R. Sridhara and N. R. Shanbhag,“Coding for system-on-chip net-works: A uni?ed framework,”IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 13, no. 6, pp. 655–667, Jun. 2005
[23]. D. Bertozzi, L. Benini, and G. De Micheli,“Error control schemes for on-chip communication links: The energy-reliability tradeoff,”IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 6, pp. 818–831, Jun. 2005
[24]. Q. Yu, B. Zhang, Y. Li and P. Ampadu,“Error control integration scheme for reliable NoC,”in Proc. 2010 IEEE Intl. Symp. on Circuit and Syst. (ISCAS’10), pp. 3893-3896, May 2010
[25]. Amlan Ganguly, Partha Pande, Benjamin Belzer,“Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects”, IEEE Transactions on VLSI (TVLSI) Vol. 17, No.11, pp. 1626-1639, November 2009.
[26]. P-T. Huang , W.-L. Fang , Y.-L. Wang and W. Hwang "Low power and reliable interconnection with self-corrected green coding scheme for network-on-chip", Proc. IEEE NoC Symp., pp. 77 2008
[27].都政.NoC关键技术研究与实现.[硕士论文].湖南,国防科学技术大学.2007
[28]. Axel Jantsch.NOC Architecture.ESSCIRC.September 2001.
[29].王峥,顾华玺,杨烨,乐天助.片上网络交换机制的研究.中国集成电路.2007,12.22-27
[30].李磊.片上网络NoC通信研究.[博士论文].杭州.浙江大学.2007
[31].刘毅,杨银堂,周东红.一种面向片上网络的多时钟路由器设计.西安电子科技大学学报(自然科学版).2011,4.146-150
[32]. A.Sheibanyrad, Asynchronous implementation of a distributed network-on-chip, Ph.D. thesis, University of Pierre et Marie Curie (2008)
[33]. J. Bainbridge, S. Furber, Chain: a delay-insensitive chip area interconnect, IEEE Micro 22 (2002) 16–23
[34]. T. Felicijan, S. B. Furber, An asynchronous on-chip network router with quality-of-service ( QoS ) support, in: Proc. Of IEEE International SOC Conference, 2004, pp. 274–277
[35]. E. Beign′e, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin, An asynchronous NOC architecture providing low latencyservice and its multi-level design framework, in: Proc. of ASYNC, 2005, pp. 54–63
[36]. Wei Song,Doug Edwards. Asynchronous Spatial Division Multiplexing Router,Ph.D. thesis.2011
[37]. http://en.wikipedia.org/wiki/Asynchronous_system
[38]. D. J. Kinniment, Synchronization and Arbitration in Digital Systems. John Wiley & Sons Inc., 2007
[39]. R. R. Dobkin, R. Ginosar, A. Kolodny, QNoC asynchronous router, Integration, the VLSI Journal 42 (2) (2009) 103–115.
[40]. K. S. Low and A. Yakovlev,“Token ring arbiters: An exercise in asynchronous logic design with Petri nets,”Newcastle University, Tech.Rep., 1995
[41]. M. B. Josephs and J. T. Yantchev,“CMOS design of the tree arbiter element,”IEEE Transactions on VLSI, vol. 4, no. 4, pp. 472–476,Dec 1996
[42]. S. Golubcovs, D. Shang, F. Xia, A. Mokhov, A. Yakovlev, Modular approach to multi-resource arbiter design, in: Proc.of ASYNC, 2009, pp. 107–116.
[43]. D. Shang, F. Xia, S. Golubcovs, A. Yakovlev, The magic rule of tiles: virtual delay insensitivity, in: Proc. of PATMOS,2009
[44]. http://en.wikipedia.org/wiki/C-element