铜互联工艺中的DFM方法研究
|
摘要
随着半导体技术代的快速发展，传统的SOC芯片设计逐渐变得无法制造，这个问题在铜互联技术中表现的尤为突出。本文针对铜互联工艺的几项关键技术，展开了相关的DFM基础研究，论文主要包括以下内容：
(1)光刻OPC建模和检验。利用光学仿真，得到传统照明条件和6％透射率的移相掩模板组合是最佳的双重曝光组合，实际的试验结果也与模拟相同。经过优化，光刻胶B在传统照明条件(248nm 0．68NA／0．5sigma)和6％透射率的移相掩模板组合的曝光条件下表现最为优异，其工艺窗口符合双重曝光需求，经过OPC修正后，各种不同Pitch下的线宽差异减小到+／-5nm以内，并且版图、OPC模拟图像和SEM照片完美重合，使得设计具备了可制造性，可以进行量产试验。
(2)钨CMP工艺建模及检验。提出钨CMP时侵蚀的模型，该模型与试验数据能很好地吻合。赝侵蚀是该模型的重要概念。模型可用于指导CMP工艺中的关于凹陷和侵蚀的分析，由此减少工艺监控环节，降低成本。
(3)铜CMP侵蚀模型研究。研究了铜化学机械抛光时的侵蚀现象，提出了相关数学模型，模型能解释不同的图形密度、设计规则对化学机械抛光后侵蚀的影响。
As the semiconductor fabrication ground rule has reached the 130nm node beyond,itseems that traditional SOC design technology cannot meet the need of advancedcopper metallization for Ultra-Large-Scale-lntegrated (ULSI) circuits needed to meetperformance requirements for advanced interconnect technologies.In this thesis,threekey copper interconnection process technology have been researched to developcopper interconnection DFM method.The main research subjects are as following:(1) Modeling of Optical Proximity Correction and process simulation.To study thedouble exposure mechanism,we have used a 248 nm deep-UV exposure tool andseveral well chosen photoresist to study and simulate the photo performanceparameters in the merge of two photo exposures.By photolithography simulation,wefind that traditional illumination conditions,together with PSM which has 6%refractive index,can be the best double exposure combination,process data also showthe same result.By process optimization,it seems that,with a traditional illuminationconditions (248nm 0.68NA/0.5sigma)combined with PSM which has 6% refractiveindex,photoresist B shows the most excellent performance,its process window canfit the need of double exposure,also by Optical Proximity Correction,the variation ofline-width at different pitch can be reduced to +/-5nm,At the same time,physicalSEM analysis also show the same result,so we can come to a decision that this designcan be used to manufacture.
(2) Modeling ofW CMP erosion.Process experiments show that this model can beused to explain the abnormal phenomena of erosion after W CMP.And by this means,the monitor item for W CMP erosion can be skipped so as to lower down the cost ofowner.
(3) Modeling of Cu CMP erosion.It is well known that topography resulting frompattern dependencies in various processes, especially Chemical-MechanicalPlanarization (CMP),is a major problem in interconnects.An pattern dependenterosion model for copper metallization is contributed to help understand and meeterosion requirements,to optimize the polishing process to achieve minimialenvironmental impact,higher yield and performance,and to enable optimization oflayout and dummy fill designs.
(1)光刻OPC建模和检验。利用光学仿真，得到传统照明条件和6％透射率的移相掩模板组合是最佳的双重曝光组合，实际的试验结果也与模拟相同。经过优化，光刻胶B在传统照明条件(248nm 0．68NA／0．5sigma)和6％透射率的移相掩模板组合的曝光条件下表现最为优异，其工艺窗口符合双重曝光需求，经过OPC修正后，各种不同Pitch下的线宽差异减小到+／-5nm以内，并且版图、OPC模拟图像和SEM照片完美重合，使得设计具备了可制造性，可以进行量产试验。
(2)钨CMP工艺建模及检验。提出钨CMP时侵蚀的模型，该模型与试验数据能很好地吻合。赝侵蚀是该模型的重要概念。模型可用于指导CMP工艺中的关于凹陷和侵蚀的分析，由此减少工艺监控环节，降低成本。
(3)铜CMP侵蚀模型研究。研究了铜化学机械抛光时的侵蚀现象，提出了相关数学模型，模型能解释不同的图形密度、设计规则对化学机械抛光后侵蚀的影响。
As the semiconductor fabrication ground rule has reached the 130nm node beyond,itseems that traditional SOC design technology cannot meet the need of advancedcopper metallization for Ultra-Large-Scale-lntegrated (ULSI) circuits needed to meetperformance requirements for advanced interconnect technologies.In this thesis,threekey copper interconnection process technology have been researched to developcopper interconnection DFM method.The main research subjects are as following:(1) Modeling of Optical Proximity Correction and process simulation.To study thedouble exposure mechanism,we have used a 248 nm deep-UV exposure tool andseveral well chosen photoresist to study and simulate the photo performanceparameters in the merge of two photo exposures.By photolithography simulation,wefind that traditional illumination conditions,together with PSM which has 6%refractive index,can be the best double exposure combination,process data also showthe same result.By process optimization,it seems that,with a traditional illuminationconditions (248nm 0.68NA/0.5sigma)combined with PSM which has 6% refractiveindex,photoresist B shows the most excellent performance,its process window canfit the need of double exposure,also by Optical Proximity Correction,the variation ofline-width at different pitch can be reduced to +/-5nm,At the same time,physicalSEM analysis also show the same result,so we can come to a decision that this designcan be used to manufacture.
(2) Modeling ofW CMP erosion.Process experiments show that this model can beused to explain the abnormal phenomena of erosion after W CMP.And by this means,the monitor item for W CMP erosion can be skipped so as to lower down the cost ofowner.
(3) Modeling of Cu CMP erosion.It is well known that topography resulting frompattern dependencies in various processes, especially Chemical-MechanicalPlanarization (CMP),is a major problem in interconnects.An pattern dependenterosion model for copper metallization is contributed to help understand and meeterosion requirements,to optimize the polishing process to achieve minimialenvironmental impact,higher yield and performance,and to enable optimization oflayout and dummy fill designs.
引文
[1]D.Edelstein,J.Heidenreich,R.Goldblatt,W.Cote,C.Uzoh,R.Lustig,P.Roper,T.McDevitt,W.Motsiff,A.Simon,J.Dukovic,R.Wachnik,H.Rathore,R.Schulz,L.Su,S.Luce,and J.Slattery,“Full Copper Wiring in a Sub-0.25 μm CMOS ULSI Technology,” Proc.IEEE IEDM,pp.773-776,1997.
[2]S.Venkatesan,A.V.Gelatos,V.Misra,B.Smith,R.Islam,J.Cope,B.Wilson,D.Tuttle,R.Cardwell,S.Anderson,M.Angyal,R.Bajaj,C.Capasso,P.Crabtree,S.Das,J.Farkas,S.Filipiak,B.Fiordalice,M.Freeman,P.V.Gilvert,M.Herrick,A.Jain,H.Kawasaki,C.King,J.Klein,T.Lii,K.Reid,T.Saaranen,C.Simpson,T.Sparks,P.Tsui,R.Venkatraman,D.Watts,E.J.Weitzman,R.Woodruff,I.Yang,N.Bhat,G.Hamilton,and Y.Yu,“A High Performance 1.8V,0.29 μm CMOS Technology with Copper Metallization,” Proc.IEEE IEDM,pp.769-772,1997.
[3]R.Rosenberg,D.C.Edelstein,C.-K.Hu,and K.P.Rodbell,“Copper Metallizationfor High Performance Silicon Technology,” Annu.Rev.Mater.Res.,vol.30,pp.229-262,2000.
[4]C.Wyon,“Future technology for advanced MOS devices,” Nuclear Instruments andMethods in Physics Research Section B:Beam Interactions with Materials and Atoms,vol.186,No.1-4,pp.380-391,2002.
[5]H.Takeuchi,W.Lee:P.Ranade,and W.Ring,“Improved PMOSFET short-channel performance using ultra-shallow SiO.8Ge 0.2 source/drain extensions,”IEDM Technical Digest,pp.501-504,1999.
[6]International Technology Roadmap for Semiconductors,International SEMATECH,Austin,TX,2005.
[7]R.H.Havemann and J.A.Hutchby,“High-performance interconnects:an integrationoverview,” Proceedings of the IEEE,vol.89,no.5,pp.586-601,2001
[8]R.D.Levenson,N.S.Viswanathan,R.A.Simpson,“Improving Resolution in Photolithography with a Phase Shifting Mask,” IEEE Trans.Electr.Dev.,ED-29(12),pp.1828-1836,1982.
[9]K.Kamon,T.Miyamoto,M.Yasuhito,H.Nagata,M.Tanaka,and K.Horie,“Photolithography System Using Annular Illumination,” Jpn.J.Appl.Phys.,Vol.30,No.11B,pp.3012-3029,1991.
[10]N.Shiraishi,S.Hirukawa,V.Takeuchi,N.Magome,“New Imaging Technique for 64M-DRAM,” Proceedings of SPIE,Vol.1674,pp.741-752,1992.
[11] F. M. Schellenberger, H. Zhang. and J. Morrow, "SEMATECH J111 Project: OPC Validation," Proceedings of SPIE, Vol. 3334, pp. 892-911, 1998.
[12] Donis G. Flagello, Bernd Geh, Robert Socha, "Understanding illumination effects for control of optical proximity effects (OPE), " Proceedings of SPIE,6924, 69241U ,2008.
[13] P. Chien and M. Chen, "Proximity Effects in Submicron Optical Lithography,Proceedings of SPIE, Vol. 772, pp. 35-40, 1987.
[14] P. Pforr, A. K. Wong, K. Ronse, "Feature Biasing Versus Feature-Assisted Lithography: A Comparison of Proximity Correction Methods for 0.5*(λ/NA) Lithography, " Proceedings of SPIE, Vol. 2440, pp. 150-170, 1995.
[15] A. Starikov, "Use of a Single Size Square Serif for Variable Print Bias Compensation in Microlithography: Method, Design and Practice, " Proceedings of SPIE, " Vol. 1088, pp. 34-36,1989.
[16] W. Arnold, M. Dusa, J. Finders, "Manufacturing Challenges in Double Patterning Lithography," IEEE, PP. 283-286.
[17] M. Maenhoudt, "Lithography options and challenges for sub-45nm node interconnect layers, " IEEE, pp.70-72, 2008.
[18] F. Preston, J. Soc. Glass Tech. 11, 214 (1927)
[17] Joseph M. Steigerwald, Chemical Mechanical Planarization of Microelectronic Materials, P 84, John Wiley & Sons, Inc., 1997
[19] Beverina et al, Photo-Corrosion Effects during Cu Interconnection Cleaning,1999 joint international meeting ECS, Hawaii, 17-22, Oct. 1999, P 625
[20] Anji Technology Materials: Cu Barrier CMP Report
[1]Keith Nabors and Jacob White,“FastCap:A Multipole Accelerated 3-D Capacitance Extraction Program,” IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems,vol.10,no.11,pp.1447-1459,1991
[2]S.Nassif,“Modeling and Analysis of Manufacturing Variations”,IEEE CICC,pp.223-228,2001.
[3]P.C.Andricacos,C.Uzoh,J.O.Pukovic,J.Horkans,and H.Deligianni,“Damascene Copper Electroplating for Chip Interconnects,” IBM Journal of Research and Development,Vol.42,No.5,1998.
[4] J. M. Steigerwald, S. P. Murarka, and R. J. Gutmann, "Chemical Mechanical Planarization of Microelectronic Materials," John Wiley and Sons, Inc., 1997.
[5] Jeong-Taek Kong, "CAD for Nanometer Silicon Design Challenges and Success" ,IEEE Transactions on VLSI Systems, vol. 12, No. 11, Nov. 2004
[6] D. Boning, B. Lee, C. Oji, D. Ouma, T. Park, T. Smith, and T. Tugbawa, "Pattern Dependent Modeling for CMP Optimization and Control, " Materials Research Society 1999 Spring Meeting, San Francisco, CA, April 1999.
[7] T. Park, D. Ouma, R. Muralidhar, D. Boning, and J. Chung, "Copper Damascene CMP Project Mask Documentation, " MIT, Cambridge, MA, April 1997.
[8] T. Park, T. Tugbawa, D. Boning, C. Chidambaram, C. Borst, and G. Shin,"Chip-Scale Modeling of Electroplated Copper Surface Profiles, " Journal of the Electrochemical Society, vol. 151, no. 6, pp. C418-C430, June 2004.
[9] T. Tugbawa, T. Park, and I). Boning, L. Camilletti, M. Brongo, and P. Lefevre,"Modeling of Pattern Dependencies in Multi-Step Copper Chemical Mechanical Polishing Processes, " Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MIC 2001), pp. 65-68, Santa Clara, March 2001.
[10] T. Tugbawa, "Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polilshing Processes, " Ph. D Thesis, Electrical Engineering and Computer Science, MIT, June 2002.
[11] Taber H. Smith, Simon J. Fang, Duane S. Boning, Greg B. Shinn, and Jerry A.Stefani, "A CMP Model Combining Density and Time Dependencies, " 1999 Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MIC), Santa Clara, Feb. 1999.
[12] Stine, B., D. Ouma, R. Divecha, D. Boning, J. Chung, D. Hetherington, I. Ali,G. Shinn, J. Clark, O. Nakagawa, S-Y Oh. , "A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes, " 1997 Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MIC), p. 266, Santa Clara, February,1997.
[13] L. Yang, "Modeling CMP for Copper Dual Damascene Interconnects, " Solid State Tech., vol. 43, no. 6, June 2000.
[2]S.Venkatesan,A.V.Gelatos,V.Misra,B.Smith,R.Islam,J.Cope,B.Wilson,D.Tuttle,R.Cardwell,S.Anderson,M.Angyal,R.Bajaj,C.Capasso,P.Crabtree,S.Das,J.Farkas,S.Filipiak,B.Fiordalice,M.Freeman,P.V.Gilvert,M.Herrick,A.Jain,H.Kawasaki,C.King,J.Klein,T.Lii,K.Reid,T.Saaranen,C.Simpson,T.Sparks,P.Tsui,R.Venkatraman,D.Watts,E.J.Weitzman,R.Woodruff,I.Yang,N.Bhat,G.Hamilton,and Y.Yu,“A High Performance 1.8V,0.29 μm CMOS Technology with Copper Metallization,” Proc.IEEE IEDM,pp.769-772,1997.
[3]R.Rosenberg,D.C.Edelstein,C.-K.Hu,and K.P.Rodbell,“Copper Metallizationfor High Performance Silicon Technology,” Annu.Rev.Mater.Res.,vol.30,pp.229-262,2000.
[4]C.Wyon,“Future technology for advanced MOS devices,” Nuclear Instruments andMethods in Physics Research Section B:Beam Interactions with Materials and Atoms,vol.186,No.1-4,pp.380-391,2002.
[5]H.Takeuchi,W.Lee:P.Ranade,and W.Ring,“Improved PMOSFET short-channel performance using ultra-shallow SiO.8Ge 0.2 source/drain extensions,”IEDM Technical Digest,pp.501-504,1999.
[6]International Technology Roadmap for Semiconductors,International SEMATECH,Austin,TX,2005.
[7]R.H.Havemann and J.A.Hutchby,“High-performance interconnects:an integrationoverview,” Proceedings of the IEEE,vol.89,no.5,pp.586-601,2001
[8]R.D.Levenson,N.S.Viswanathan,R.A.Simpson,“Improving Resolution in Photolithography with a Phase Shifting Mask,” IEEE Trans.Electr.Dev.,ED-29(12),pp.1828-1836,1982.
[9]K.Kamon,T.Miyamoto,M.Yasuhito,H.Nagata,M.Tanaka,and K.Horie,“Photolithography System Using Annular Illumination,” Jpn.J.Appl.Phys.,Vol.30,No.11B,pp.3012-3029,1991.
[10]N.Shiraishi,S.Hirukawa,V.Takeuchi,N.Magome,“New Imaging Technique for 64M-DRAM,” Proceedings of SPIE,Vol.1674,pp.741-752,1992.
[11] F. M. Schellenberger, H. Zhang. and J. Morrow, "SEMATECH J111 Project: OPC Validation," Proceedings of SPIE, Vol. 3334, pp. 892-911, 1998.
[12] Donis G. Flagello, Bernd Geh, Robert Socha, "Understanding illumination effects for control of optical proximity effects (OPE), " Proceedings of SPIE,6924, 69241U ,2008.
[13] P. Chien and M. Chen, "Proximity Effects in Submicron Optical Lithography,Proceedings of SPIE, Vol. 772, pp. 35-40, 1987.
[14] P. Pforr, A. K. Wong, K. Ronse, "Feature Biasing Versus Feature-Assisted Lithography: A Comparison of Proximity Correction Methods for 0.5*(λ/NA) Lithography, " Proceedings of SPIE, Vol. 2440, pp. 150-170, 1995.
[15] A. Starikov, "Use of a Single Size Square Serif for Variable Print Bias Compensation in Microlithography: Method, Design and Practice, " Proceedings of SPIE, " Vol. 1088, pp. 34-36,1989.
[16] W. Arnold, M. Dusa, J. Finders, "Manufacturing Challenges in Double Patterning Lithography," IEEE, PP. 283-286.
[17] M. Maenhoudt, "Lithography options and challenges for sub-45nm node interconnect layers, " IEEE, pp.70-72, 2008.
[18] F. Preston, J. Soc. Glass Tech. 11, 214 (1927)
[17] Joseph M. Steigerwald, Chemical Mechanical Planarization of Microelectronic Materials, P 84, John Wiley & Sons, Inc., 1997
[19] Beverina et al, Photo-Corrosion Effects during Cu Interconnection Cleaning,1999 joint international meeting ECS, Hawaii, 17-22, Oct. 1999, P 625
[20] Anji Technology Materials: Cu Barrier CMP Report
[1]Keith Nabors and Jacob White,“FastCap:A Multipole Accelerated 3-D Capacitance Extraction Program,” IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems,vol.10,no.11,pp.1447-1459,1991
[2]S.Nassif,“Modeling and Analysis of Manufacturing Variations”,IEEE CICC,pp.223-228,2001.
[3]P.C.Andricacos,C.Uzoh,J.O.Pukovic,J.Horkans,and H.Deligianni,“Damascene Copper Electroplating for Chip Interconnects,” IBM Journal of Research and Development,Vol.42,No.5,1998.
[4] J. M. Steigerwald, S. P. Murarka, and R. J. Gutmann, "Chemical Mechanical Planarization of Microelectronic Materials," John Wiley and Sons, Inc., 1997.
[5] Jeong-Taek Kong, "CAD for Nanometer Silicon Design Challenges and Success" ,IEEE Transactions on VLSI Systems, vol. 12, No. 11, Nov. 2004
[6] D. Boning, B. Lee, C. Oji, D. Ouma, T. Park, T. Smith, and T. Tugbawa, "Pattern Dependent Modeling for CMP Optimization and Control, " Materials Research Society 1999 Spring Meeting, San Francisco, CA, April 1999.
[7] T. Park, D. Ouma, R. Muralidhar, D. Boning, and J. Chung, "Copper Damascene CMP Project Mask Documentation, " MIT, Cambridge, MA, April 1997.
[8] T. Park, T. Tugbawa, D. Boning, C. Chidambaram, C. Borst, and G. Shin,"Chip-Scale Modeling of Electroplated Copper Surface Profiles, " Journal of the Electrochemical Society, vol. 151, no. 6, pp. C418-C430, June 2004.
[9] T. Tugbawa, T. Park, and I). Boning, L. Camilletti, M. Brongo, and P. Lefevre,"Modeling of Pattern Dependencies in Multi-Step Copper Chemical Mechanical Polishing Processes, " Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MIC 2001), pp. 65-68, Santa Clara, March 2001.
[10] T. Tugbawa, "Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polilshing Processes, " Ph. D Thesis, Electrical Engineering and Computer Science, MIT, June 2002.
[11] Taber H. Smith, Simon J. Fang, Duane S. Boning, Greg B. Shinn, and Jerry A.Stefani, "A CMP Model Combining Density and Time Dependencies, " 1999 Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MIC), Santa Clara, Feb. 1999.
[12] Stine, B., D. Ouma, R. Divecha, D. Boning, J. Chung, D. Hetherington, I. Ali,G. Shinn, J. Clark, O. Nakagawa, S-Y Oh. , "A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes, " 1997 Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MIC), p. 266, Santa Clara, February,1997.
[13] L. Yang, "Modeling CMP for Copper Dual Damascene Interconnects, " Solid State Tech., vol. 43, no. 6, June 2000.