同时多线程处理器资源共享控制策略研究
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摘要
随着超大规模集成电路技术持续以指数级地发展,处理器芯片上集成的资源将大量地增加,如何有效利用这些资源成为发挥处理器性能的关键。同时多线程(SMT)处理器通过同时执行来自多个线程的指令利用了线程级并行和指令级并行,其细粒度的资源共享和操作延迟隐藏为处理器带来较好的性能提升。然而同时多线程环境中,线程竞争共享资源胜过分享资源,不合理的资源竞争将会导致共享资源的阻塞、滥用和浪费。资源共享控制的合理性决定了处理器的吞吐量和线程间的公平性。随着处理器和存储器之间性能差距的增大,片外访存操作的长延迟将造成SMT处理器上越来越明显的资源阻塞和资源滥用。另外,各线程在竞争共享资源的过程中随着程序行为的变化表现出变化的资源需求,适应性不强的资源共享控制策略将很难持续地提供优化的资源分配方案。这些问题使如何合理地控制SMT处理器资源在线程之间的共享显得尤其重要。
围绕上述问题,本文在深入研究分析相关工作的基础上,从避免长延迟load依赖指令阻塞共享资源、利用计算访存并发性有效隐藏片外访存长延迟、增强资源共享策略对程序行为变化的适应性、以及避免控制决策运算影响关键流水线路径这四种途径展开研究,并提出了相应的同时多线程处理器资源共享控制策略,通过模拟实验验证了各策略的有效性。主要取得以下研究成果。
(1)为避免长延迟load依赖指令阻塞共享资源,提出了长延迟load感知的SMT处理器指令派遣策略DSTALL和DSTALLp。该策略在流水线的派遣阶段实施停止派遣控制决策,根据检测到的或预测到的二级Cache失效信息决定是否停止派遣线程的指令到指令队列。通过避免已取指的长延迟load依赖指令在检测到长延迟load后继续阻塞资源,以及缩短控制决策反馈信息利用延迟的方式,减少了长延迟load给SMT处理器资源共享带来的负面影响。
(2)针对隐藏片外访存长延迟的问题,提出了利用计算和访存操作并发性的SMT处理器资源划分策略ECMC。它从SMT处理器利用线程级并行隐藏长操作延迟的本质特性出发,周期性地根据线程计算型访存型操作并发能力来调整共享资源在各线程之间的划分,为在计算操作与片外访存操作并发性方面表现较好的线程分配更多的资源,提高了执行时钟上的计算操作与访存操作并发率,较有效地隐藏了Cache失效load操作的长延迟。
(3)为了避免资源分配优化过程陷入局部次优空间,增强在变化的程序行为中持续优化的能力,提出了一种空间触发的耗散式SMT处理器资源分配策略SDRD。该策略的分配优化自组织机制和分配空间上触发的混沌协同工作,通过控制资源分配方案的相似度使资源分配方案能逃离局部极优方案,为程序行为变化的不同阶段提供持续的资源分配优化。在仅以吞吐量为目标的情况下,同时照顾了吞吐量和公平性性能。
(4)提出了SMT处理器上非关键路径资源分配器设计模型NCPRD。该模型使资源分配模块独立于处理器关键流水线路径,以避免资源分配在关键流水线路径上的开销给处理器性能带来不可忽略的影响。NCPRD的异步工作模式对于时钟开销较明显的SMT处理器隐式资源共享控制策略也具有参考意义。
With the continuing advancements at an exponential rate in VLSI technology, the volume of resources integrated into a processor chip will increase rapidly. How to make efficient utilization of these resources is the key to exert processor's performance. Simultaneous MultiThreading (SMT) processor takes advantage of both thread level parallelism and instruction level parallelism via concurrently executing instructions from different threads. Its fine-grained resource sharing and long latency hiding brings good performance improvement. However, threads compete for common resources rather than they share them in SMT environment, unreasonable resource competing will result in resource clogging, abusement and wastage. The rationality of resource sharing control determines the throughput performance for processor and the fairness between threads. With the ever increasing performance gap between processor and memory, the long latency from off-chip memory access will make the resource clogging and abusement in SMT processor more eminent. Moreover, threads change their requirment of resources with the the change of their program behavior when they compete for resources, it is difficult for an unadaptable resource sharing control policy to supply continuing optimization of resource distribution. All these problems especially augment the signification of how to reasonably control the sharing of SMT processor resources among the threads.
According to the problems mentioned above, this dissertation, after a deep study on related works, launched the research in four approaches: preventing long-latency-load dependents from clogging common resources, exploiting the concurrency of compute and memory access operations for hiding of off-chip memory access latency, making the resource sharing control policy adaptable to changing program behavior, and eliminating the influence brought to the critical pipeline by those cycles spent on making resource control decision. Corresponding resource sharing control policy for SMT processors was present per approach, and their validity were proved through simulations. The main contributions are as follows.
(1)To prevent instructions dependent on long-latency loads from clogging the common resources, a long-latency-load awared dispatch policy for SMT processors is proposed. This policy decides on whether a thread should be dispatch-stalled at the dispatch stage in the pipeline according to the detected or predicted L2 cache miss information. By preventing those long-latency-load dependents that have been fetched from clogging the common resources after detection of long-latency load, and reducing the feedback latency of the L2 cache miss information, it alleviates the negative influence brought to the resource sharing in SMT processor by long-latency loads.
(2)To address the problem of hiding long latency of off-chip access, a resource partitioning policy for SMT processors exploiting the compute-memory concurrency is proposed. It follows the essential feature of SMT processors that hide long latency by exploiting thread level parallelism, tunes the resource partitions among the threads periodically according to the concurrency level of compute-memory operations of each thread, and provides more resources to the thread that has better performance in compute-memory concurrency. This policy improves the proportion of time for concurrent compute-memory executing to the whole executing time, providing effective hiding of long latency brought by cache-miss loads.
(3)To avoid the stagnation in the suboptimal resource distribution spaces in the resource distribution optimization procedure, and enhance the capability of performing a continue optimization for resource distribution for changing program behavior, a spatially triggered dissipative resource distribution policy for SMT processors is proposed. In this policy, the self-organization mechanism cooperates with the spatially triggered chaos for the distribution solutions. By taking control of the similarity of the distribution solutions, the policy can escape from the suboptimal solution, and supply persistent optimization for resource distribution in different program phases. The throughput and fairness performance are both improved by taking only the throughput as the optimization target.
(4) A design model of non-critical path resource distributor for SMT processors is proposed, which separates the resource distribution module from the critical pipeline path to avoid the clock wastage caused by the computation on the allocation solutions. The asynchronous work mode of this non-critical path resource distributor is also meaningful for those implicit resource sharing control policies that consume obvious cycles in making decision.
围绕上述问题,本文在深入研究分析相关工作的基础上,从避免长延迟load依赖指令阻塞共享资源、利用计算访存并发性有效隐藏片外访存长延迟、增强资源共享策略对程序行为变化的适应性、以及避免控制决策运算影响关键流水线路径这四种途径展开研究,并提出了相应的同时多线程处理器资源共享控制策略,通过模拟实验验证了各策略的有效性。主要取得以下研究成果。
(1)为避免长延迟load依赖指令阻塞共享资源,提出了长延迟load感知的SMT处理器指令派遣策略DSTALL和DSTALLp。该策略在流水线的派遣阶段实施停止派遣控制决策,根据检测到的或预测到的二级Cache失效信息决定是否停止派遣线程的指令到指令队列。通过避免已取指的长延迟load依赖指令在检测到长延迟load后继续阻塞资源,以及缩短控制决策反馈信息利用延迟的方式,减少了长延迟load给SMT处理器资源共享带来的负面影响。
(2)针对隐藏片外访存长延迟的问题,提出了利用计算和访存操作并发性的SMT处理器资源划分策略ECMC。它从SMT处理器利用线程级并行隐藏长操作延迟的本质特性出发,周期性地根据线程计算型访存型操作并发能力来调整共享资源在各线程之间的划分,为在计算操作与片外访存操作并发性方面表现较好的线程分配更多的资源,提高了执行时钟上的计算操作与访存操作并发率,较有效地隐藏了Cache失效load操作的长延迟。
(3)为了避免资源分配优化过程陷入局部次优空间,增强在变化的程序行为中持续优化的能力,提出了一种空间触发的耗散式SMT处理器资源分配策略SDRD。该策略的分配优化自组织机制和分配空间上触发的混沌协同工作,通过控制资源分配方案的相似度使资源分配方案能逃离局部极优方案,为程序行为变化的不同阶段提供持续的资源分配优化。在仅以吞吐量为目标的情况下,同时照顾了吞吐量和公平性性能。
(4)提出了SMT处理器上非关键路径资源分配器设计模型NCPRD。该模型使资源分配模块独立于处理器关键流水线路径,以避免资源分配在关键流水线路径上的开销给处理器性能带来不可忽略的影响。NCPRD的异步工作模式对于时钟开销较明显的SMT处理器隐式资源共享控制策略也具有参考意义。
With the continuing advancements at an exponential rate in VLSI technology, the volume of resources integrated into a processor chip will increase rapidly. How to make efficient utilization of these resources is the key to exert processor's performance. Simultaneous MultiThreading (SMT) processor takes advantage of both thread level parallelism and instruction level parallelism via concurrently executing instructions from different threads. Its fine-grained resource sharing and long latency hiding brings good performance improvement. However, threads compete for common resources rather than they share them in SMT environment, unreasonable resource competing will result in resource clogging, abusement and wastage. The rationality of resource sharing control determines the throughput performance for processor and the fairness between threads. With the ever increasing performance gap between processor and memory, the long latency from off-chip memory access will make the resource clogging and abusement in SMT processor more eminent. Moreover, threads change their requirment of resources with the the change of their program behavior when they compete for resources, it is difficult for an unadaptable resource sharing control policy to supply continuing optimization of resource distribution. All these problems especially augment the signification of how to reasonably control the sharing of SMT processor resources among the threads.
According to the problems mentioned above, this dissertation, after a deep study on related works, launched the research in four approaches: preventing long-latency-load dependents from clogging common resources, exploiting the concurrency of compute and memory access operations for hiding of off-chip memory access latency, making the resource sharing control policy adaptable to changing program behavior, and eliminating the influence brought to the critical pipeline by those cycles spent on making resource control decision. Corresponding resource sharing control policy for SMT processors was present per approach, and their validity were proved through simulations. The main contributions are as follows.
(1)To prevent instructions dependent on long-latency loads from clogging the common resources, a long-latency-load awared dispatch policy for SMT processors is proposed. This policy decides on whether a thread should be dispatch-stalled at the dispatch stage in the pipeline according to the detected or predicted L2 cache miss information. By preventing those long-latency-load dependents that have been fetched from clogging the common resources after detection of long-latency load, and reducing the feedback latency of the L2 cache miss information, it alleviates the negative influence brought to the resource sharing in SMT processor by long-latency loads.
(2)To address the problem of hiding long latency of off-chip access, a resource partitioning policy for SMT processors exploiting the compute-memory concurrency is proposed. It follows the essential feature of SMT processors that hide long latency by exploiting thread level parallelism, tunes the resource partitions among the threads periodically according to the concurrency level of compute-memory operations of each thread, and provides more resources to the thread that has better performance in compute-memory concurrency. This policy improves the proportion of time for concurrent compute-memory executing to the whole executing time, providing effective hiding of long latency brought by cache-miss loads.
(3)To avoid the stagnation in the suboptimal resource distribution spaces in the resource distribution optimization procedure, and enhance the capability of performing a continue optimization for resource distribution for changing program behavior, a spatially triggered dissipative resource distribution policy for SMT processors is proposed. In this policy, the self-organization mechanism cooperates with the spatially triggered chaos for the distribution solutions. By taking control of the similarity of the distribution solutions, the policy can escape from the suboptimal solution, and supply persistent optimization for resource distribution in different program phases. The throughput and fairness performance are both improved by taking only the throughput as the optimization target.
(4) A design model of non-critical path resource distributor for SMT processors is proposed, which separates the resource distribution module from the critical pipeline path to avoid the clock wastage caused by the computation on the allocation solutions. The asynchronous work mode of this non-critical path resource distributor is also meaningful for those implicit resource sharing control policies that consume obvious cycles in making decision.
引文
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