X型CPU内建自测试系统的设计与实现
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摘要
X微处理器是一款结构异常复杂的微处理器,它的内部包含有:Cache、微码ROM、指令预取部件和动态分支预测部件、指令译码部件、整数部件、多媒体部件、浮点部件、分段和分页部件、总线接口部件、双处理器接口部件、可编程中断控制部件等。对于一个结构如此复杂的微处理器,若要仅仅依靠外部测试得到预期的故障覆盖率,是一件非常困难的事,因此必须在芯片中增加内建自测试设计。
本文深入研究了目前国际上各种自测试设计技术和方法,根据X微处理器的特点和其对测试的具体需求,提出了一整套X微处理器的内建自测试设计方案。该方案充分考虑了X处理器的内部结构,有针对性的选择了一系列成熟可靠的自测试技术和方法,并充分利用X处理器所具有的处理能力和CPU特有的地址、数据总线及其调测试结构,在尽量少的硬件开销的前提下,提供了很高的测试覆盖率和故障覆盖率,很好的满足了X处理器对测试的需求。同时还具体实现了这套自测试方案,构造了完整的X处理器的自测试结构,应用于X处理器上并流片成功。
X微处理器的内建自测试分为结构自测试和微码程序自测试两阶段。在结构自测试阶段,对处理器的指令流通路、微码rom以及其它一些重要电路进行了测试;在微码程序自测试阶段,通过事先存储的微程序,对处理器指令部件、各功能部件以及各大型存储单元阵列进行了测试,同时实现了对处理器控制通路和数据通路的测试,从而使高达70%的硬件得到了覆盖;通过对自测试过程的精心组织以及自测试逻辑与芯片扫描结构的有效整合,为用户提供了非常方便的自测试使用和诊断手段。
X processor is a very much complex microprocessor, which contains Caches, microcode ROM, instruction prefetch unit, dynamic branch prediction unit, instruction decode unit, integer unit, multi media extension unit, floating point unit, segment and page management unit, bus unit, dual processor unit and APIC. For such a complex microprocessor, only relying on extern test to achieve desired fault coverage will be very impractical, thus, we must embed the built-in self logic in it to improve the processor's testability.
In this paper, based on the study of all kinds of BIST technologies and ways prevailing currently in the world, a scheme of the design of BIST oriented to the X microprocessor's features and specified test requirements is proposed. This scheme considers the internal structure of X microprocessor fully, as well as the processor's processing ability, address-data bus architecture and its debugging and testing logic. So this BIST design can provide very high test coverage and fault coverage at a very low hardware cost and meets the X processor's testing demand very well. And this BIST design has been realized on the X processor which has been tapped out and functions correctly.
The X processor's built-in self test is partitioned into two stages: structural BIST and microcode BIST. During structural BIST, the X processor's instruction flow path, microcode ROMs and some other important circuits are tested; during microcode BIST, the X processor's instruction unit, all function components and large memory arrays are tested by the microcode programs which have been stored in the microcode ROMs in advance, and processor's control path and data path are also tested at the same time. About 70 percent of the processor's logic is covered during BIST; by organizing the BIST process carefully and utilizing the processor's scan structure effectively, we provide a very convenient BIST use and diagnosis interface.
本文深入研究了目前国际上各种自测试设计技术和方法,根据X微处理器的特点和其对测试的具体需求,提出了一整套X微处理器的内建自测试设计方案。该方案充分考虑了X处理器的内部结构,有针对性的选择了一系列成熟可靠的自测试技术和方法,并充分利用X处理器所具有的处理能力和CPU特有的地址、数据总线及其调测试结构,在尽量少的硬件开销的前提下,提供了很高的测试覆盖率和故障覆盖率,很好的满足了X处理器对测试的需求。同时还具体实现了这套自测试方案,构造了完整的X处理器的自测试结构,应用于X处理器上并流片成功。
X微处理器的内建自测试分为结构自测试和微码程序自测试两阶段。在结构自测试阶段,对处理器的指令流通路、微码rom以及其它一些重要电路进行了测试;在微码程序自测试阶段,通过事先存储的微程序,对处理器指令部件、各功能部件以及各大型存储单元阵列进行了测试,同时实现了对处理器控制通路和数据通路的测试,从而使高达70%的硬件得到了覆盖;通过对自测试过程的精心组织以及自测试逻辑与芯片扫描结构的有效整合,为用户提供了非常方便的自测试使用和诊断手段。
X processor is a very much complex microprocessor, which contains Caches, microcode ROM, instruction prefetch unit, dynamic branch prediction unit, instruction decode unit, integer unit, multi media extension unit, floating point unit, segment and page management unit, bus unit, dual processor unit and APIC. For such a complex microprocessor, only relying on extern test to achieve desired fault coverage will be very impractical, thus, we must embed the built-in self logic in it to improve the processor's testability.
In this paper, based on the study of all kinds of BIST technologies and ways prevailing currently in the world, a scheme of the design of BIST oriented to the X microprocessor's features and specified test requirements is proposed. This scheme considers the internal structure of X microprocessor fully, as well as the processor's processing ability, address-data bus architecture and its debugging and testing logic. So this BIST design can provide very high test coverage and fault coverage at a very low hardware cost and meets the X processor's testing demand very well. And this BIST design has been realized on the X processor which has been tapped out and functions correctly.
The X processor's built-in self test is partitioned into two stages: structural BIST and microcode BIST. During structural BIST, the X processor's instruction flow path, microcode ROMs and some other important circuits are tested; during microcode BIST, the X processor's instruction unit, all function components and large memory arrays are tested by the microcode programs which have been stored in the microcode ROMs in advance, and processor's control path and data path are also tested at the same time. About 70 percent of the processor's logic is covered during BIST; by organizing the BIST process carefully and utilizing the processor's scan structure effectively, we provide a very convenient BIST use and diagnosis interface.
引文
[1]Essentials of Electronic Testing For Digital,Memory And Mixed-Signal VLSI Circuits,Kluwer Academic Publishers,2000
[2]曾芷德,数字系统测试与可测性,长沙:国防科技大学出版社,1992.12
[3]Johann,mairhofer,Hierarchical Self-Test Concept Based On The JTAG Standard,International Test Conference,1990:127-134
[4]Archambeau E C,Mccluskey E J,Fault Coverage Of Pseudo-Exhaustive Testing,FTCS-14,1984
[5]A.J.van de Goor,Testing Semiconductor Memories:Theory and Practice,New York:Wiley,1991
[6]S.Hamdioui and A.J.van de Goor,"An experiment analysis of spot defects in SRAMS:Realisticfault models and tests"in Proc,Asian Test Symp,2000,pp.131-138
[7]李晓维,并行反馈内置自测试设计方案,电子测试与仪器学报,1994.03,第八卷第一期
[8]S.W.Golomb,Shift Register Sequences,Aegean Park Press,Laguna Hills,Calif,1982
[9]T.Sridhar et al,"Analysis and Simulation of Parallel Signature Analyzers," Int'l J.Computers and Machematics with Applications,Vol13,No.5/6,Feb.1987,pp.537-545
[10]M.Nic01aidis,"Transparent BIST for RAMS,"in Proc.IEEE Int.Test Conf,1992,pp.598-607
[11]M.G.Karpovsky and V.N.Yarmolik,"Transparent memory BIST,"in Proc.IEEE Int.Workshop Memory Technology,Design and Testing,1994,pp.106-111
[12]D.C.Huang and W.B.Jone,"A Parallel Transparent BIST Method for Embedded Memory Arrays by Tolerating Redundant Operations,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and System,2002,pp.617-628
[13]Mitrajit Chatterjee and Dhiraj K.Pradhan,Fellow,IEEE,"A Bist Pattern Generator Design For Near-Perfect Fault Coverage",IEEE Transactions on Computers,2003.12,VOL.52,NO.12,pp.334-242
[14]Henk Hollmann,"Design of Test Sequences for VLSI Self-Testing Using LFSR",IEEE Transactions On Information Theory,1990.03,VOL.36,NO2,pp.254-235
[15]J.Bateson,In-Circuit Testing,New York:Van Nostrand Reinhold Company,1985
[16]R.Benciverrga,T.J.Chakraborty,and S.Davidson,"The Architecture of the Gentest Sequential Test Generator," in proc.Of the Custom Integrated Circuits Conf,1991,pp.17.11-17.1.4
[17]P.S.Bottorff,R.E.France,N.H.Garges,and E.J.Orosz,"Test Generation for Large Logic Networks," in proc.Of the 14th Design Automation Conf.,1997.06,pp.479-485
[18]刘明远,邵锦荣,数字IC可测性设计和测试生成技术,微电子学,1998,第28卷第5期,362-364
[19]张盛兵,高德远,NRS4000微处理器的可测性设计,西北工业大学学报,1999.08,第17卷第3期,344-349
[20]何蓉辉等,一款通用CPU的存储器内建自测试设计,同济大学学报,2002.10,第30卷第10期,1204-1208
[21]徐国强等,基于微处理器的可测性设计,计算机工程,2002,第28卷第9期,190-191
[22]叶波,郑增钰,并行BIST可测性设计,固体电子学研究与进展,1996,第16卷第2期,150-153
[23]朱小莉,陈迪平,王镇道,SRAM的一种可测性设计,湖南大学学报,2003,第30卷第6期,22-25
[24]IEEE Standard Test Access Port And Boundary-Scan Architecture,IEEE Std 1149.1-1990
[25]IEEE Standard.Supplement to IEEE Std.1149.1-1990,IEEE Standard test Access Port and Boundary-scan architecture.IEEE Std.1149.1b-1994,1995
[26]B.Ayari and B.Kaminska,"A New Dynamic Test Vector Compaction for Automatic Test Pattern Generation,"IEEE Trans.On Computer-Aided Design,1994.03,vol.13,no.3,pp.353-358
[27]A.Balivada,J.Chen,and J.A.Abraham,"Analog Testing with Time Response Parameters," IEEE Design and Test of Computers,1996.Summer,VOL.13,NO.2,pp.18-25
[28]S.Banerjee,S.T.Chakradhar and R.K.Roy,"Synchronous Test Generation Model for Asynchronous Circuits," in proc.Of the 9th International Conf.on VLSI Design,1996,pp.178-185
[29]P.H.Bardell,W.H.McAnney,and J.Savir,Built-In Test for VLSI:Pseudorandom Techniques,New York:John Wiley and Sons,Inc,1987
[30]F.Brglez,"On Testability Analysis of Combinational Networks,"in Proc.Of the International Symp.On Circuits and Systems,1984.05,pp.221-225
[31]J.A.Brzozowski and H.Jurgensen,"A Model for Sequential Machine Testing,"Research Report CS-88-12,U.of Waerloo,Dept.of Computer Science, 1998.04
[32] T.J.Chakraborty and V.D.Agrawal, "Robust Testing for Stuck-at Faults,"in proc. Of the 8th International Conf. on VLSI Design, 1995.02, pp.42-46
[33] S.GChappell,"Automatic Test Generation for Asynchronous Digital Circuits," Bell System Technical Journal, 1974.08, vol.53, no.8, pp.l477-1503
[34] LL.Lewyn and J.D.Meindl, "Physical Limits of VLSI DRAMS/TEEE Journal of solic-state Circuits, 1985.01, vol.SC-20, no.1, pp231-241
[35] M.Marinescu, "Simple and Efficient Algorithms for Functional RAM Testing,"in proc. Of the International Test Conf.,1982.11, pp.236-239
[36] P.Mazumder, "An Efficient Design of Embedded Memories and their Testability Analysis using Markov Chains," in Proc. Of the int'l.Conf on Wafer Scale Integration, 1989.01, pp.389-400
[37] P.Mazumder and J.H.Patel, "An Efficient Built-in Self-Testing for Random Access Memory,"in Proc. Of the International Test Conf, 1987.09, pp.1072-1077
[38] P.Mazumder and J.H.Patel, "Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories," IEEE Trans. On Computers, 1989, vol.C-38,no.3,pp.394-407
[39] R.F.M.Meershoek, "Functional and IDDQ Testing on a Static RAM/TUD Report 1-68340-28(1990)04, Dept. of Electrical Eng., Delft University of Technology, Delft/The Netherlands, 1990
[40] R.Nair, S.M.Thatte, and J.A.Abraham, "Efficient Algorithms for Testing semiconductor Random-Access Memories," IEEE Trans. On Computers, 1979.03, vol.C-28, no.3, pp.258-261
[41] M.Nicolaidis, "An Efficient Built-in Self-Test Scheme for Functional Test of Embedded Rams," in Proc. Of the IEEE fault Tolerant Computer Systems Conf.,1985,pp.ll8-123
[2]曾芷德,数字系统测试与可测性,长沙:国防科技大学出版社,1992.12
[3]Johann,mairhofer,Hierarchical Self-Test Concept Based On The JTAG Standard,International Test Conference,1990:127-134
[4]Archambeau E C,Mccluskey E J,Fault Coverage Of Pseudo-Exhaustive Testing,FTCS-14,1984
[5]A.J.van de Goor,Testing Semiconductor Memories:Theory and Practice,New York:Wiley,1991
[6]S.Hamdioui and A.J.van de Goor,"An experiment analysis of spot defects in SRAMS:Realisticfault models and tests"in Proc,Asian Test Symp,2000,pp.131-138
[7]李晓维,并行反馈内置自测试设计方案,电子测试与仪器学报,1994.03,第八卷第一期
[8]S.W.Golomb,Shift Register Sequences,Aegean Park Press,Laguna Hills,Calif,1982
[9]T.Sridhar et al,"Analysis and Simulation of Parallel Signature Analyzers," Int'l J.Computers and Machematics with Applications,Vol13,No.5/6,Feb.1987,pp.537-545
[10]M.Nic01aidis,"Transparent BIST for RAMS,"in Proc.IEEE Int.Test Conf,1992,pp.598-607
[11]M.G.Karpovsky and V.N.Yarmolik,"Transparent memory BIST,"in Proc.IEEE Int.Workshop Memory Technology,Design and Testing,1994,pp.106-111
[12]D.C.Huang and W.B.Jone,"A Parallel Transparent BIST Method for Embedded Memory Arrays by Tolerating Redundant Operations,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and System,2002,pp.617-628
[13]Mitrajit Chatterjee and Dhiraj K.Pradhan,Fellow,IEEE,"A Bist Pattern Generator Design For Near-Perfect Fault Coverage",IEEE Transactions on Computers,2003.12,VOL.52,NO.12,pp.334-242
[14]Henk Hollmann,"Design of Test Sequences for VLSI Self-Testing Using LFSR",IEEE Transactions On Information Theory,1990.03,VOL.36,NO2,pp.254-235
[15]J.Bateson,In-Circuit Testing,New York:Van Nostrand Reinhold Company,1985
[16]R.Benciverrga,T.J.Chakraborty,and S.Davidson,"The Architecture of the Gentest Sequential Test Generator," in proc.Of the Custom Integrated Circuits Conf,1991,pp.17.11-17.1.4
[17]P.S.Bottorff,R.E.France,N.H.Garges,and E.J.Orosz,"Test Generation for Large Logic Networks," in proc.Of the 14th Design Automation Conf.,1997.06,pp.479-485
[18]刘明远,邵锦荣,数字IC可测性设计和测试生成技术,微电子学,1998,第28卷第5期,362-364
[19]张盛兵,高德远,NRS4000微处理器的可测性设计,西北工业大学学报,1999.08,第17卷第3期,344-349
[20]何蓉辉等,一款通用CPU的存储器内建自测试设计,同济大学学报,2002.10,第30卷第10期,1204-1208
[21]徐国强等,基于微处理器的可测性设计,计算机工程,2002,第28卷第9期,190-191
[22]叶波,郑增钰,并行BIST可测性设计,固体电子学研究与进展,1996,第16卷第2期,150-153
[23]朱小莉,陈迪平,王镇道,SRAM的一种可测性设计,湖南大学学报,2003,第30卷第6期,22-25
[24]IEEE Standard Test Access Port And Boundary-Scan Architecture,IEEE Std 1149.1-1990
[25]IEEE Standard.Supplement to IEEE Std.1149.1-1990,IEEE Standard test Access Port and Boundary-scan architecture.IEEE Std.1149.1b-1994,1995
[26]B.Ayari and B.Kaminska,"A New Dynamic Test Vector Compaction for Automatic Test Pattern Generation,"IEEE Trans.On Computer-Aided Design,1994.03,vol.13,no.3,pp.353-358
[27]A.Balivada,J.Chen,and J.A.Abraham,"Analog Testing with Time Response Parameters," IEEE Design and Test of Computers,1996.Summer,VOL.13,NO.2,pp.18-25
[28]S.Banerjee,S.T.Chakradhar and R.K.Roy,"Synchronous Test Generation Model for Asynchronous Circuits," in proc.Of the 9th International Conf.on VLSI Design,1996,pp.178-185
[29]P.H.Bardell,W.H.McAnney,and J.Savir,Built-In Test for VLSI:Pseudorandom Techniques,New York:John Wiley and Sons,Inc,1987
[30]F.Brglez,"On Testability Analysis of Combinational Networks,"in Proc.Of the International Symp.On Circuits and Systems,1984.05,pp.221-225
[31]J.A.Brzozowski and H.Jurgensen,"A Model for Sequential Machine Testing,"Research Report CS-88-12,U.of Waerloo,Dept.of Computer Science, 1998.04
[32] T.J.Chakraborty and V.D.Agrawal, "Robust Testing for Stuck-at Faults,"in proc. Of the 8th International Conf. on VLSI Design, 1995.02, pp.42-46
[33] S.GChappell,"Automatic Test Generation for Asynchronous Digital Circuits," Bell System Technical Journal, 1974.08, vol.53, no.8, pp.l477-1503
[34] LL.Lewyn and J.D.Meindl, "Physical Limits of VLSI DRAMS/TEEE Journal of solic-state Circuits, 1985.01, vol.SC-20, no.1, pp231-241
[35] M.Marinescu, "Simple and Efficient Algorithms for Functional RAM Testing,"in proc. Of the International Test Conf.,1982.11, pp.236-239
[36] P.Mazumder, "An Efficient Design of Embedded Memories and their Testability Analysis using Markov Chains," in Proc. Of the int'l.Conf on Wafer Scale Integration, 1989.01, pp.389-400
[37] P.Mazumder and J.H.Patel, "An Efficient Built-in Self-Testing for Random Access Memory,"in Proc. Of the International Test Conf, 1987.09, pp.1072-1077
[38] P.Mazumder and J.H.Patel, "Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories," IEEE Trans. On Computers, 1989, vol.C-38,no.3,pp.394-407
[39] R.F.M.Meershoek, "Functional and IDDQ Testing on a Static RAM/TUD Report 1-68340-28(1990)04, Dept. of Electrical Eng., Delft University of Technology, Delft/The Netherlands, 1990
[40] R.Nair, S.M.Thatte, and J.A.Abraham, "Efficient Algorithms for Testing semiconductor Random-Access Memories," IEEE Trans. On Computers, 1979.03, vol.C-28, no.3, pp.258-261
[41] M.Nicolaidis, "An Efficient Built-in Self-Test Scheme for Functional Test of Embedded Rams," in Proc. Of the IEEE fault Tolerant Computer Systems Conf.,1985,pp.ll8-123