数模混合信号芯片的测试与可测性设计研究
摘要
随着集成电路设计与加工技术的飞速发展,集成电路复杂程度不断提高,而其尺寸却在不断缩小,超大规模集成电路(VLSI)的测试已经成为一个越来越困难的问题,特别是进入深亚微米工艺以及超高集成度发展阶段以来,通过集成各种IP核,系统级芯片(SOC)的功能越来越强大,但也带来一系列设计和测试问题。测试和可测性设计的理论与技术已经成为VLSI领域中的一个重要研究方向,它们在理论和实践中都有十分突出的价值。
本文从集成电路基本测试理论和测试方法开始,逐步深入地对系统级模数混合信号芯片的可测性进行研究。首先,对系统级芯片进行可测性分析,从基本的故障模型开始,对故障的分类、故障模拟、测试生成及其算法等方面进行初步的分析,然后对可测性设计进行深入的研究,包括扫描测试、边界扫描测试、内建自测试和IDDQ测试,并且使用FPGA芯片实现了一个BIST的例子,其包括测试向量发生器、被测内核和特征分析器。通过对被测内核注入故障,然后对正常电路和注入故障后的电路分别进行仿真来说明BIST的正确性和有效性。接着,对混合信号电路测试进行了专门的探讨,通过对模拟电路的仿真策略和混合信号的仿真策略进行比较来说明混合信号电路设计和仿真的困难性,并且对用来描述混合电路设计和仿真的VHDL-AMS语言进行介绍,指出用VHDL-AMS语言来设计的基本流程和VHDL-AMS中扩展的新概念,同时也介绍了混合信号测试总线1149.4标准在VLSI中的应用。本文最后介绍了DSP测试混合信号电路的原理,通过利用DSP测试DAC的具体方案来说明混合电路测试的方法,并且介绍了参与研发的基于DSP的集成电路及PCB板的智能测试仪器的软硬件设计。总之,具有低廉的测试成本、尽可能高的故障覆盖率和高度可靠的混合信号芯片的可测性设计方法将是系统级芯片进一步发展的要求。
With the rapid development of IC design and manufacturing technology, the complication of IC is increasing with its size decreasing, and the test of VLSI is becoming a more and more difficult problem. Specially, when entering the deep sub-micron processing technique and ultra high integrated period, vary IP cores are integrated, and the function of SOC is becoming more and more powerful, but it also brings out a series of design and testing problems. The theory and technology of testing and testable design have become an important research direction in VLSI field, and it is much more valuable in theory and practice.
This paper starts with the basic testing theory and method, and then gets a more deep research into the testability of system level mixed-signal chip. First, analysis of the system level chip testability is started from the basic fault model, and a primary analysis is made on fault classification, fault simulation, test generation and algorithm. Then a deeper research is made on testability of design, including scan test, boundary scan test, build in self test and IDDQ test. An example is also proposed to demonstrate BIST based on FPGA, including modules of test pattern generator, kernel circuit under test and feature analyzer. To demonstrate the correctness and efficiency of BIST, a fault is injected into a normal circuit, and then a simulation is performed on both the normal circuit and the circuit with fault injection. A special discussion on testing the mixed signal circuit is performed, and a comparison is carried out on the simulation strategy between analog circuit and mixed signal circuit to illustrate the difficulty in designing and simulating the mixed-signal circuit. Also, an introduction to the VHDL-AMS language is made, which is used to describe mixed signal design and its simulation, and the paper is also pointed out the basic design flow using VHDL-AMS and the extended new concept of VHDL-AMS. The application of 1149.4 standard of mixed signal test bus in VLSI is also introduced. Last, the paper introduces the mixed signal test theory based on DSP, and a detailed scheme of testing DAC based on DSP is offered. The paper also presents the hardware and software design of the auto test equipment based on DSP which can be used to test integrated circuit and PCB board.
In conclusion, the design method of testability for mixed-signal chip with lower cost, higher fault coverage and higher reliability is the demand of further development of system level chip.
本文从集成电路基本测试理论和测试方法开始,逐步深入地对系统级模数混合信号芯片的可测性进行研究。首先,对系统级芯片进行可测性分析,从基本的故障模型开始,对故障的分类、故障模拟、测试生成及其算法等方面进行初步的分析,然后对可测性设计进行深入的研究,包括扫描测试、边界扫描测试、内建自测试和IDDQ测试,并且使用FPGA芯片实现了一个BIST的例子,其包括测试向量发生器、被测内核和特征分析器。通过对被测内核注入故障,然后对正常电路和注入故障后的电路分别进行仿真来说明BIST的正确性和有效性。接着,对混合信号电路测试进行了专门的探讨,通过对模拟电路的仿真策略和混合信号的仿真策略进行比较来说明混合信号电路设计和仿真的困难性,并且对用来描述混合电路设计和仿真的VHDL-AMS语言进行介绍,指出用VHDL-AMS语言来设计的基本流程和VHDL-AMS中扩展的新概念,同时也介绍了混合信号测试总线1149.4标准在VLSI中的应用。本文最后介绍了DSP测试混合信号电路的原理,通过利用DSP测试DAC的具体方案来说明混合电路测试的方法,并且介绍了参与研发的基于DSP的集成电路及PCB板的智能测试仪器的软硬件设计。总之,具有低廉的测试成本、尽可能高的故障覆盖率和高度可靠的混合信号芯片的可测性设计方法将是系统级芯片进一步发展的要求。
With the rapid development of IC design and manufacturing technology, the complication of IC is increasing with its size decreasing, and the test of VLSI is becoming a more and more difficult problem. Specially, when entering the deep sub-micron processing technique and ultra high integrated period, vary IP cores are integrated, and the function of SOC is becoming more and more powerful, but it also brings out a series of design and testing problems. The theory and technology of testing and testable design have become an important research direction in VLSI field, and it is much more valuable in theory and practice.
This paper starts with the basic testing theory and method, and then gets a more deep research into the testability of system level mixed-signal chip. First, analysis of the system level chip testability is started from the basic fault model, and a primary analysis is made on fault classification, fault simulation, test generation and algorithm. Then a deeper research is made on testability of design, including scan test, boundary scan test, build in self test and IDDQ test. An example is also proposed to demonstrate BIST based on FPGA, including modules of test pattern generator, kernel circuit under test and feature analyzer. To demonstrate the correctness and efficiency of BIST, a fault is injected into a normal circuit, and then a simulation is performed on both the normal circuit and the circuit with fault injection. A special discussion on testing the mixed signal circuit is performed, and a comparison is carried out on the simulation strategy between analog circuit and mixed signal circuit to illustrate the difficulty in designing and simulating the mixed-signal circuit. Also, an introduction to the VHDL-AMS language is made, which is used to describe mixed signal design and its simulation, and the paper is also pointed out the basic design flow using VHDL-AMS and the extended new concept of VHDL-AMS. The application of 1149.4 standard of mixed signal test bus in VLSI is also introduced. Last, the paper introduces the mixed signal test theory based on DSP, and a detailed scheme of testing DAC based on DSP is offered. The paper also presents the hardware and software design of the auto test equipment based on DSP which can be used to test integrated circuit and PCB board.
In conclusion, the design method of testability for mixed-signal chip with lower cost, higher fault coverage and higher reliability is the demand of further development of system level chip.
引文
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[4] Andrew Grochowski,Debashis Bhattacharya,T.R.Viswanathan,etal, Ingegrated Circuit Testing for Quality Assurance in Manufacturing:History,Current Status, and Future Trends. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEM-II: ANALOG AND DIGITAL SIGNAL PROCESSING, 1997,44(8):610-633
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[6] Michael L. Bushnell, Vishwani D. Agrawal.Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits.First Edtion.New York:Kluwer Academic Publishers,2002,57-248
[7] JOHN W. BANDLER, ALY E. SALAMA. Fault Diagnosis of Analogue Circuits. PROCEEDINGS OF THE IEEE, 1985,73(8),1279-1325
[8] Miron Abramovici,Melvin A. Breuer,Arthur D. Friedman.数字系统测试与可测性设计.李华伟,鲁巍.第一版.北京:机械工业出版社,2006,7-328
[9] Niraj Jha,Sandeep Gupta.数字系统测试.王新安,蒋安平,宋春殚.第一版.北京:电子工业出版社,2007,1-244
[10] 时万春.现代集成电路测试技术.第一版.北京:化学工业出版社,2006,1-252
[11] 雷绍充,邵志标,梁峰.VLSI 测试方法学和可测性设计.第一版.北京:电子工业出版社,2005,10-243
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[13] 王志华,邓仰东.数字集成系统的结构化设计与高层次综合.第一版.北京:清华大学出版社,2000,321-323
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[16] 胡 瑜 , 韩 银 和 , 李 晓 维 .SOC 可 测 性 设 计 与 测 试 技 术 . 计 算 机 研 究 与 发展,2005,42(1):153-162
[17] 曾繁泰,候亚宁,崔元明.可编程器件应用导论. 第一版.北京:清华大学出版社,2001,207-238
[18] 成立,王振宇,高平等 .VLSI 电路可测性设计技术及其应用综述.半导体技术,2004,29(5):20-34
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[20] Alexander Miczo.Digital Loigc Testing and Simulation.Second Edition.New Jersey:John Wiley&Sons,Inc,2003,33-444
[21] 刘 勇 .VLSI 测 试 中 移 相 伪 随 机 序 列 的 设 计 . 电 子 科 技 大 学 学报,2002,31(6):608-611
[22] Janusz Rajski,Jerzy Tyszer.Arithmetic Built-in Self-Test for Embedde Systems.First Edition.USA:Prentice Hall,1997,1-81
[23] Steve Kilts. Advanced FPGA Design: Architecture, Implementation, and Optimization.First Edition.New Jersey: John Wiley & Sons,Inc,2007,151-195
[24] Mark Zwolinski.Digital System Design with VHDL.First Edition.Southampton: Pearson Education Limited,1999,165-256
[25] 鲍信茹,汪志伟,李文石.IDDQ 测试原理及案例.中国集成电路,2006,(9):74-30
[26] Mark Burns, Gordon W.Roberts.An Introduction to Mixed-Signal IC Test and Measurement. First Edition. Oxford New York: Oxford University Press, 2001,123-184
[27] B.K.S.V.L.Varaprasad,Lalit Mohan Patnaik,Hirisave S. Jamadagni,etal,A New ATPG Technique(MultiDetect) for Testing of Analog Macros in Mixed-Signal Circuits.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2004,23(2):273-286
[28] Sunil R.Das,Jila Zakizadeh,Satyendra Biswas,etal,Testing Analog and Mixed-Signal Circuits With Built-In Hardware-A New Approach.IEEE TRANSATIONS ON INSTRUMENTATION AND MEASUREMENT,2007,56(3): 840-852
[29] 徐卫林,何怡刚,厉芸.数模混合信号的测试与仿真.现代电子技术,2004,(22):80-93
[30] 刘 全 喜 , 何 怡 刚 , 刘 美 容 等 .SoC 中 混 合 信 号 的 测 试 . 现 代 电 子 技术,2006,(3):94-98
[31] 韩泽耀 ,叶润涛 .模拟 /混合信号硬件描述语言 VHDL-AMS 综述 .微电子学,2001,31(2):83-84
[32] 张俊涛,徐丹旸,于海勋.数模混合电路的 VHDL 建模与仿真分析. 陕西科技大学学报,2004,22(6):57-60
[33] 林传骝.P1149.4 混合信号测试、总线综述.国外电子测量技术,1998,(5):6-8
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[35] 李 正 光 , 雷 加 .IEEE1149.4 测 试 系 统 的 研 究 与 设 计 . 计 算 机 工 程 与 应用,2004,(6):128-134
[36] IEEE-Std-1149.4-1999 IEEE Standard for a Mixed Signal Test Bus.New York:The Institute of Electrical and Electronics Engineers,Inc.1999,1-84
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[38] 李杰,杨军,李锐等.一种实现数模混合电路中 ADC 测试的 BIST 结构.微电子学,2004,34(4):467-468
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[40] 唐玉兰,陶伟,于宗光.一种实现数模混合电路中 DAC 测试的 BIST 结构.电子器件,2006,29(1):231-234
[41] 杨剑,贾冲,杨吉斌.基于 DSP 同步串口的异步串行通信接口的设计与实现.电子技术应用,2006,(1):112-117
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[2] 杨士元,童诗白.模拟系统的故障诊断与可靠性设计.第一版.北京:清华大学出版社,2001,1-7
[3] 杨士元 .数字系统的故障诊断与可靠性设计 .第二版 ,北京 :清华大学出版社,2000,10-15
[4] Andrew Grochowski,Debashis Bhattacharya,T.R.Viswanathan,etal, Ingegrated Circuit Testing for Quality Assurance in Manufacturing:History,Current Status, and Future Trends. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEM-II: ANALOG AND DIGITAL SIGNAL PROCESSING, 1997,44(8):610-633
[5] Prakash Rashinkar,Peter Paterson,Leena Singh.System-on-a-Chip Verification Methodology and Techniques.First Edition.New York:Kluwer Academic Publishers,2002,129-232
[6] Michael L. Bushnell, Vishwani D. Agrawal.Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits.First Edtion.New York:Kluwer Academic Publishers,2002,57-248
[7] JOHN W. BANDLER, ALY E. SALAMA. Fault Diagnosis of Analogue Circuits. PROCEEDINGS OF THE IEEE, 1985,73(8),1279-1325
[8] Miron Abramovici,Melvin A. Breuer,Arthur D. Friedman.数字系统测试与可测性设计.李华伟,鲁巍.第一版.北京:机械工业出版社,2006,7-328
[9] Niraj Jha,Sandeep Gupta.数字系统测试.王新安,蒋安平,宋春殚.第一版.北京:电子工业出版社,2007,1-244
[10] 时万春.现代集成电路测试技术.第一版.北京:化学工业出版社,2006,1-252
[11] 雷绍充,邵志标,梁峰.VLSI 测试方法学和可测性设计.第一版.北京:电子工业出版社,2005,10-243
[12] 曾平英,李兆麟,毛志刚.ASIC 可测性设计技术.微电子学,1999,29(3):149-153
[13] 王志华,邓仰东.数字集成系统的结构化设计与高层次综合.第一版.北京:清华大学出版社,2000,321-323
[14] 王永生 ,肖立伊 ,毛志刚等 .SOC 可测试性设计技术 .同济大学学报 ,2002,30(10):1272-1276
[15] 刘丽华,辛德禄,李本俊.专用集成电路设计方法.第一版.北京:北京邮电大学出版社,2000,200-202
[16] 胡 瑜 , 韩 银 和 , 李 晓 维 .SOC 可 测 性 设 计 与 测 试 技 术 . 计 算 机 研 究 与 发展,2005,42(1):153-162
[17] 曾繁泰,候亚宁,崔元明.可编程器件应用导论. 第一版.北京:清华大学出版社,2001,207-238
[18] 成立,王振宇,高平等 .VLSI 电路可测性设计技术及其应用综述.半导体技术,2004,29(5):20-34
[19] 于云华,石寅.数字集成电路故障测试策略和技术的研究进展.电路与系统学报,2004,9(3):83-91
[20] Alexander Miczo.Digital Loigc Testing and Simulation.Second Edition.New Jersey:John Wiley&Sons,Inc,2003,33-444
[21] 刘 勇 .VLSI 测 试 中 移 相 伪 随 机 序 列 的 设 计 . 电 子 科 技 大 学 学报,2002,31(6):608-611
[22] Janusz Rajski,Jerzy Tyszer.Arithmetic Built-in Self-Test for Embedde Systems.First Edition.USA:Prentice Hall,1997,1-81
[23] Steve Kilts. Advanced FPGA Design: Architecture, Implementation, and Optimization.First Edition.New Jersey: John Wiley & Sons,Inc,2007,151-195
[24] Mark Zwolinski.Digital System Design with VHDL.First Edition.Southampton: Pearson Education Limited,1999,165-256
[25] 鲍信茹,汪志伟,李文石.IDDQ 测试原理及案例.中国集成电路,2006,(9):74-30
[26] Mark Burns, Gordon W.Roberts.An Introduction to Mixed-Signal IC Test and Measurement. First Edition. Oxford New York: Oxford University Press, 2001,123-184
[27] B.K.S.V.L.Varaprasad,Lalit Mohan Patnaik,Hirisave S. Jamadagni,etal,A New ATPG Technique(MultiDetect) for Testing of Analog Macros in Mixed-Signal Circuits.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2004,23(2):273-286
[28] Sunil R.Das,Jila Zakizadeh,Satyendra Biswas,etal,Testing Analog and Mixed-Signal Circuits With Built-In Hardware-A New Approach.IEEE TRANSATIONS ON INSTRUMENTATION AND MEASUREMENT,2007,56(3): 840-852
[29] 徐卫林,何怡刚,厉芸.数模混合信号的测试与仿真.现代电子技术,2004,(22):80-93
[30] 刘 全 喜 , 何 怡 刚 , 刘 美 容 等 .SoC 中 混 合 信 号 的 测 试 . 现 代 电 子 技术,2006,(3):94-98
[31] 韩泽耀 ,叶润涛 .模拟 /混合信号硬件描述语言 VHDL-AMS 综述 .微电子学,2001,31(2):83-84
[32] 张俊涛,徐丹旸,于海勋.数模混合电路的 VHDL 建模与仿真分析. 陕西科技大学学报,2004,22(6):57-60
[33] 林传骝.P1149.4 混合信号测试、总线综述.国外电子测量技术,1998,(5):6-8
[34] 胡 政 , 温 熙 森 , 杨 拥 民 . 数 模 混 合 信 号 测 试 总 线 -IEEE P1149.4. 微 电 子 测试,1997,011(002):40-43
[35] 李 正 光 , 雷 加 .IEEE1149.4 测 试 系 统 的 研 究 与 设 计 . 计 算 机 工 程 与 应用,2004,(6):128-134
[36] IEEE-Std-1149.4-1999 IEEE Standard for a Mixed Signal Test Bus.New York:The Institute of Electrical and Electronics Engineers,Inc.1999,1-84
[37] IEEE-std-1149.1-2001 IEEE Standard Test Access Port and Boundary-Scan Architecture.the United States of America New York:The Institute of Electrical and Electronics Engineers,Inc.2001,1-208
[38] 李杰,杨军,李锐等.一种实现数模混合电路中 ADC 测试的 BIST 结构.微电子学,2004,34(4):467-468
[39] 成立,李加元,王振宇等.用于混合信号系统的模/数分块一体化测试技术.半导体技术,2006,31(2):128-134
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