X型DSP程序寻址部件的设计与实现
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摘要
本课题参与研制的X型DSP是一款高性能、低功耗的16位定点数字信号处理器芯片。它采用改进的哈佛结构(一条程序存储器总线、3条数据存储器总线和4条地址总线),CPU内核整合了算术逻辑运算单元ALU、乘累加单元MAC、比较＼选择＼存储单元CSSU、指数编码器EXP等功能部件,片上集成大量的存储器和丰富的外设,采用高度专业化的指令集,这都使得X型DSP特别适合于嵌入式应用。
本课题采用0.18μmCMOS工艺,采用全定制的方法,设计并实现了X型DSP的程序寻址部件,并对其进行了全面的系统级验证和分析。本课题研究的主要内容和成果包括以下几个方面：
1、本文在深入研究了X型DSP指令集和体系结构的基础上,并根据X型DSP处理器的总体设计要求,确定了程序寻址部件的总体结构。
2、采用自顶向下、逐级细化的方法对程序寻址部件进行模块划分,并采用全定制的方法对各模块进行了设计。其中对关键模块还进行了电路级优化和性能分析,并对各种程序寻址操作的实现原理也做了详细分析。
3、在模块级验证全部通过的基础上,对X型DSP的程序寻址部件进行了全芯片系统级的功能验证,验证结果表明该部件的设计完全满足X型DSP的设计要求。
X型DSP处理器已经投片成功,完全满足了设计要求,也证明了作为其重要控制部件——程序寻址部件的正确性。
The X-DSP is a high performance and low power 16-bit fixed-point digital signal processor. It combines an advanced modified Harvard architecture (with one program memory bus, three data memory buses, and four address buses), a CPU core with arithmetic/logic unit(ALU), multiply/accumulate unit(MAC), compare/select/store unit(CSSU), exponent encoder(EXP) and otherwise application-specific hardware logic, on-chip memory, on-chip peripherals, a highly specialized instruction set, and all these make X-DSP being fit for embed application.
With 0.18μm CMOS technology and full custom design method, I have designed and realized the program-addressing unit of the X-DSP and given a thorough simulation and analysis. The main content and production of this paper are showed as follows.
1. Analyze and research the instruction set and architecture of X-DSP processor, and design the architecture of program-addressing component according to system design rule of X-DSP processor.
2. Use the top-down tactic to divide the program-addressing unit to hiberarchy modules,and use full custom design method to design and realize these modules. Especially, optimized some pivotal modules at circuit level and gave a capability analyse of them, and also explained the elements of all program-addressing operations detailedly.
3. Verify the function of program-addressing unit in entire chip circumstance based on the module simulation passed. The result showed that the program-addressing unit this paper designed achieved the project's objective of X-DSP absolutely.
X-DSP processor has been taped out successfully, and it can completely satisfy the request of design. Finally, the result proves that the program-addressing unit works correctly as the important control unit.
本课题采用0.18μmCMOS工艺,采用全定制的方法,设计并实现了X型DSP的程序寻址部件,并对其进行了全面的系统级验证和分析。本课题研究的主要内容和成果包括以下几个方面：
1、本文在深入研究了X型DSP指令集和体系结构的基础上,并根据X型DSP处理器的总体设计要求,确定了程序寻址部件的总体结构。
2、采用自顶向下、逐级细化的方法对程序寻址部件进行模块划分,并采用全定制的方法对各模块进行了设计。其中对关键模块还进行了电路级优化和性能分析,并对各种程序寻址操作的实现原理也做了详细分析。
3、在模块级验证全部通过的基础上,对X型DSP的程序寻址部件进行了全芯片系统级的功能验证,验证结果表明该部件的设计完全满足X型DSP的设计要求。
X型DSP处理器已经投片成功,完全满足了设计要求,也证明了作为其重要控制部件——程序寻址部件的正确性。
The X-DSP is a high performance and low power 16-bit fixed-point digital signal processor. It combines an advanced modified Harvard architecture (with one program memory bus, three data memory buses, and four address buses), a CPU core with arithmetic/logic unit(ALU), multiply/accumulate unit(MAC), compare/select/store unit(CSSU), exponent encoder(EXP) and otherwise application-specific hardware logic, on-chip memory, on-chip peripherals, a highly specialized instruction set, and all these make X-DSP being fit for embed application.
With 0.18μm CMOS technology and full custom design method, I have designed and realized the program-addressing unit of the X-DSP and given a thorough simulation and analysis. The main content and production of this paper are showed as follows.
1. Analyze and research the instruction set and architecture of X-DSP processor, and design the architecture of program-addressing component according to system design rule of X-DSP processor.
2. Use the top-down tactic to divide the program-addressing unit to hiberarchy modules,and use full custom design method to design and realize these modules. Especially, optimized some pivotal modules at circuit level and gave a capability analyse of them, and also explained the elements of all program-addressing operations detailedly.
3. Verify the function of program-addressing unit in entire chip circumstance based on the module simulation passed. The result showed that the program-addressing unit this paper designed achieved the project's objective of X-DSP absolutely.
X-DSP processor has been taped out successfully, and it can completely satisfy the request of design. Finally, the result proves that the program-addressing unit works correctly as the important control unit.
引文
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[2]G. Yeap. Practical Low Power Digital VLSI Design. Kluwer Academic Publishers, USA,1998.4
[3]Sung-Mo Kang. Elements of Low Power Design for Integrated Systems, International Symposium on Low Power Electronics and Design,2003.5:205-210
[4]A.P.Chandrakasan, S.Sheng, R.W.Brodersen. Low-Power CMOS Digital Design. IEEE Journal of Solid-StatCircuit,1992.6(27):473-483
[5]Montanaro J, Witek R T, Anne K, et al. A 160-MHZ,32-bit,0.5-W CMOS RISC microprocessor. IEEE J Sol Sta Circ,1996.3 (11):1703-1714
[6]李思昆,曾献君,郭阳.VLSI设计方法学.长沙：国防科技出版社,2002.4
[7]Texas Instruments Incorporated. TMS320VC54x系列DSP的CPU与外设.北京：清华大学出版社,2005.12
[8]David A Hodges, Horace G. Jackson, Ressve A.Saleh. Analysis and Design of Digital Integrated Circuits In Deep Submicron Technology Third Edition.北京：电子工业出版社,2005.9
[9]Neil H.E, Weste David Harris. CMOS VLSI Design:A Circuits and Systems Perspective (3rd Edition). Addison Wesley,2004.5
[10]梁斌,孙永节,微处理器系统级验证平台的研究.中国计算机学会第八届计算机工程与工艺学术年会,2003.8(8)：168-172
[11]Neil H E West, Kerman Eshraghian. Principle Of CMOS VLSI Desig.机械工业出版社,1999.10
[12]John L Hennessy, David. A patterson. Computer Architecture:A Quantitative Approach. 北京:机械工业出版社,1999.6
[13]张晨曦,王志英,张春元,戴葵.计算机体系结构.北京：高等教育出版社,2000.2
[14]邹彦.DSP原理及应用.北京：电子工业出版社,2006.8
[15]Michael Keating, Pierre Bricaud. Reuse Methodology Manual:For System-on-a-Chip Design(Third Edition). Boston/Dordrecht/London:Kluwer Academic Publishers,2002.10
[16]N. Kranitis, GXenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian. Low-Cost Software-Based Self-Testing of RISC Processor Cores. IEEE, DATE'2003, Munich, Germany,2003.3
[17]N.Kranitis, D.Gizopoulos, A.Paschalis, Y.Zorian. Instruction-Based Self-Testing of Processor Cores. IEEE VLSI Test Symposium 2002 (VTS'2002), Monterey, CA, USA,2002.4
[18]Glenn Reinmany, Todd Austinz, Brad Calde. A Scalable Front-End Architecture for Fast Instruction Delivery. Published in the Proceedings of the 26th International Symposium on Computer Architecture,1999.5
[19]K.Chakrabarty, A.Chandra. Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip.38th Conference on Design Automation (DAC'O1),2001
[20]B.Curran, B.McCredie, L.Sigal, E.Schwarz.4GHz Low-Latency Fixed-Point and Binary Floating-point Execution Units for the POWER6 Processor. IEEE International Solid-State Circuits Conference(ISSCC),2006.2:436-437
[21]Michael John Sebastian smith著,虞惠华,汤庭鳌,来金梅,孙承绶等译.专用集成电路.电子工业出版社,2007
[22]Viji Srinicasan, David Brooks, Mickael Gschwind, Pradip Bose. Optimizing Pipelines for Power and Performance.35th Annual IEEE/ACM International Symposium on Microarchitecture,2002:333-344
[23]N.Zhaung, H.Wu. A new design of the CMOS full-adder. IEEE Journal of Solid State Circuits,1992(27):840-844
[24]Nei H.E.Weste, David Harris著,汪东,李振涛,毛二坤,李宝锋等译.CMOS VLSI Design a Circuits and Systems perspective(third Edition).中国电力出版社,2006
[25]Michael D.Ciletti. Advanced Digital Design with the Verilog HDL.北京：电子工业出版社,2005.1
[26]J. M. Rabaey, M. Pedram. Low Power Design Methodologies. Kluwer Academic Publ ishers,1996.6
[27]Synopsys Inc. Managing Power in Ultra Deep Submicron ASIC/IC Design. Synopsys White Paper,2002.5
[28]李伟华VLSI设计基础.电子工业出版社,2002.5
[29]唐冬,宁志刚.DSP原理及应用.北京：电子工业出版社,2005.6
[30]夏宇闻.复杂数字电路与系统的Verilog HDL设计技术.北京：北京航空航天大学出版社,1998.2
[31]周明德,蒋本珊.微机原理与接口技术.北京：人民邮电出版社,2002.10
[2]G. Yeap. Practical Low Power Digital VLSI Design. Kluwer Academic Publishers, USA,1998.4
[3]Sung-Mo Kang. Elements of Low Power Design for Integrated Systems, International Symposium on Low Power Electronics and Design,2003.5:205-210
[4]A.P.Chandrakasan, S.Sheng, R.W.Brodersen. Low-Power CMOS Digital Design. IEEE Journal of Solid-StatCircuit,1992.6(27):473-483
[5]Montanaro J, Witek R T, Anne K, et al. A 160-MHZ,32-bit,0.5-W CMOS RISC microprocessor. IEEE J Sol Sta Circ,1996.3 (11):1703-1714
[6]李思昆,曾献君,郭阳.VLSI设计方法学.长沙：国防科技出版社,2002.4
[7]Texas Instruments Incorporated. TMS320VC54x系列DSP的CPU与外设.北京：清华大学出版社,2005.12
[8]David A Hodges, Horace G. Jackson, Ressve A.Saleh. Analysis and Design of Digital Integrated Circuits In Deep Submicron Technology Third Edition.北京：电子工业出版社,2005.9
[9]Neil H.E, Weste David Harris. CMOS VLSI Design:A Circuits and Systems Perspective (3rd Edition). Addison Wesley,2004.5
[10]梁斌,孙永节,微处理器系统级验证平台的研究.中国计算机学会第八届计算机工程与工艺学术年会,2003.8(8)：168-172
[11]Neil H E West, Kerman Eshraghian. Principle Of CMOS VLSI Desig.机械工业出版社,1999.10
[12]John L Hennessy, David. A patterson. Computer Architecture:A Quantitative Approach. 北京:机械工业出版社,1999.6
[13]张晨曦,王志英,张春元,戴葵.计算机体系结构.北京：高等教育出版社,2000.2
[14]邹彦.DSP原理及应用.北京：电子工业出版社,2006.8
[15]Michael Keating, Pierre Bricaud. Reuse Methodology Manual:For System-on-a-Chip Design(Third Edition). Boston/Dordrecht/London:Kluwer Academic Publishers,2002.10
[16]N. Kranitis, GXenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian. Low-Cost Software-Based Self-Testing of RISC Processor Cores. IEEE, DATE'2003, Munich, Germany,2003.3
[17]N.Kranitis, D.Gizopoulos, A.Paschalis, Y.Zorian. Instruction-Based Self-Testing of Processor Cores. IEEE VLSI Test Symposium 2002 (VTS'2002), Monterey, CA, USA,2002.4
[18]Glenn Reinmany, Todd Austinz, Brad Calde. A Scalable Front-End Architecture for Fast Instruction Delivery. Published in the Proceedings of the 26th International Symposium on Computer Architecture,1999.5
[19]K.Chakrabarty, A.Chandra. Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip.38th Conference on Design Automation (DAC'O1),2001
[20]B.Curran, B.McCredie, L.Sigal, E.Schwarz.4GHz Low-Latency Fixed-Point and Binary Floating-point Execution Units for the POWER6 Processor. IEEE International Solid-State Circuits Conference(ISSCC),2006.2:436-437
[21]Michael John Sebastian smith著,虞惠华,汤庭鳌,来金梅,孙承绶等译.专用集成电路.电子工业出版社,2007
[22]Viji Srinicasan, David Brooks, Mickael Gschwind, Pradip Bose. Optimizing Pipelines for Power and Performance.35th Annual IEEE/ACM International Symposium on Microarchitecture,2002:333-344
[23]N.Zhaung, H.Wu. A new design of the CMOS full-adder. IEEE Journal of Solid State Circuits,1992(27):840-844
[24]Nei H.E.Weste, David Harris著,汪东,李振涛,毛二坤,李宝锋等译.CMOS VLSI Design a Circuits and Systems perspective(third Edition).中国电力出版社,2006
[25]Michael D.Ciletti. Advanced Digital Design with the Verilog HDL.北京：电子工业出版社,2005.1
[26]J. M. Rabaey, M. Pedram. Low Power Design Methodologies. Kluwer Academic Publ ishers,1996.6
[27]Synopsys Inc. Managing Power in Ultra Deep Submicron ASIC/IC Design. Synopsys White Paper,2002.5
[28]李伟华VLSI设计基础.电子工业出版社,2002.5
[29]唐冬,宁志刚.DSP原理及应用.北京：电子工业出版社,2005.6
[30]夏宇闻.复杂数字电路与系统的Verilog HDL设计技术.北京：北京航空航天大学出版社,1998.2
[31]周明德,蒋本珊.微机原理与接口技术.北京：人民邮电出版社,2002.10