LAWCA宇宙线实验触发电子学研究
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摘要
为了探寻更多的甚高能伽马射线源,经过长期的调查、论证、研究、仿真,最终决定将进行LAWCA实验的建设。LAWCA实验探测器阵列由900个光电倍增管组成,这900个光电倍增管分布在150m×150m的范围内。每3×3个光电倍增管形成一组,通过一个前端电子学(Front End Electronics, FEE)模块将其输出信号的时间及电荷信息进行数字化并读出。
由于宇宙线本底等影响,将给本实验部署的900个光电倍增管探测器带来许多不必要的冗余及噪声信号。为了避免这些冗余信号给系统带来的额外处理压力和资源消耗,希望通过电子学的手段将这些无效信息加以剔除,此即本论文中研究的触发电子学的目标。由于宇宙线簇射的现象十分复杂,从而对触发电子学的灵活性提出了很高的要求。在本论文的研究过程中,对于国际上其他一些采用了大规模水切伦科夫探测器阵列的实验进行了调研,了解其物理目标、探测器分布及触发电子学结构。除此之外,对于近来在对撞机物理实验中兴起的无硬件触发结构的全数据读出数据获取方案也进行了相关调研。
在以上调研的基础上,根据LAWCA实验自身的特点及需求,提出了基于硬件实时触发判选的全数据读出方案设计。该方案中采用单片大容量、高性能现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)作为触发判选的核心器件,通过基于光纤的高速串行通信方式将来自前端电子学模块的完整数据全部集中到此核心触发FPGA中。在核心触发FPGA内部提取出数据的特征信息进行触发判选,最后采用基于千兆以太网的网络通信方式将判选后的有效数据传输至DAQ系统。这种方案省去了传统触发电子学结构向前端反馈触发信号线的过程,简化了系统；由于触发电子学能够获得前端电子学的全部完整数据,大大地提高了触发算法设计的灵活性,能更好地提高触发效率；通过对FPGA内部触发判选逻辑的重配置,使得可重构的触发电子学的实现称为可能。这种基于硬件实时触发判选的全数据读出结构具有以下两个明显优势：
一、所有前端电子学的完整数据全部汇总到触发判选模块中,使得更多的事例信息能够参与到触发判选中去,大大提高了触发模式设计的灵活性。同时可针对完整的事例信息设计各种处理方式,实现可重构的触发判选。
二、这种结构省去了触发信号向各个前端电子学模块回馈的过程,从而简化了系统结构,有利于提高系统稳定性。
在这样的触发电子学结构方案下,进行了相应的LAWCA实验触发电子学原型验证系统的设计。该原型验证系统既可用以验证触发电子学方案设计的正确性及可行性,也可作为未来触发电子学进行工程化时的一个良好技术基础。此原型验证系统采用单片大容量Xilinx Virtex-6系列XC6VLX365T FPGA作为触发判选的核心器件,并围绕其设计了与10个时钟分发及数据传输插件间的高速串行数据传输通道,其单路数据传输率为1.25Gbps。以此实现对于5.4Gbps系统平均数据率的汇总及实时缓存与触发判选。采用了Xilinx Virtex-5系列XC5VFX70T FPGA及相应的物理层芯片实现了两路基于千兆以太网的判选后有效数据读出通道。此原型验证系统通过VME总线来接收来自上位机的控制命令并反馈状态信息等,并可通过VME总线进行核心FPGA的在线重配置。通过这些技术手段,实现了触发电子学方案中的相应设计要求。
随后,根据目前基本触发模式的要求,进行了触发判选功能的算法与FPGA逻辑设计。在本文中介绍了其中采用的诸如延时方式实现多数据传输通道间的数据同步、分区缓存实现触发数据读出的2μs读出时间窗口等多种方法。以及对于多种触发判选逻辑工作模式的支持和一些触发判选算法中用到参数的在线动态调整配置方法。
为了验证触发电子学原型验证系统及相应的触发判选逻辑设计,物理学家给出了一些模拟数据来进行测试。在测试中,首先使用了MATLAB以基本触发模式的要求对模拟数据进行软件的触发判选,随后将模拟数据导入到触发模块中进行硬件的触发判选,最后将二者的结果进行比较,发现结果完全一致。这表明触发判选逻辑的设计完全符合我们对基本触发模式的建模结果。同时,还进行了眼图、误码率、数据丢包率等数据传输接口的相关测试,并对测试结果做了相应的分析。对于反映出设计存在不足的测试结果,也讨论了潜在的一些改善方案和未来进一步的改进设计。
在本论文的最后,总结了对于LAWCA实验触发电子学方案及原型验证系统的相关研究工作,并针对LAWCA实验下一步可能的探测器布局改动提出了相应的设计思路。同时对于实现TCP协议数据传输的可能设计改进方案也进行了一些探讨。
The Large Area Water Cherenkov Array (LAWCA) aims at the physical target of gamma astronomy at high energies. The LAWCA detector consists of900Photon Multiplier Tubes (PMTs) which are scattered in a150×150m2area. Every3×3PMTs form a group and their outputs are fed to one Front End Electronic (FEE) module for time and charge information measurement.
The data generated by FEE consists of valid signals and background noises. To eject the noises, the trigger electronics is demanded.Due to the complicated phenomena of cosmic ray showers, the flexibility of the trigger electronics must be guaranteed. During this research, we have made an investigation of the trigger electronics in other Water Cherenkov experiments. We also studied the "triggerless" total data readout method in the collider experiments.
Invoked by the idea of hardware triggerless architecture and based on our survey, a scheme of LAWCA trigger electronics is designed with all data transferred to a trigger module for processing. In the trigger module, one single FPGA device is employed to carry out the real-time trigger processing.Compared with traditional trigger electronics receiving only part of the data from front end, much more detailed information can be utilized to achieve a better trigger flexibility. It also eliminates the need of trigger signals fed back to front end; thus better system simplicity can be accomplished. Based on the abundant programmable inner connections and logic resources in the FPGA, reconfigurable trigger electronics can be realized; meanwhile, the trigger algorithms can be upgraded online with future modifications. Besides, because a large part of fake events can be rejected by the trigger electronics, the requirement on DAQ is significantly reduced.
Based on this scheme, a prototype of LAWCA trigger electronics is implemented. It could verify the correctless of this scheme and it could also be recognized as a good technical foundation for future engineering. A high capacity Xilinx Virtex-6series FPGA XC6VLX365T is adopted as the kernel device for trigger and data selection.10fiber based serial transmission channels are built; each supports a data transmission rate at1.25Gbps to accommodate the5.4Gbps system average data rate.The Gigabit Ethernet interface, which is used for triggered data transmission, is implemented with virtex-5XC5VFX70T FPGA and corresponding PHY chip. The online reconfiguration of this prototype is realized base on the VME bus. With these techniques, the requirements of the trigger electronics are met.
This trigger electronics prototype is designed and evaluated based on a basic trigger pattern. According to this basic trigger pattern, the trigger algorithm and FPGA logic is developed. And then some initial tests are also carried out. Simulation data generated by physicists is imported to verify the correctless of the trigger processing logic. The simulation data is processed by MATLAB and the prototype independently. The results from these two are fully matched, which indicates that the prototype functions well with the trigger logic strictly following the expected trigger pattern.
In the final chapter, the scheme and prototype research on the LAWCA trigger electronics is concluded. Some discussions about the future detector array layout modification are given. Some improved schemes on the TCP based Ethernet data transmission are also presented.
由于宇宙线本底等影响,将给本实验部署的900个光电倍增管探测器带来许多不必要的冗余及噪声信号。为了避免这些冗余信号给系统带来的额外处理压力和资源消耗,希望通过电子学的手段将这些无效信息加以剔除,此即本论文中研究的触发电子学的目标。由于宇宙线簇射的现象十分复杂,从而对触发电子学的灵活性提出了很高的要求。在本论文的研究过程中,对于国际上其他一些采用了大规模水切伦科夫探测器阵列的实验进行了调研,了解其物理目标、探测器分布及触发电子学结构。除此之外,对于近来在对撞机物理实验中兴起的无硬件触发结构的全数据读出数据获取方案也进行了相关调研。
在以上调研的基础上,根据LAWCA实验自身的特点及需求,提出了基于硬件实时触发判选的全数据读出方案设计。该方案中采用单片大容量、高性能现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)作为触发判选的核心器件,通过基于光纤的高速串行通信方式将来自前端电子学模块的完整数据全部集中到此核心触发FPGA中。在核心触发FPGA内部提取出数据的特征信息进行触发判选,最后采用基于千兆以太网的网络通信方式将判选后的有效数据传输至DAQ系统。这种方案省去了传统触发电子学结构向前端反馈触发信号线的过程,简化了系统；由于触发电子学能够获得前端电子学的全部完整数据,大大地提高了触发算法设计的灵活性,能更好地提高触发效率；通过对FPGA内部触发判选逻辑的重配置,使得可重构的触发电子学的实现称为可能。这种基于硬件实时触发判选的全数据读出结构具有以下两个明显优势：
一、所有前端电子学的完整数据全部汇总到触发判选模块中,使得更多的事例信息能够参与到触发判选中去,大大提高了触发模式设计的灵活性。同时可针对完整的事例信息设计各种处理方式,实现可重构的触发判选。
二、这种结构省去了触发信号向各个前端电子学模块回馈的过程,从而简化了系统结构,有利于提高系统稳定性。
在这样的触发电子学结构方案下,进行了相应的LAWCA实验触发电子学原型验证系统的设计。该原型验证系统既可用以验证触发电子学方案设计的正确性及可行性,也可作为未来触发电子学进行工程化时的一个良好技术基础。此原型验证系统采用单片大容量Xilinx Virtex-6系列XC6VLX365T FPGA作为触发判选的核心器件,并围绕其设计了与10个时钟分发及数据传输插件间的高速串行数据传输通道,其单路数据传输率为1.25Gbps。以此实现对于5.4Gbps系统平均数据率的汇总及实时缓存与触发判选。采用了Xilinx Virtex-5系列XC5VFX70T FPGA及相应的物理层芯片实现了两路基于千兆以太网的判选后有效数据读出通道。此原型验证系统通过VME总线来接收来自上位机的控制命令并反馈状态信息等,并可通过VME总线进行核心FPGA的在线重配置。通过这些技术手段,实现了触发电子学方案中的相应设计要求。
随后,根据目前基本触发模式的要求,进行了触发判选功能的算法与FPGA逻辑设计。在本文中介绍了其中采用的诸如延时方式实现多数据传输通道间的数据同步、分区缓存实现触发数据读出的2μs读出时间窗口等多种方法。以及对于多种触发判选逻辑工作模式的支持和一些触发判选算法中用到参数的在线动态调整配置方法。
为了验证触发电子学原型验证系统及相应的触发判选逻辑设计,物理学家给出了一些模拟数据来进行测试。在测试中,首先使用了MATLAB以基本触发模式的要求对模拟数据进行软件的触发判选,随后将模拟数据导入到触发模块中进行硬件的触发判选,最后将二者的结果进行比较,发现结果完全一致。这表明触发判选逻辑的设计完全符合我们对基本触发模式的建模结果。同时,还进行了眼图、误码率、数据丢包率等数据传输接口的相关测试,并对测试结果做了相应的分析。对于反映出设计存在不足的测试结果,也讨论了潜在的一些改善方案和未来进一步的改进设计。
在本论文的最后,总结了对于LAWCA实验触发电子学方案及原型验证系统的相关研究工作,并针对LAWCA实验下一步可能的探测器布局改动提出了相应的设计思路。同时对于实现TCP协议数据传输的可能设计改进方案也进行了一些探讨。
The Large Area Water Cherenkov Array (LAWCA) aims at the physical target of gamma astronomy at high energies. The LAWCA detector consists of900Photon Multiplier Tubes (PMTs) which are scattered in a150×150m2area. Every3×3PMTs form a group and their outputs are fed to one Front End Electronic (FEE) module for time and charge information measurement.
The data generated by FEE consists of valid signals and background noises. To eject the noises, the trigger electronics is demanded.Due to the complicated phenomena of cosmic ray showers, the flexibility of the trigger electronics must be guaranteed. During this research, we have made an investigation of the trigger electronics in other Water Cherenkov experiments. We also studied the "triggerless" total data readout method in the collider experiments.
Invoked by the idea of hardware triggerless architecture and based on our survey, a scheme of LAWCA trigger electronics is designed with all data transferred to a trigger module for processing. In the trigger module, one single FPGA device is employed to carry out the real-time trigger processing.Compared with traditional trigger electronics receiving only part of the data from front end, much more detailed information can be utilized to achieve a better trigger flexibility. It also eliminates the need of trigger signals fed back to front end; thus better system simplicity can be accomplished. Based on the abundant programmable inner connections and logic resources in the FPGA, reconfigurable trigger electronics can be realized; meanwhile, the trigger algorithms can be upgraded online with future modifications. Besides, because a large part of fake events can be rejected by the trigger electronics, the requirement on DAQ is significantly reduced.
Based on this scheme, a prototype of LAWCA trigger electronics is implemented. It could verify the correctless of this scheme and it could also be recognized as a good technical foundation for future engineering. A high capacity Xilinx Virtex-6series FPGA XC6VLX365T is adopted as the kernel device for trigger and data selection.10fiber based serial transmission channels are built; each supports a data transmission rate at1.25Gbps to accommodate the5.4Gbps system average data rate.The Gigabit Ethernet interface, which is used for triggered data transmission, is implemented with virtex-5XC5VFX70T FPGA and corresponding PHY chip. The online reconfiguration of this prototype is realized base on the VME bus. With these techniques, the requirements of the trigger electronics are met.
This trigger electronics prototype is designed and evaluated based on a basic trigger pattern. According to this basic trigger pattern, the trigger algorithm and FPGA logic is developed. And then some initial tests are also carried out. Simulation data generated by physicists is imported to verify the correctless of the trigger processing logic. The simulation data is processed by MATLAB and the prototype independently. The results from these two are fully matched, which indicates that the prototype functions well with the trigger logic strictly following the expected trigger pattern.
In the final chapter, the scheme and prototype research on the LAWCA trigger electronics is concluded. Some discussions about the future detector array layout modification are given. Some improved schemes on the TCP based Ethernet data transmission are also presented.
引文
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[1]Xilinx. Virtex-6 Family Overview, http://www.xilinx.com/support/documentation/data_sheets/ds150.pdf
[2]张宏斌,邱昆,周东.波分复用光纤通信技术[J].电子科技大学学报,2000,29(4)：337-341.
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[4]Xilinx. Virtex-6 GTX Transceivers, User Guide http://www.xilinx.com/support/documentation/user_guides/ug366.pdf
[5]Xilinx UG511 Virtex-5 FXT PowerPC 440 and MicroBlaze embedded processor, Data Sheet, http://www.xilinx.com/support/documentation/boards_and_kits/ug511.pdf
[6]Xilinx UG368 Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide,Data Sheet, http://www.xilinx.com/support/documentation/user_guides/ug368.pdf
[7]Marvell,88E1111 Product Brief, Data Sheet, http://www.marvell.com/transceivers/assets/Marvell-Alaska-Ultra-88E1111-GbE.pdf
[8]Xilinx UG534 ML605 Hardware User Guide, Data Sheet, http://www.xilinx.com/support/documentation/user_guides/ug534.pdf
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