高压IGBT的设计与实现及功率器件可靠性研究
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摘要
IGBT作为最新一代的复合全控型功率器件,具有电压控制、输入阻抗大、驱动功率小、控制电路简单、开关损耗小、工作频率高等诸多优点,而高压IGBT在电机控制、新能源、轨道交通、智能电网、电动汽车等领域起着不可替代的作用。由于国内工艺技术水平相对落后,高压IGBT的设计与生产长期落后于国外。本课题旨在结合现有国内工艺,研发具有自主知识产权的高压IGBT芯片,为高压IGBT在国内的研发和实现积累一定的经验。
功率器件可靠性问题已经成为影响功率模块整体性能的关键问题之一。本论文通过对功率器件SG-NLDMOS在热流子退化及关态雪崩击穿下的退化进行仿真与实验研究,揭示其退化机制,并提出改进措施。此项研究可为功率器件的可靠性设计及评估体系提供一定的参考价值。
本论文的主要工作及创新点包括：
1、提出高压IGBT的设计方法,设计并实现了一款1700V/100A高压大电流NPT-IGBT,包括其元胞结构、终端结构、工艺流程及版图的设计。通过分析及仿真确定元胞的结构参数；采用场限环与场板相结合的终端结构,讨论场板的设置对终端结构的影响,提出多晶硅场板设置的方案；对IGBT背面的集电极工艺进行探索及优化；简化工艺流程,应用六块光刻版完成整个工艺流程；设计了栅电极置中的版图结构。
2、提出了双面N+扩散残留层的新结构来改善平面栅型IGBT的JFET电阻,在改善器件导通压降的同时,击穿电压没有发生显著的下降；把N+扩散残留层应用到沟槽栅型IGBT当中,提出了DR-IGBT的结构,并与传统的NPT-IGBT和LPT CSTBT进行比较。与传统的NPT-IGBT相比,在相同的击穿电压下,其导通压降与电流能力更优；与LPT CSTBT相比,击穿电压更高,而导通压降则在大电流密度下比LPT CSTBT更低；引入背面P-缓冲层,提出了NPN管辅助快速开关的IGBT(NFS-IGBT)新结构,具有更好的导通压降与关断时间的折衷。
3、采用中子嬗变掺杂的区熔单晶硅作为衬底,制作了多目标光刻版,流片完成后进行半桥模块的封装,并对IGBT器件进行了测试。击穿电压达到1700V以上,125℃下工作电流100A；阈值电压5.2V左右、栅发射极漏电流小于80nA、关断时间0.744μs、关断功耗25mJ,都达到设计要求,只是导通压降略高(3.7V)。
4、采用直流电压应力实验TCAD仿真、电荷泵测试,对SG-NLDMOS器件的热载流子效应进行研究,揭示热载流子效应与栅压相关,在中等栅压下,热载流子退化发生在积累区,界面态和氧化层陷阱电荷同时发生作用；在高栅压下,退化发生在侧墙区,界面态起主导作用；研究了结构参数Ndd对热载流子效应的影响,并提出了改善措施。采用电流脉冲应力实验、TCAD仿真和电荷泵测试,研究了SG-NLDMOS的关态雪崩击穿退化机制,发现雪崩击穿退化近似于高栅压和中等栅压下热载流子退化的叠加,氧化层陷阱正电荷主要产生于积累区,而界面态在整个漂移区中都有增加。
As the latest generation of somposite full-controlled power devices, IGBT has most outstanding characteristics, such as voltage control, large input impedance, small driving power, simple control circuit, low switching losses, and high operating frequency. High-voltage IGBT plays an irreplaceable role in motor control, new energy, rail transportation, smart grid, electric vehicles, and other fields. However, due to relatively late research, technology lags behind, resulting in the design and production of high-voltage IGBT long-term behind foreign countries. The purpose of this thesis is to combine the existing domestic technology, research, and development of high-voltage IGBT with independent intellectual property rights, and accumulate certain experience for domestic high-voltage IGBT design.
In addition, the power device's reliability problem has become one of the key problems affecting the overall ferformance of the power integrated circuit. Through the research of hot carrier degradation and off-state avalanche breakdown degradation of SG-NLDMOS by experiments and simulation, this thesis reveals the degradation mechanisms and put forward the measures of improvement. The research can provide certain reference value for the power device reliability design and evaluation system.
The main work and innovations include:
1. Put forward the design method of high-voltage IGBT. Design1700V NPT-IGBT, including its cell structure, terminal structure, process, and layout design. The structure of the various parts of cell parameters was determined through analysis the principle of the device and simulation the device. The field limiting ring combined with field plate was adopted as terminal structure, the influence of field plate arranged on the terminal structure was discussed, and the polysilicon field plate setting scheme was put forward. The process of IGBT back collector was explored to optimize it. To simplify the entire process and the whole process was completed with six photolithographies. And finally the layout with gate in the center was designed.
2. The structure of N+diffusion remnant layer was proposed to improve the JFET resistance of planar gate IGBT, thus improving the on-state voltage drop at the same time without a significant breakdown voltage decline. The structure of N+diffusion remnant layer was applied to the trench gate IGBT which is proposed DR-IGBT, and compared with conventional NPT-IGBT and LPT CSTBT. Under the same breakdown voltage, the on-state voltage drop and current capability of DR-IGBT are superior to NPT-IGBT. The breaddown voltage of DR-IGBT is higher than LPT CSTBT, while the voltage drop of DR-IGBT in the high current density is lower than the LPT CSTBT. By introduction of P-buffer layer to optimize the back structure of IGBT, the NPN aided fast switching IGBT (NFS-IGBT) is presented, which has visibly better trade-off relationship between on-state voltage drop and turn-off time.
3. The NPT-IGBT fabrication used high resistance float zone silicon crystal with neutron transmutation doping as substrate and making of a MPW mask. After the chip completed, the NPT-IGBT was packed with the half-bridge module and tested. Vces>1700V, Ic=100A (125℃) Vth:5.2V, Ige<80nA, Toff=0.744μs, Eoff=25mJ. All the electrical characteristics meet the disgn requirements, except Vces=3.7V.
4. The hot carrier effect of SG-NLDMOS was investigated by DC voltage stress, TC AD simulation, and charge pumping test. The hot carrier effect of SG-NLDMOS is associated with the gate voltage. When stressed under middle Vgs, interface states and positive oxide trapped charge generation in the accumulation region under the poly step cause the degradation. When stressed under high Vgs, interface states formation in the spacer region near the drain contact play a leading role. The structural parameter affects on the hot carrier effects have been studied and the measures of improving the hot carrier degradation are put forward. The degradation induced by off-state avalanche breakdown of SG-NLDMOS was investigated by current pulse stress, TCAD simulations, and charge pumping test. The degradation induced by off-state avalanche breakdown is similar to the stacked hot-carrier degradation under high Vgs and middle Vgs. The positive oxide trapped charge generates in the accumulation region, while the interface states have increased in the whole drift region.
功率器件可靠性问题已经成为影响功率模块整体性能的关键问题之一。本论文通过对功率器件SG-NLDMOS在热流子退化及关态雪崩击穿下的退化进行仿真与实验研究,揭示其退化机制,并提出改进措施。此项研究可为功率器件的可靠性设计及评估体系提供一定的参考价值。
本论文的主要工作及创新点包括：
1、提出高压IGBT的设计方法,设计并实现了一款1700V/100A高压大电流NPT-IGBT,包括其元胞结构、终端结构、工艺流程及版图的设计。通过分析及仿真确定元胞的结构参数；采用场限环与场板相结合的终端结构,讨论场板的设置对终端结构的影响,提出多晶硅场板设置的方案；对IGBT背面的集电极工艺进行探索及优化；简化工艺流程,应用六块光刻版完成整个工艺流程；设计了栅电极置中的版图结构。
2、提出了双面N+扩散残留层的新结构来改善平面栅型IGBT的JFET电阻,在改善器件导通压降的同时,击穿电压没有发生显著的下降；把N+扩散残留层应用到沟槽栅型IGBT当中,提出了DR-IGBT的结构,并与传统的NPT-IGBT和LPT CSTBT进行比较。与传统的NPT-IGBT相比,在相同的击穿电压下,其导通压降与电流能力更优；与LPT CSTBT相比,击穿电压更高,而导通压降则在大电流密度下比LPT CSTBT更低；引入背面P-缓冲层,提出了NPN管辅助快速开关的IGBT(NFS-IGBT)新结构,具有更好的导通压降与关断时间的折衷。
3、采用中子嬗变掺杂的区熔单晶硅作为衬底,制作了多目标光刻版,流片完成后进行半桥模块的封装,并对IGBT器件进行了测试。击穿电压达到1700V以上,125℃下工作电流100A；阈值电压5.2V左右、栅发射极漏电流小于80nA、关断时间0.744μs、关断功耗25mJ,都达到设计要求,只是导通压降略高(3.7V)。
4、采用直流电压应力实验TCAD仿真、电荷泵测试,对SG-NLDMOS器件的热载流子效应进行研究,揭示热载流子效应与栅压相关,在中等栅压下,热载流子退化发生在积累区,界面态和氧化层陷阱电荷同时发生作用；在高栅压下,退化发生在侧墙区,界面态起主导作用；研究了结构参数Ndd对热载流子效应的影响,并提出了改善措施。采用电流脉冲应力实验、TCAD仿真和电荷泵测试,研究了SG-NLDMOS的关态雪崩击穿退化机制,发现雪崩击穿退化近似于高栅压和中等栅压下热载流子退化的叠加,氧化层陷阱正电荷主要产生于积累区,而界面态在整个漂移区中都有增加。
As the latest generation of somposite full-controlled power devices, IGBT has most outstanding characteristics, such as voltage control, large input impedance, small driving power, simple control circuit, low switching losses, and high operating frequency. High-voltage IGBT plays an irreplaceable role in motor control, new energy, rail transportation, smart grid, electric vehicles, and other fields. However, due to relatively late research, technology lags behind, resulting in the design and production of high-voltage IGBT long-term behind foreign countries. The purpose of this thesis is to combine the existing domestic technology, research, and development of high-voltage IGBT with independent intellectual property rights, and accumulate certain experience for domestic high-voltage IGBT design.
In addition, the power device's reliability problem has become one of the key problems affecting the overall ferformance of the power integrated circuit. Through the research of hot carrier degradation and off-state avalanche breakdown degradation of SG-NLDMOS by experiments and simulation, this thesis reveals the degradation mechanisms and put forward the measures of improvement. The research can provide certain reference value for the power device reliability design and evaluation system.
The main work and innovations include:
1. Put forward the design method of high-voltage IGBT. Design1700V NPT-IGBT, including its cell structure, terminal structure, process, and layout design. The structure of the various parts of cell parameters was determined through analysis the principle of the device and simulation the device. The field limiting ring combined with field plate was adopted as terminal structure, the influence of field plate arranged on the terminal structure was discussed, and the polysilicon field plate setting scheme was put forward. The process of IGBT back collector was explored to optimize it. To simplify the entire process and the whole process was completed with six photolithographies. And finally the layout with gate in the center was designed.
2. The structure of N+diffusion remnant layer was proposed to improve the JFET resistance of planar gate IGBT, thus improving the on-state voltage drop at the same time without a significant breakdown voltage decline. The structure of N+diffusion remnant layer was applied to the trench gate IGBT which is proposed DR-IGBT, and compared with conventional NPT-IGBT and LPT CSTBT. Under the same breakdown voltage, the on-state voltage drop and current capability of DR-IGBT are superior to NPT-IGBT. The breaddown voltage of DR-IGBT is higher than LPT CSTBT, while the voltage drop of DR-IGBT in the high current density is lower than the LPT CSTBT. By introduction of P-buffer layer to optimize the back structure of IGBT, the NPN aided fast switching IGBT (NFS-IGBT) is presented, which has visibly better trade-off relationship between on-state voltage drop and turn-off time.
3. The NPT-IGBT fabrication used high resistance float zone silicon crystal with neutron transmutation doping as substrate and making of a MPW mask. After the chip completed, the NPT-IGBT was packed with the half-bridge module and tested. Vces>1700V, Ic=100A (125℃) Vth:5.2V, Ige<80nA, Toff=0.744μs, Eoff=25mJ. All the electrical characteristics meet the disgn requirements, except Vces=3.7V.
4. The hot carrier effect of SG-NLDMOS was investigated by DC voltage stress, TC AD simulation, and charge pumping test. The hot carrier effect of SG-NLDMOS is associated with the gate voltage. When stressed under middle Vgs, interface states and positive oxide trapped charge generation in the accumulation region under the poly step cause the degradation. When stressed under high Vgs, interface states formation in the spacer region near the drain contact play a leading role. The structural parameter affects on the hot carrier effects have been studied and the measures of improving the hot carrier degradation are put forward. The degradation induced by off-state avalanche breakdown of SG-NLDMOS was investigated by current pulse stress, TCAD simulations, and charge pumping test. The degradation induced by off-state avalanche breakdown is similar to the stacked hot-carrier degradation under high Vgs and middle Vgs. The positive oxide trapped charge generates in the accumulation region, while the interface states have increased in the whole drift region.
引文
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