小数频率合成器建模与仿真
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摘要
本文对于采用delta-sigma调制的小数频率合成器(Δ-ΣPLL)的建模与仿真方式进行了深入的讨论。所涉及的模型分为两个部分,线性模型和行为级模型。
本文首先对混合信号系统的传输函数形式进行了讨论。在已有的连续和离散信号处理理论的基础之上,加以综合,推导出了一个明确的混合信号系统传输函数表达式,适用于实际应用中的锁相环(PLL)、延迟环(MDLL)等混合信号系统。
随后对二阶电荷泵锁相环的线性模型进行了介绍,尤其对其中的鉴频鉴相器(PFD)时域和频域模型进行着重论述,运用了相关领域的仿真方式,在数学上证明了基于何种假设可以得到一个PFD的线性频域模型。并对其中的近似程度做了讨论。
论文的其余部分基于作者编写的一套PLL辅助设计软件,对于其动态分析与行为级模型进行了论述。动态分析运用前述的混合信号系统传输函数表达式以及线性建模结果,得到一个二阶Δ-Σ电荷泵PLL的系统传输函数。讨论了其系统参数确定方法以及稳定时间和噪声特性优化方法。
最后关于行为级模型,作者运用Matlab编写了一套二阶Δ-Σ电荷泵PLL行为级模型,进行工作周期级(Cycle-wise)的行为级仿真。能够对于锁相环中的电荷泵、压控振荡器以及delta-sigma调制器的非线性行为做出描述,得到准确的时域稳定时间分析曲线。
In this work, the modeling and simulation approaches of delta-sigma fractional-n (Δ-ΣPLL) frequency synthesizer is closely discussed, including two different field of models: linearized modeling and behavior modeling.
One expression of transfer function for mixed signal system is firstly proposed in this work, based on discrete time and continuous time signal processing theory, which could be employed on the study and analysis on the practical mixed-signal system, such as PLL and MDLL
Secondly the linearized model of a second order charge pump PLL is discussed. And the focus is on the linearized model of PFD module, some approaches is adopted for arriving at a mathematic deduction for the linearized process based on several definite assumption. Further, the extent of approximation is discussed.
The rest part of this work is based on one set of PLL design assistant toolbox developed by the author, and is focus on the dynamics analysis and behavior modeling of 2nd orderΔ-ΣPLL. The dynamics analysis is based on the foregoing mixed signal system transfer function expression and linearized modeling approaches, obtaining the system transfer function of a 2nd orderΔ-ΣPLL. Hence, the methodology of system specs, parameters calculation and optimization of settling time and noise performance, is discussed.
Finally, the behavior model proposed in this work, is developed in Matlab, which could perform cycle-wise behavior simulation of a 2nd orderΔ-ΣPLL. The nonlinearity of charge pump, VCO and SDM is covered by this model, which results in a accurate settling time simulation.
本文首先对混合信号系统的传输函数形式进行了讨论。在已有的连续和离散信号处理理论的基础之上,加以综合,推导出了一个明确的混合信号系统传输函数表达式,适用于实际应用中的锁相环(PLL)、延迟环(MDLL)等混合信号系统。
随后对二阶电荷泵锁相环的线性模型进行了介绍,尤其对其中的鉴频鉴相器(PFD)时域和频域模型进行着重论述,运用了相关领域的仿真方式,在数学上证明了基于何种假设可以得到一个PFD的线性频域模型。并对其中的近似程度做了讨论。
论文的其余部分基于作者编写的一套PLL辅助设计软件,对于其动态分析与行为级模型进行了论述。动态分析运用前述的混合信号系统传输函数表达式以及线性建模结果,得到一个二阶Δ-Σ电荷泵PLL的系统传输函数。讨论了其系统参数确定方法以及稳定时间和噪声特性优化方法。
最后关于行为级模型,作者运用Matlab编写了一套二阶Δ-Σ电荷泵PLL行为级模型,进行工作周期级(Cycle-wise)的行为级仿真。能够对于锁相环中的电荷泵、压控振荡器以及delta-sigma调制器的非线性行为做出描述,得到准确的时域稳定时间分析曲线。
In this work, the modeling and simulation approaches of delta-sigma fractional-n (Δ-ΣPLL) frequency synthesizer is closely discussed, including two different field of models: linearized modeling and behavior modeling.
One expression of transfer function for mixed signal system is firstly proposed in this work, based on discrete time and continuous time signal processing theory, which could be employed on the study and analysis on the practical mixed-signal system, such as PLL and MDLL
Secondly the linearized model of a second order charge pump PLL is discussed. And the focus is on the linearized model of PFD module, some approaches is adopted for arriving at a mathematic deduction for the linearized process based on several definite assumption. Further, the extent of approximation is discussed.
The rest part of this work is based on one set of PLL design assistant toolbox developed by the author, and is focus on the dynamics analysis and behavior modeling of 2nd orderΔ-ΣPLL. The dynamics analysis is based on the foregoing mixed signal system transfer function expression and linearized modeling approaches, obtaining the system transfer function of a 2nd orderΔ-ΣPLL. Hence, the methodology of system specs, parameters calculation and optimization of settling time and noise performance, is discussed.
Finally, the behavior model proposed in this work, is developed in Matlab, which could perform cycle-wise behavior simulation of a 2nd orderΔ-ΣPLL. The nonlinearity of charge pump, VCO and SDM is covered by this model, which results in a accurate settling time simulation.
引文
[1] 王志华, 吴恩得, “CMOS 射频集成电路的现状与发展,” 电子学报,vol. 29, No. 2, pp. 233-238, 2001
[2] M. Copeland, T. Riley, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 553-559, May 1993
[3] Dana Series 7000 Digiphase Frequency Synthesizers, Publication 980428, Dana Laboratories, Inc., 1973
[4] 2. J. Candy and G. Temes, “Oversampling methods for AID and D/A conversion” in Oversampling Delta-Sigma Data Converters, pp. 1-25, IEEE Press, 1992.
[5] T. A. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-sigma modulation in fractional-n frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553–559, May 1993.
[6] David Johns, Ken Martin, “Analog Integrated Circuit Design” John Wiley & Sons, Inc. pp. 531-555.
[7] Richard Schreier, Gabor C. Temes, “Understanding Delta-Sigma Data Converters” John Wiley & Sons, Inc. Publication.
[8] E.A.Lee and D.G.Messerschmitt, Digital Commun-ication, 2nd ed. Norwell, MA: Kluwer, 1994.
[9] Best R E. Phase-locked loops [M]. 2nd ed. New York, NY: McGraw-Hill, 1993.
[10] N. B. Carvalho , R. C. Madureira and J. C. Pedro, “Prediction of PLL Frequency Discriminator Non-Linear Distortion Using The Volterra Series Approach”
[11] M. H. Perrott, M.D. Trott, and C. G. Sodini. A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis. In IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp. 1028--1038, Aug. 2002.C
[12] W. Egan, Frequency Synthesis by Phase Look, New York, John Wiley & Sons, USA, 1980
[13] M. H. Perrott, “Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers with noise shaping,” Ph.D. dissertation, Massachusetts Inst. Technol., Cambridge, MA, 1997.
[14] M. Perrott, T. Tewksbury, and C. Sodini, “A 27-mW CMOS fractional- N synthesizer using digital compensation for 2.5-Mb/s GFSM modulation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048–2060, Dec. 1997.
[15] S.Willingham, M. Perrott, B. Setterberg, A. Grzegorek, andW. McFarland, “An integrated 2.5-GHz sigma–delta frequency synthesizer with 5 microseconds settling and 2-Mb/s closed-loop modulation,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2000, pp. 200–201.
[16] M. H. Perrott, “Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits,” in Proc. Design Automation Conf. (DAC), June 2002, pp. 498–503.
[17] B. Miller and R. Conley, “A multiple modulator fractional divider,” IEEE Transactions on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991
[18] K. C. Chao, S. Nadeen, W. L. Lee and C. G. Sodini, "A higher order topology for interpolative modulators for oversampling A/D converter," IEEE Trans. Circuits System., vol. CAS-37, pp.309-318, Mar. 1990.
[19] C.Y. Lau, M.H. Perrott, "Fractional-N Frequency Synthesizer Design at the Transfer Function Level Using a Direct Closed Loop Realization Algorithm," 2003 DAC, Anaheim, CA.
[20] Raghavendra R G and Bharadwaj Amrutur, “Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop,”GLSVLSI 2007.
[21] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits” Second Edition, pp. 659-678
[22] W. O. Keese, "An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops," at: http://www.sss-mag.com/pdf/pllfil.pdf
[23] L. Risbo, “D-S modulators—Stability analysis and optimization,” Ph.D. dissertation, Electron. Instit., Tech. Univ. Denmark, Denmark, June 1994.
[24] B. Razavi, IEEE Custom Integrated Circuits Conference, p.395 (1997). pp. 13-16
[25] A. Hill, A. Surber, “The PLL Dead Zone and How to Avoid It”, RF Design, pages 131-134, Mar 1992.
[26] Sudhakar Pamarti, “Enabling Techniques for Wide Bandwidth Fractional-N Phase Locked Loops”, a dissertation in partial satisfaction of the requirements for the PHD. In ECE., UCSD., 2003.
[27] Michael H. Perrott, “PLL Design Using the PLL Design Assistant Program”, 2005
[28] Michael H. Perrott, “Fractional-N Frequency Synthesizer Design Using The PLL Design Assistant and CppSim Programs”, 2004
[29] Scott E. Meninger, “Design of a Wideband Fractional-N Frequency Synthesizer Using CppSim”, 2005
[30] Michael H. Perrott, “Sue2 User Manual (Version 1.0)”, 2004
[2] M. Copeland, T. Riley, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 553-559, May 1993
[3] Dana Series 7000 Digiphase Frequency Synthesizers, Publication 980428, Dana Laboratories, Inc., 1973
[4] 2. J. Candy and G. Temes, “Oversampling methods for AID and D/A conversion” in Oversampling Delta-Sigma Data Converters, pp. 1-25, IEEE Press, 1992.
[5] T. A. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-sigma modulation in fractional-n frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553–559, May 1993.
[6] David Johns, Ken Martin, “Analog Integrated Circuit Design” John Wiley & Sons, Inc. pp. 531-555.
[7] Richard Schreier, Gabor C. Temes, “Understanding Delta-Sigma Data Converters” John Wiley & Sons, Inc. Publication.
[8] E.A.Lee and D.G.Messerschmitt, Digital Commun-ication, 2nd ed. Norwell, MA: Kluwer, 1994.
[9] Best R E. Phase-locked loops [M]. 2nd ed. New York, NY: McGraw-Hill, 1993.
[10] N. B. Carvalho , R. C. Madureira and J. C. Pedro, “Prediction of PLL Frequency Discriminator Non-Linear Distortion Using The Volterra Series Approach”
[11] M. H. Perrott, M.D. Trott, and C. G. Sodini. A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis. In IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp. 1028--1038, Aug. 2002.C
[12] W. Egan, Frequency Synthesis by Phase Look, New York, John Wiley & Sons, USA, 1980
[13] M. H. Perrott, “Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers with noise shaping,” Ph.D. dissertation, Massachusetts Inst. Technol., Cambridge, MA, 1997.
[14] M. Perrott, T. Tewksbury, and C. Sodini, “A 27-mW CMOS fractional- N synthesizer using digital compensation for 2.5-Mb/s GFSM modulation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048–2060, Dec. 1997.
[15] S.Willingham, M. Perrott, B. Setterberg, A. Grzegorek, andW. McFarland, “An integrated 2.5-GHz sigma–delta frequency synthesizer with 5 microseconds settling and 2-Mb/s closed-loop modulation,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2000, pp. 200–201.
[16] M. H. Perrott, “Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits,” in Proc. Design Automation Conf. (DAC), June 2002, pp. 498–503.
[17] B. Miller and R. Conley, “A multiple modulator fractional divider,” IEEE Transactions on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991
[18] K. C. Chao, S. Nadeen, W. L. Lee and C. G. Sodini, "A higher order topology for interpolative modulators for oversampling A/D converter," IEEE Trans. Circuits System., vol. CAS-37, pp.309-318, Mar. 1990.
[19] C.Y. Lau, M.H. Perrott, "Fractional-N Frequency Synthesizer Design at the Transfer Function Level Using a Direct Closed Loop Realization Algorithm," 2003 DAC, Anaheim, CA.
[20] Raghavendra R G and Bharadwaj Amrutur, “Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop,”GLSVLSI 2007.
[21] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits” Second Edition, pp. 659-678
[22] W. O. Keese, "An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops," at: http://www.sss-mag.com/pdf/pllfil.pdf
[23] L. Risbo, “D-S modulators—Stability analysis and optimization,” Ph.D. dissertation, Electron. Instit., Tech. Univ. Denmark, Denmark, June 1994.
[24] B. Razavi, IEEE Custom Integrated Circuits Conference, p.395 (1997). pp. 13-16
[25] A. Hill, A. Surber, “The PLL Dead Zone and How to Avoid It”, RF Design, pages 131-134, Mar 1992.
[26] Sudhakar Pamarti, “Enabling Techniques for Wide Bandwidth Fractional-N Phase Locked Loops”, a dissertation in partial satisfaction of the requirements for the PHD. In ECE., UCSD., 2003.
[27] Michael H. Perrott, “PLL Design Using the PLL Design Assistant Program”, 2005
[28] Michael H. Perrott, “Fractional-N Frequency Synthesizer Design Using The PLL Design Assistant and CppSim Programs”, 2004
[29] Scott E. Meninger, “Design of a Wideband Fractional-N Frequency Synthesizer Using CppSim”, 2005
[30] Michael H. Perrott, “Sue2 User Manual (Version 1.0)”, 2004