通用型8位MCU内核设计及应用
摘要
MCU在现实生活中越来越多,人们也越来越享受MCU带来的生活上的便利。从智能家电、消费类电子、电动自行车到远程抄表、网络支付等现代化产品都体现出MCU的巨大作用和深远影响。
由于MCU内核的结构不同,其工作速度和性能也不同。RISC结构简单,指令少,CISC复杂,指令较多,但编译方便;Harvard结构由于寻址方式的原因较冯·诺伊曼结构工作速度快。
本文主要研究了MCU内核的电路结构和实现方式,并通过一个混合信号的MCU—HS16C711来验证内核。本文着重讨论了ALU的设计方法,演算出ALU和加法器之间的逻辑递推关系,研究分析了Core的时钟系统、时序、指令代码的译码方式、两级流水线的结构等,并设计了MCU的常用电路如RAM、Program Counter、堆栈等。
本设计采用原理图直接输入的方式,利用cadence工具软件Verilog-XL进行了逻辑仿真,关键电路使用hspice进行了电路网表仿真,如四相时钟和复位电路等。设计完成后,利用QuartusII工具编译、下载,进行了FPGA测试。最后利用CSMC0.5um N阱CMOS混合信号工艺进行了版图布局和生产。
通过实际流片后,验证了设计的正确性。
MCU is more and more popular in our daily life . people are also increasingly brought life to enjoy the convenience of MCU. From smart home appliances, consumer electronics, electric bicycles to the remote meter reading, the MCU have acted as a important role in Internet payment and other modern products,which also has a far-reaching implications.
Because of the structure of MCU core is different, its working speed and performance are also different. RISC with simple structure and less instruction,while CISC with complex structure and more instruction, but easy to compile; Harvard structure, is work faster than von Neumann as the reason of addressing modes.
This paper mainly research on the MCU core circuit structure and implementation methods, and through a mixed-signal MCU - HS16C711 to verify the core. This paper is focuses on the design methods of ALU , calculuing the logic relations between the ALU and adders, researching analyzing of the Core of the clock system, timing, decoding methodv of instruction code, two pipelines structure. besides ,it also design of the MCU commonly used circuits, such as RAM, Program Counter, the stack and so on.
This design uses the way of a direct schematic input , using software tool of cadence and Verilog-XL for logic simulation. The key circuits used hspice for simulation of the circuit netlist,such as Four-phase clock,circuit reset and so on . when the design was completed, I used QuartusII to compile and download, while conducted a FPGA test.At last, I used CSMC0.5um N-well CMOS mixed-signal to Carry out the territory layout and production.
After passing through the actual silicon,it verify the design is correct
由于MCU内核的结构不同,其工作速度和性能也不同。RISC结构简单,指令少,CISC复杂,指令较多,但编译方便;Harvard结构由于寻址方式的原因较冯·诺伊曼结构工作速度快。
本文主要研究了MCU内核的电路结构和实现方式,并通过一个混合信号的MCU—HS16C711来验证内核。本文着重讨论了ALU的设计方法,演算出ALU和加法器之间的逻辑递推关系,研究分析了Core的时钟系统、时序、指令代码的译码方式、两级流水线的结构等,并设计了MCU的常用电路如RAM、Program Counter、堆栈等。
本设计采用原理图直接输入的方式,利用cadence工具软件Verilog-XL进行了逻辑仿真,关键电路使用hspice进行了电路网表仿真,如四相时钟和复位电路等。设计完成后,利用QuartusII工具编译、下载,进行了FPGA测试。最后利用CSMC0.5um N阱CMOS混合信号工艺进行了版图布局和生产。
通过实际流片后,验证了设计的正确性。
MCU is more and more popular in our daily life . people are also increasingly brought life to enjoy the convenience of MCU. From smart home appliances, consumer electronics, electric bicycles to the remote meter reading, the MCU have acted as a important role in Internet payment and other modern products,which also has a far-reaching implications.
Because of the structure of MCU core is different, its working speed and performance are also different. RISC with simple structure and less instruction,while CISC with complex structure and more instruction, but easy to compile; Harvard structure, is work faster than von Neumann as the reason of addressing modes.
This paper mainly research on the MCU core circuit structure and implementation methods, and through a mixed-signal MCU - HS16C711 to verify the core. This paper is focuses on the design methods of ALU , calculuing the logic relations between the ALU and adders, researching analyzing of the Core of the clock system, timing, decoding methodv of instruction code, two pipelines structure. besides ,it also design of the MCU commonly used circuits, such as RAM, Program Counter, the stack and so on.
This design uses the way of a direct schematic input , using software tool of cadence and Verilog-XL for logic simulation. The key circuits used hspice for simulation of the circuit netlist,such as Four-phase clock,circuit reset and so on . when the design was completed, I used QuartusII to compile and download, while conducted a FPGA test.At last, I used CSMC0.5um N-well CMOS mixed-signal to Carry out the territory layout and production.
After passing through the actual silicon,it verify the design is correct
引文
[1] R.Jacob Baker, Harry W.Li, David E.Boyce. CMOS电路设计(第二版).陈中建等译.北京:机械工业出版社,2006.1.
[2] "microchip中档参考手册”,microchip,I nc.,2001.
[3]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿等译.西安:西安交通大学出版社,2003.
[4] Sung-Mo Kang,Yusuf Leblebici.CMOS数字集成电路——分析与设计(第三版).王志功等译.北京:电子工业出版社,2004.10.
[5] CHRIS A.YOUNG.An Enhanced Method for Characterizing Successive Approximation Converters.IEEE Trans.Instrum.Meas.,1990.
[6] Wayne Wolf.现代VLSI电路设计——芯片系统设计(第三版,英文影印版).北京:科学出版社,2003.
[7]童诗白.数字电子技术基础第二版.北京:高等教育出版社, 1988.5, pp.224-400
[8]朱如琪,罗杰,"CPLD/FPGA与ASIC设计实践教程”,北京:科学出版社,2005.
[9]任艳颖,王彬,“IC设计基础”,西安:西安电子科技大学出版社,2003.
[10] Samir Palnitkar.Verilog HDL数字设计与综合(第二版).夏宇闻等译.北京:电子工业出版社,2004.11.
[11]周昔平,“高速数字电路的微系统结构研究”,西北工业大学,2002
[12]高德远,樊晓娅,张盛兵,王党辉,罗呈,“超大规模集成电路—系统和电路的设计原理”,北京:高等教育出版社,2003.
[13]王礼平,王观凤,“超前进位加法器的延迟时间公式与优化设计”,武汉理工大学学报(交通科学与工程版),28-4,2004.8.
[14]李侠,“低功耗嵌入式微处理器的VLSI设计研究’,复旦大学,2004.
[15]黄恺著,李三立等译。计算机算术运算原理、结构与设计。北京:科学出版社。1979.
[16]工新刚,“多线程处理器存储结构研究”,西北工业大学,2004.
[17]郑伟,“多媒体应用的高性能数字信号处理器功能部件结构设计研究”,浙江大学,2003.
[18] J. Bhasker(著),徐振林等(译),"Verilog HDL硬件描述语言”,北京:机械工业出版社,2000.
[19]刘志碧,"16位高性能嵌入式数字信号处理器的研究与设计”,湖南大学,2003.
[20] JohnF .W akerly.D igitalD esignP rinciples& Practices( ThirdE dition影印版)[M].北京:高等教育出版社,2002.
[21] VititKantabutra,Pasquale Corsonello, Stefanie Fast, Low--CostAddersUsing CarryStrength Signals SSGGRR 2000, 1' Aquila, Italy; 31July-6 August.
[22] E. Nishimura, T. Nakamura, etal.,"Multiplying Unit Circuit", US Parent N0. 5010510,1991.
[23] K. Hwang. "Computer Arithmetic Principles, Architecture. and Design",John Wiley&Sons. 1979.
[24] Manzoul M. A, "Parallel CLA algorithm for fast addition", Proc Intl Par Comput EEConf. 2000.
[25] C. S.Wallace,"A suggestion for a Fast Multiplier", IEEE Trans. Electronic Computer,Vol.E C-13, pn. 14-17,f eb. 1964.
[26]刘宝琴王德生罗嵘(编著),“逻辑设计与数字系统”,北京:清华大学出版社,2005.
[27]王行,李衍,"EDA技术入门与提高”,西安:西安电子科技大学出版社,2002,西安电子科技大学出版社,2005.
[28]杨刚,龙海燕,“现代电子技术—VJDL与数字系统设计’,,北京:电子工业出版社,2004.
[29]诸振勇,翁木云,"FPGA设计及应用”,西安.
[30] K. Hwang. "Computer Arithmetic Principles, Architecture. and Design",John Wiley&Sons. 1979.
[31] C. S.Wallace,"A suggestion for a Fast Multiplier", IEEE Trans. Electronic Computer,Vol.E C-13, pn. 14-17,f eb. 1964.
[2] "microchip中档参考手册”,microchip,I nc.,2001.
[3]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿等译.西安:西安交通大学出版社,2003.
[4] Sung-Mo Kang,Yusuf Leblebici.CMOS数字集成电路——分析与设计(第三版).王志功等译.北京:电子工业出版社,2004.10.
[5] CHRIS A.YOUNG.An Enhanced Method for Characterizing Successive Approximation Converters.IEEE Trans.Instrum.Meas.,1990.
[6] Wayne Wolf.现代VLSI电路设计——芯片系统设计(第三版,英文影印版).北京:科学出版社,2003.
[7]童诗白.数字电子技术基础第二版.北京:高等教育出版社, 1988.5, pp.224-400
[8]朱如琪,罗杰,"CPLD/FPGA与ASIC设计实践教程”,北京:科学出版社,2005.
[9]任艳颖,王彬,“IC设计基础”,西安:西安电子科技大学出版社,2003.
[10] Samir Palnitkar.Verilog HDL数字设计与综合(第二版).夏宇闻等译.北京:电子工业出版社,2004.11.
[11]周昔平,“高速数字电路的微系统结构研究”,西北工业大学,2002
[12]高德远,樊晓娅,张盛兵,王党辉,罗呈,“超大规模集成电路—系统和电路的设计原理”,北京:高等教育出版社,2003.
[13]王礼平,王观凤,“超前进位加法器的延迟时间公式与优化设计”,武汉理工大学学报(交通科学与工程版),28-4,2004.8.
[14]李侠,“低功耗嵌入式微处理器的VLSI设计研究’,复旦大学,2004.
[15]黄恺著,李三立等译。计算机算术运算原理、结构与设计。北京:科学出版社。1979.
[16]工新刚,“多线程处理器存储结构研究”,西北工业大学,2004.
[17]郑伟,“多媒体应用的高性能数字信号处理器功能部件结构设计研究”,浙江大学,2003.
[18] J. Bhasker(著),徐振林等(译),"Verilog HDL硬件描述语言”,北京:机械工业出版社,2000.
[19]刘志碧,"16位高性能嵌入式数字信号处理器的研究与设计”,湖南大学,2003.
[20] JohnF .W akerly.D igitalD esignP rinciples& Practices( ThirdE dition影印版)[M].北京:高等教育出版社,2002.
[21] VititKantabutra,Pasquale Corsonello, Stefanie Fast, Low--CostAddersUsing CarryStrength Signals SSGGRR 2000, 1' Aquila, Italy; 31July-6 August.
[22] E. Nishimura, T. Nakamura, etal.,"Multiplying Unit Circuit", US Parent N0. 5010510,1991.
[23] K. Hwang. "Computer Arithmetic Principles, Architecture. and Design",John Wiley&Sons. 1979.
[24] Manzoul M. A, "Parallel CLA algorithm for fast addition", Proc Intl Par Comput EEConf. 2000.
[25] C. S.Wallace,"A suggestion for a Fast Multiplier", IEEE Trans. Electronic Computer,Vol.E C-13, pn. 14-17,f eb. 1964.
[26]刘宝琴王德生罗嵘(编著),“逻辑设计与数字系统”,北京:清华大学出版社,2005.
[27]王行,李衍,"EDA技术入门与提高”,西安:西安电子科技大学出版社,2002,西安电子科技大学出版社,2005.
[28]杨刚,龙海燕,“现代电子技术—VJDL与数字系统设计’,,北京:电子工业出版社,2004.
[29]诸振勇,翁木云,"FPGA设计及应用”,西安.
[30] K. Hwang. "Computer Arithmetic Principles, Architecture. and Design",John Wiley&Sons. 1979.
[31] C. S.Wallace,"A suggestion for a Fast Multiplier", IEEE Trans. Electronic Computer,Vol.E C-13, pn. 14-17,f eb. 1964.