基于FPGA的数据加密设备的设计
摘要
随着信息化和数字化社会的发展,人们对信息安全和保密的重要性的认识不断提高,如何有效保护计算机的信息安全已经成为IT界研究的热点。针对这种隐患的存在,本文以FPGA为平台将USB接口、AES加密技术和EDA技术相结合,采用SOPC软硬协同的方式设计了PC机外接数据加密设备。在不占用计算机硬件资源的情况下,实现了PC机上的数据的加解密,保证了PC机中数据的安全性。并且密钥固化在FPGA芯片中,不用担心忘记密钥而带来的不便。本设计既具有FPGA本身的高速性,安全性以及软件方面的易维护性和灵活性,又带有USB的热插拔,即插即用等功能,使用方便,而且性价比高。
系统开发的硬件平台是FPGA,操作系统平台是Microsoft Windows XP,开发工具是QuartusII9.O、 SOPC Builder和NiosII IDE、 Microsoft Visual C++。系统结构包括软件和硬件两部分。PC主机负责上位机软件部分,完成用户应用程序界面的开发；FPGA开发负责硬件部分,完成AES算法模块和USB接口控制器的开发,其中AES算法单元采用硬件描述语言Verilog实现,由加解密模块、数据缓冲模块、控制模块和密钥扩展模块组成,实现数据的加解密；USB接口控制器采用SOPC软硬结合的方式实现,由SOPC硬件系统平台和NIOSII软核驱动程序两部分组成,实现开发板和PC机之间的通信以及对AES算法模块的控制。
本文首先介绍了设计的背景、FPGA的开发流程、开发环境以及开发工具。接着详细介绍了系统整体设计和实现方案包括AES算法的实现,硬件系统的配置和软件系统的编程。最后介绍了系统上位机的设计和系统仿真与硬件调试。
With the development of information technology and digital society, it is an increasing awareness of the importance of information security, and how to protect computer information security has become the research focus in the IT sector. In this article, USB interface, AES encryption technology and EDA technology are combined in an FPGA, designed of a PC external data encryption device, using the SOPC hardware and software in a concerted way. In the case of the occupation of computer hardware resources, this design can achieve data encryption and decryption on a PC, which guarantees the security of the data. And the key is fixed in the FPGA chip, so we do not have to worry about the inconvenience brought by forgeting the key. This design has both high-speed FPGA itself, security and easy maintenance and flexibility of software and hot-swappable, plug and play of USB, easy to use, cost-effective.
System development hardware platform is FPGA;the operating system is Microsoft Windows XP; development tools are QuartusII9.0, SOPC Builder, Nios II IDE and Microsoft Visual C++.The design is divided into two parts of the software and hardware system. The PC needs to complete the development of user applications and the FPGA needs to complete the hardware development system. Hardware includes the unit of AES algorithm, the USB controller. AES, using hardware description language Verilog, contains the encryption and decryption module, the data buffer module, control module and the key expansion module. AES can achieve the data encryption and decryption between PC and FPGA; USB controller, using SOPC hardware and software combination and containing SOPC hardware platform and NIOSII software, can achieve the communication between board and PC, and control AES module.
Firstly, the background of design, FPGA development process, development environment and tools are introduced.Then, the overall system design and implementation, including the AES algorithm realization, the configuration of the hardware system and software systems programming, are all explained. Finally, introduces the host machine design, system simulation and hardware debugging.
系统开发的硬件平台是FPGA,操作系统平台是Microsoft Windows XP,开发工具是QuartusII9.O、 SOPC Builder和NiosII IDE、 Microsoft Visual C++。系统结构包括软件和硬件两部分。PC主机负责上位机软件部分,完成用户应用程序界面的开发；FPGA开发负责硬件部分,完成AES算法模块和USB接口控制器的开发,其中AES算法单元采用硬件描述语言Verilog实现,由加解密模块、数据缓冲模块、控制模块和密钥扩展模块组成,实现数据的加解密；USB接口控制器采用SOPC软硬结合的方式实现,由SOPC硬件系统平台和NIOSII软核驱动程序两部分组成,实现开发板和PC机之间的通信以及对AES算法模块的控制。
本文首先介绍了设计的背景、FPGA的开发流程、开发环境以及开发工具。接着详细介绍了系统整体设计和实现方案包括AES算法的实现,硬件系统的配置和软件系统的编程。最后介绍了系统上位机的设计和系统仿真与硬件调试。
With the development of information technology and digital society, it is an increasing awareness of the importance of information security, and how to protect computer information security has become the research focus in the IT sector. In this article, USB interface, AES encryption technology and EDA technology are combined in an FPGA, designed of a PC external data encryption device, using the SOPC hardware and software in a concerted way. In the case of the occupation of computer hardware resources, this design can achieve data encryption and decryption on a PC, which guarantees the security of the data. And the key is fixed in the FPGA chip, so we do not have to worry about the inconvenience brought by forgeting the key. This design has both high-speed FPGA itself, security and easy maintenance and flexibility of software and hot-swappable, plug and play of USB, easy to use, cost-effective.
System development hardware platform is FPGA;the operating system is Microsoft Windows XP; development tools are QuartusII9.0, SOPC Builder, Nios II IDE and Microsoft Visual C++.The design is divided into two parts of the software and hardware system. The PC needs to complete the development of user applications and the FPGA needs to complete the hardware development system. Hardware includes the unit of AES algorithm, the USB controller. AES, using hardware description language Verilog, contains the encryption and decryption module, the data buffer module, control module and the key expansion module. AES can achieve the data encryption and decryption between PC and FPGA; USB controller, using SOPC hardware and software combination and containing SOPC hardware platform and NIOSII software, can achieve the communication between board and PC, and control AES module.
Firstly, the background of design, FPGA development process, development environment and tools are introduced.Then, the overall system design and implementation, including the AES algorithm realization, the configuration of the hardware system and software systems programming, are all explained. Finally, introduces the host machine design, system simulation and hardware debugging.
引文
[1]http://tech.sina. com. cn/s/2008-10-10/1524831480. shtml
[2]苏振宇.基于FPGA的DES、3DES硬件加密技术.今日电子,2008(7)：54-55.
[3]周轶男,李曦,冯朝阳.高速全并行的AES加解密算法在单片FPGA上的实现.计算机应用,2004,(s2)：34-39.
[4]刘景亚,季晓勇.基于FPGA的CPRS混沌加解密算法高效实现.电子测量技术,2008(11)：23-24.
[5]程千里,马艳南.基于FPGA+USB接口的硬件加密系统.空矿自动化,2008(2)：47-51.
[6]http://news. zol. com. cn/2001/1019/30873. shtml
[7]高红梅,孙科学.基于USB和EDA的硬件加密系统.现代电子技术,2007(10)：127-130.
[8]http://article.pchome.net/content-28508-2.html
[9]江国强.EDA技术与应用.北京：电子工业出版社,2005.
[10]夏宇闻Verilog数字系统设计教程.北京：航空航天大学出版社,2005.
[11]亿特科技CPLD/FPGA应用系统设计与产品开发.北京：人民邮电出版社,2008.
[12]黑金动力开发板手册.
[13]万隆,巴奉丽.EDA技术及应用.北京：清华大学出版社,2011.
[14]李英兰NiosII嵌入式软核SOPC设计原理及应用.北京：航空航天大学出版社,2006.
[15]赫建国,倪德克,郑燕.基于NIOSII勾核的FPGA电路系统设计.北京：电子工业出版社,2010.
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[18]胡予濮,张玉清,肖国镇.对称密码学.北京：机械工业出版社,2002.
[19]张延伟,杨金岩,葛爱学.Verilog HDL程序设计实例详解.北京：人民邮电出版社,2008.
[20]Joan Daemen, Vincent Rijmen. The design of rijndael AES-The Advanced Encrytion Standard. New York:Springer,2002.
[21]J Daemen, R Govaerts, J Vandewalle. A new approach towards Block Cipher Design. Fast Software Encryption. New York:Springer Verlag,1994.
[22]李洪革FPGA/ASIC高性能数字系统设计.北京：电子工业出版社,2011.
[23]沈启峰,黄士坦,杨靓.AES中有限域运算的优化及算法高速实现.微机发展,2005(15).
[24]佟玉伟,陆浪如,李明等.基于FPGA先进加密算法(AES)的并行实现.交通与计算机,2002,6(20)：15-18.
[25]Xinmiao Zhang, Keshab K.Parhi.High-Speed VLSI Architectures for the AES Algorithm. IEEE Transactions on VLSI Systems.2004,12(9):957-967.
[26]Joan Daemen, Vincent Ri jmen著.谷大武,徐胜波译.高级加密标准(AES)算法一Rijndael的设计.北京：清华大学出社,2003.
[27]韩威,徐火生,方湘艳.EDA与集成电路工程设计.北京：科学出版社,2009.
[28]杨波.现代密码学.北京：清华大学出版社,2002.
[29]阮传概,孙伟.近世代数及其应用.北京：北京邮电大学出版社,2001.
[30]杨小东,王毅.AES密钥扩展新方法.微电子学与计算机,2010(1)：24-26.
[31]胡亮,袁巍,于孟涛,初剑峰,刘方.单向性策略与AES密钥生成算法的改进,吉林大学学报(工学版),2009(1)：52-56.
[32]闫茂德,纪志强,贺昱曜,张阳.AES与ECC混合加密算法的无线数据通信系统设计.微电子学与计算机,2007(7)：32-34.
[33]代大勇.AES算法及其DSP实现.(硕士学位论文).哈尔滨：哈尔滨工业大学,2008.
[34]孙瑜.基于FPGA的数据加解密系统的设计.(硕士学位论文).大连：大连海事大学,2010.
[35]http://www.hqew.com/tech/detail/CH376.html.
[36]洪霞.基于CH376的U盘读写系统的设计与实现.民营科技,2011(12)：42-43.
[37]CH376中文手册
[38]CH372中文手册
[39]童洪洁,李宝华.USB上位机程序开发与设计.仪器仪表用户,2005(1)：62-65.
[40]阴法强.基于USB的矿车速度测量记录系统的研制.(硕士学位论文).山东：山东科技大学,2007.
[41]孙科学.基于USB的硬件加密系统的设计与实现.(硕士学位论文).北京：北京邮电大学,2007：12.
[42]吴鹏,陶正苏,胡宇贞.基于单片机USB接口的PC主机驱动程序和应用程序设计.电子器件,2005(3)：22-25.
[43]李涵.USB接口驱动的研究与设计.(硕士学位论文).山东：山东科技大学,2005：20.
[2]苏振宇.基于FPGA的DES、3DES硬件加密技术.今日电子,2008(7)：54-55.
[3]周轶男,李曦,冯朝阳.高速全并行的AES加解密算法在单片FPGA上的实现.计算机应用,2004,(s2)：34-39.
[4]刘景亚,季晓勇.基于FPGA的CPRS混沌加解密算法高效实现.电子测量技术,2008(11)：23-24.
[5]程千里,马艳南.基于FPGA+USB接口的硬件加密系统.空矿自动化,2008(2)：47-51.
[6]http://news. zol. com. cn/2001/1019/30873. shtml
[7]高红梅,孙科学.基于USB和EDA的硬件加密系统.现代电子技术,2007(10)：127-130.
[8]http://article.pchome.net/content-28508-2.html
[9]江国强.EDA技术与应用.北京：电子工业出版社,2005.
[10]夏宇闻Verilog数字系统设计教程.北京：航空航天大学出版社,2005.
[11]亿特科技CPLD/FPGA应用系统设计与产品开发.北京：人民邮电出版社,2008.
[12]黑金动力开发板手册.
[13]万隆,巴奉丽.EDA技术及应用.北京：清华大学出版社,2011.
[14]李英兰NiosII嵌入式软核SOPC设计原理及应用.北京：航空航天大学出版社,2006.
[15]赫建国,倪德克,郑燕.基于NIOSII勾核的FPGA电路系统设计.北京：电子工业出版社,2010.
[16]http://www. innovateasia.com/cn/win_2008/CN293. htm.
[17]张仕斌,万武南,张金全.应用密码学.西安：西安电子科技大学出版社,2009.
[18]胡予濮,张玉清,肖国镇.对称密码学.北京：机械工业出版社,2002.
[19]张延伟,杨金岩,葛爱学.Verilog HDL程序设计实例详解.北京：人民邮电出版社,2008.
[20]Joan Daemen, Vincent Rijmen. The design of rijndael AES-The Advanced Encrytion Standard. New York:Springer,2002.
[21]J Daemen, R Govaerts, J Vandewalle. A new approach towards Block Cipher Design. Fast Software Encryption. New York:Springer Verlag,1994.
[22]李洪革FPGA/ASIC高性能数字系统设计.北京：电子工业出版社,2011.
[23]沈启峰,黄士坦,杨靓.AES中有限域运算的优化及算法高速实现.微机发展,2005(15).
[24]佟玉伟,陆浪如,李明等.基于FPGA先进加密算法(AES)的并行实现.交通与计算机,2002,6(20)：15-18.
[25]Xinmiao Zhang, Keshab K.Parhi.High-Speed VLSI Architectures for the AES Algorithm. IEEE Transactions on VLSI Systems.2004,12(9):957-967.
[26]Joan Daemen, Vincent Ri jmen著.谷大武,徐胜波译.高级加密标准(AES)算法一Rijndael的设计.北京：清华大学出社,2003.
[27]韩威,徐火生,方湘艳.EDA与集成电路工程设计.北京：科学出版社,2009.
[28]杨波.现代密码学.北京：清华大学出版社,2002.
[29]阮传概,孙伟.近世代数及其应用.北京：北京邮电大学出版社,2001.
[30]杨小东,王毅.AES密钥扩展新方法.微电子学与计算机,2010(1)：24-26.
[31]胡亮,袁巍,于孟涛,初剑峰,刘方.单向性策略与AES密钥生成算法的改进,吉林大学学报(工学版),2009(1)：52-56.
[32]闫茂德,纪志强,贺昱曜,张阳.AES与ECC混合加密算法的无线数据通信系统设计.微电子学与计算机,2007(7)：32-34.
[33]代大勇.AES算法及其DSP实现.(硕士学位论文).哈尔滨：哈尔滨工业大学,2008.
[34]孙瑜.基于FPGA的数据加解密系统的设计.(硕士学位论文).大连：大连海事大学,2010.
[35]http://www.hqew.com/tech/detail/CH376.html.
[36]洪霞.基于CH376的U盘读写系统的设计与实现.民营科技,2011(12)：42-43.
[37]CH376中文手册
[38]CH372中文手册
[39]童洪洁,李宝华.USB上位机程序开发与设计.仪器仪表用户,2005(1)：62-65.
[40]阴法强.基于USB的矿车速度测量记录系统的研制.(硕士学位论文).山东：山东科技大学,2007.
[41]孙科学.基于USB的硬件加密系统的设计与实现.(硕士学位论文).北京：北京邮电大学,2007：12.
[42]吴鹏,陶正苏,胡宇贞.基于单片机USB接口的PC主机驱动程序和应用程序设计.电子器件,2005(3)：22-25.
[43]李涵.USB接口驱动的研究与设计.(硕士学位论文).山东：山东科技大学,2005：20.