纠错码硬件加速器模板关键技术研究
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摘要
信道译码是软件无线电的关键环节,主要用差错控制的方法来纠正经过信道传输后所接收的码元错误。信道译码通过纠错码技术来实现。所谓纠错码技术,就是一种通过增加校验信息来提高信息传输可靠性的有效方法。常用的纠错码主要有卷积码、Turbo码、RS码和LDPC码四种。在不同的通信系统中,纠错码种类的不同;而同一类型的纠错码在不同的通信系统中参数标准也不尽相同。现代通信越来越倾向于实现各种不同标准的通信系统间的通信,传统的ASIC系统已经很难适应多变的需求。为了提高兼容性,译码器必须实现参数化可配置计算。基于FPGA的译码器模板便应运而生。
本文针对纠错码中的卷积码、Turbo码、RS码和LDPC码这四种纠错码,分析了其译码原理及参数类型,设计每类纠错码的译码器模板,根据参数的变化自适应选择相应的体系结构,实现了不同通信系统中纠错码的参数化可配置译码,有效地实现了译码器的兼容性,以适应通信中的不同应用环境。
本文还对四类纠错码可重构译码器构建技术进行了研究,设计了动态可重构纠错码译码器原型系统,对可重构译码器的存储结构、配置字控制技术进行了研究,并将四种纠错码的译码器在原型系统中进行了映射实现。
Channel decoder is the vital link of the SDR (Software Defined Radio). The purpose of channel decoder is to correct the error of the received codes travelling through channel by means of the error control method. Channel docoder is implemented by error correction coding, an effective method to enhance the thransmission authenticity by adding the parity bits into the code. There are four popular FEC (Forward Error Correction Codes): convolution code, Turbo, RS and LDPC. The type of the FEC varies in different communication systems and the parameters of the same type FEC also vary in different communication systems. Unfortunately, it is a tendency to communicate between several systems with different standards in modern communication. Tranditional ASIC can not meet the changeful requirement of the new comminication systems. So the docoder should support configurable parametric computation to elevate its compatibility. The template docoder on FPGA is designed to slove the problem.
Four FEC were studied in this paper: convolution code, Turbo, RS and LDPC. The decode principle and the parameters of each type of FEC were analysed firstly in this paper. The designed decoder template of each type of FEC can alter its architecture based on different parameters. The decoder template was designed to support configurable parametric decode process to realize the portability and compatibility to adjust the varied environment of communication.
The study to FEC prototype decoder building was also made in this paper. The structure of dynamic reconfigurable system was designed. The design of configurable storage and the control technology of configurable instructions were studied and implement in the prototype. Each type of FEC docoder can be implemented in this prototype perfectly.
本文针对纠错码中的卷积码、Turbo码、RS码和LDPC码这四种纠错码,分析了其译码原理及参数类型,设计每类纠错码的译码器模板,根据参数的变化自适应选择相应的体系结构,实现了不同通信系统中纠错码的参数化可配置译码,有效地实现了译码器的兼容性,以适应通信中的不同应用环境。
本文还对四类纠错码可重构译码器构建技术进行了研究,设计了动态可重构纠错码译码器原型系统,对可重构译码器的存储结构、配置字控制技术进行了研究,并将四种纠错码的译码器在原型系统中进行了映射实现。
Channel decoder is the vital link of the SDR (Software Defined Radio). The purpose of channel decoder is to correct the error of the received codes travelling through channel by means of the error control method. Channel docoder is implemented by error correction coding, an effective method to enhance the thransmission authenticity by adding the parity bits into the code. There are four popular FEC (Forward Error Correction Codes): convolution code, Turbo, RS and LDPC. The type of the FEC varies in different communication systems and the parameters of the same type FEC also vary in different communication systems. Unfortunately, it is a tendency to communicate between several systems with different standards in modern communication. Tranditional ASIC can not meet the changeful requirement of the new comminication systems. So the docoder should support configurable parametric computation to elevate its compatibility. The template docoder on FPGA is designed to slove the problem.
Four FEC were studied in this paper: convolution code, Turbo, RS and LDPC. The decode principle and the parameters of each type of FEC were analysed firstly in this paper. The designed decoder template of each type of FEC can alter its architecture based on different parameters. The decoder template was designed to support configurable parametric decode process to realize the portability and compatibility to adjust the varied environment of communication.
The study to FEC prototype decoder building was also made in this paper. The structure of dynamic reconfigurable system was designed. The design of configurable storage and the control technology of configurable instructions were studied and implement in the prototype. Each type of FEC docoder can be implemented in this prototype perfectly.
引文
[1]王新梅,肖国镇.纠错码—原理与方法(修订版).西安电子科技大学出版社.2001.
[2] Engling Yeo, Stephanie A. Augsburger, W. Rhett Davis. A 500-Mb/s soft-output Viterbi decoder. IEEE Journal Solid-State Circuits. 2003(38):1234-1241.
[3] Peter J. Black, Teresa H. Meng. A 140-Mb/s, 32-state radix-4 Viterbi decoder. IEEE Journal Solid-State Circuits. 1992. 27(12):1877-1885.
[4] Xun Liu, Marios C. Papaefthymiou. Design of a 20-Mb/s 256-state Viterbi decoder. IEEE Tram. on very large scale integration system(VLSI). 2003,11(6):965-975.
[5]乔峰,陈进等.Soft-core IP的低功耗设计.通信技术.2003(9):22-24.
[6]孙猛.VB高速译码算法及其FPGA实现.中国有线电视. 2004(3):13-18.
[7] C. B. Shung, P. H. Siegel, G. Ungerboeck. VLSI architectures for metric normalization in the Viterbi algorithm. IEEE international conf. comm. 1990(4):1723-1728.
[8]韩燕,王匡.一种寄存器回索型Viterbi译码器的VLSI设计.浙江大学学报(自然科学版).1997,31(4):539-546.
[9] Gennady Feygin, P. G. Gulak. Architectural tradeoffs fof survivor sequence memory management in Viterbi decoders. IEEE Trans. Comm.1993,41(3):425-429.
[10] P. J. Black, T. H. Y. Meng. Hybrid survivor path architectures for Viterbi decoders. Proc.ICASSP93. 1993:1433.
[11] C. M. Rader. Memory management in a Viterbi decoder. IEEE Trans. Comm. 1981,29(9):1339-1401.
[12]张荣兵.参数化Viterbi译码器的FPGA实现[硕士学位论文].哈尔滨:哈尔滨工程大学信息与通信工程学院.2005.2.
[13]张弓.可配置的Viterbi译码器的FPGA实现[硕士学位论文].西安:西安电子科技大学通信与信息系统学院.2009.1.
[14]张普珩,李宗伯,张波涛.一种可配置Viterbi译码器的FPGA实现.中国计算机学会.2008:341-244.
[15]张婷.无线信道可配置Turbo译码组件技术研究[硕士学位论文].西安:西安电子科技大学通信与信息系统学院.2009.1.
[16] Bickerstaff M., Davis,L., Thomas C., etc. A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless. Solid-State Circuits Conference, Digest of Technical Papers,ISSCC. 2003(1):150-484.
[17] S. Papaharalabos, P. Sweeney, B. Gevans. SISO algorithms based on Max-Log-MAP and Log-MAP turbo decoding. 1ET Communication. 2007,l(1):49-54.
[18] Hao Wang, Hongwen Yang, Dacheng Yang. Improved Log_MAP Decoding Algorithm for MO. 1ike Codes. IEEE Communications Letters. 2006,10(3):l86-l 88.
[19]楼喜中,毛志刚.Turbo码Log-MAP译码算法简化实现的研究.航空学报.2005,26(5):581-586.
[20] Zhongfeng Wang. High-Speed Recursion Architectures for MAP-Based Turbo Decoders. IEEE Transactions on Very Large Scale Integration systems. 2007,15(4): 470-474.
[21] S. Lee, N. Shanbhag, A. Singer. Area efficient high-throughput MAP decoder architecture. In IEEE Transacions Oil VLSI Systems. 2005,13(8):921-933.
[22] Perttu Salmela, Tuomas Jarvinen, Jarmo Takala. Simplified max-log-MAP Decoder Structure. IEEE Transactions on Communications. 2006:10-13.
[23] J. Kim, H. Park, B. Kim, etc. Modified enhanced max-log-maximum a postefiori algorithm using variable scaling factor. IET Communication. 2007,1(5):1061-1066.
[24] Leila Sabeti, Majid Ahrnadi, Kemal Tepe. New VLSI Design of a Max-Log-MAP Decoden IEEE Northeast Workshop on Circuits and Systems. 2004:37-40.
[25] Ming Li, Ming-ming Peng, Jing-sai Jiang, etc. A Pipeline Sliding Window Max-Log-Map Turbo Decoder. Proceedings of HDP’07. 2007:1-4.
[26]黄懿,周兴建,余金权,阎鸿森.高码率自适应Turbo编译码器的设计余FPGA实现.电视技术.2008.48(3):82-85.
[27] Leon W. Couch. Digital and Analog Communication Systems(第六版).北京科学出版社.2003.
[28] Shu Lin, Daniel J. Costello, Jr. Error Control Coding(Second Edition).机械工业出版社.2007.
[29]吕超英.RS、LDPC纠错码及其级联的研究[硕士学位论文].西安:电子科技大学信号与信息处理专业.2008.5.
[30]杨波,尹俊勋,石雷.一种用于IP差错控制的RS译码器及其FPGA实现.华南理工大学学报(自然科学版).2004,32(11):66-69.
[31]宋文妙,刘丽萍,张淑娥.纠两位错位RS码解码的FPGA实现.华北电力大学学报.2004,31(3):85-88.
[32]曾德才,魏廷存.基于ME算法的RS译码器的原理和FPGA实现.科学技术与工程.2007,7(9):1886-1889.
[33]何涌,潘泽友.基于FPGA的RS译码器实现.通信技术.2007,40(11):30-32.
[34]陈启亮,余宁梅,刘高辉.变参数RS译码器IP核的实现.固体电子学研究与进展.2005,25(3):357-360.
[35] R. G. Gallager. Low Density Parity Check Codes. IRE Trans on InformationTheory. 1962, IT -8:21-28.
[36] D. J. C. Mackay, R. M. Neal. Near Shannon Limit Performance of Low Density Parity Check Codes. Electronic Lett. 1996, 32(18):1645-1646.
[37] M. Sipser, D. Spilelman. Expander Codes. IEEE Trans on Information Theory. 1981, 42(6):1710-1722.
[38] R. G. Gallager. Low Density Parity Check Codes. MIT Press, Cambridge, 1963.
[39] Logliger H. A. Probablity Propagation and Decoding in Analog VLSI. IEEE Trans on Information Theory. 2001, 47(2):937-843.
[40]王文君,朱晓暄,康桂霞,张平.结构化LDPC码的高速编译码器FPGA实现.数据采集和处理.2008,23(S):113-118.
[2] Engling Yeo, Stephanie A. Augsburger, W. Rhett Davis. A 500-Mb/s soft-output Viterbi decoder. IEEE Journal Solid-State Circuits. 2003(38):1234-1241.
[3] Peter J. Black, Teresa H. Meng. A 140-Mb/s, 32-state radix-4 Viterbi decoder. IEEE Journal Solid-State Circuits. 1992. 27(12):1877-1885.
[4] Xun Liu, Marios C. Papaefthymiou. Design of a 20-Mb/s 256-state Viterbi decoder. IEEE Tram. on very large scale integration system(VLSI). 2003,11(6):965-975.
[5]乔峰,陈进等.Soft-core IP的低功耗设计.通信技术.2003(9):22-24.
[6]孙猛.VB高速译码算法及其FPGA实现.中国有线电视. 2004(3):13-18.
[7] C. B. Shung, P. H. Siegel, G. Ungerboeck. VLSI architectures for metric normalization in the Viterbi algorithm. IEEE international conf. comm. 1990(4):1723-1728.
[8]韩燕,王匡.一种寄存器回索型Viterbi译码器的VLSI设计.浙江大学学报(自然科学版).1997,31(4):539-546.
[9] Gennady Feygin, P. G. Gulak. Architectural tradeoffs fof survivor sequence memory management in Viterbi decoders. IEEE Trans. Comm.1993,41(3):425-429.
[10] P. J. Black, T. H. Y. Meng. Hybrid survivor path architectures for Viterbi decoders. Proc.ICASSP93. 1993:1433.
[11] C. M. Rader. Memory management in a Viterbi decoder. IEEE Trans. Comm. 1981,29(9):1339-1401.
[12]张荣兵.参数化Viterbi译码器的FPGA实现[硕士学位论文].哈尔滨:哈尔滨工程大学信息与通信工程学院.2005.2.
[13]张弓.可配置的Viterbi译码器的FPGA实现[硕士学位论文].西安:西安电子科技大学通信与信息系统学院.2009.1.
[14]张普珩,李宗伯,张波涛.一种可配置Viterbi译码器的FPGA实现.中国计算机学会.2008:341-244.
[15]张婷.无线信道可配置Turbo译码组件技术研究[硕士学位论文].西安:西安电子科技大学通信与信息系统学院.2009.1.
[16] Bickerstaff M., Davis,L., Thomas C., etc. A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless. Solid-State Circuits Conference, Digest of Technical Papers,ISSCC. 2003(1):150-484.
[17] S. Papaharalabos, P. Sweeney, B. Gevans. SISO algorithms based on Max-Log-MAP and Log-MAP turbo decoding. 1ET Communication. 2007,l(1):49-54.
[18] Hao Wang, Hongwen Yang, Dacheng Yang. Improved Log_MAP Decoding Algorithm for MO. 1ike Codes. IEEE Communications Letters. 2006,10(3):l86-l 88.
[19]楼喜中,毛志刚.Turbo码Log-MAP译码算法简化实现的研究.航空学报.2005,26(5):581-586.
[20] Zhongfeng Wang. High-Speed Recursion Architectures for MAP-Based Turbo Decoders. IEEE Transactions on Very Large Scale Integration systems. 2007,15(4): 470-474.
[21] S. Lee, N. Shanbhag, A. Singer. Area efficient high-throughput MAP decoder architecture. In IEEE Transacions Oil VLSI Systems. 2005,13(8):921-933.
[22] Perttu Salmela, Tuomas Jarvinen, Jarmo Takala. Simplified max-log-MAP Decoder Structure. IEEE Transactions on Communications. 2006:10-13.
[23] J. Kim, H. Park, B. Kim, etc. Modified enhanced max-log-maximum a postefiori algorithm using variable scaling factor. IET Communication. 2007,1(5):1061-1066.
[24] Leila Sabeti, Majid Ahrnadi, Kemal Tepe. New VLSI Design of a Max-Log-MAP Decoden IEEE Northeast Workshop on Circuits and Systems. 2004:37-40.
[25] Ming Li, Ming-ming Peng, Jing-sai Jiang, etc. A Pipeline Sliding Window Max-Log-Map Turbo Decoder. Proceedings of HDP’07. 2007:1-4.
[26]黄懿,周兴建,余金权,阎鸿森.高码率自适应Turbo编译码器的设计余FPGA实现.电视技术.2008.48(3):82-85.
[27] Leon W. Couch. Digital and Analog Communication Systems(第六版).北京科学出版社.2003.
[28] Shu Lin, Daniel J. Costello, Jr. Error Control Coding(Second Edition).机械工业出版社.2007.
[29]吕超英.RS、LDPC纠错码及其级联的研究[硕士学位论文].西安:电子科技大学信号与信息处理专业.2008.5.
[30]杨波,尹俊勋,石雷.一种用于IP差错控制的RS译码器及其FPGA实现.华南理工大学学报(自然科学版).2004,32(11):66-69.
[31]宋文妙,刘丽萍,张淑娥.纠两位错位RS码解码的FPGA实现.华北电力大学学报.2004,31(3):85-88.
[32]曾德才,魏廷存.基于ME算法的RS译码器的原理和FPGA实现.科学技术与工程.2007,7(9):1886-1889.
[33]何涌,潘泽友.基于FPGA的RS译码器实现.通信技术.2007,40(11):30-32.
[34]陈启亮,余宁梅,刘高辉.变参数RS译码器IP核的实现.固体电子学研究与进展.2005,25(3):357-360.
[35] R. G. Gallager. Low Density Parity Check Codes. IRE Trans on InformationTheory. 1962, IT -8:21-28.
[36] D. J. C. Mackay, R. M. Neal. Near Shannon Limit Performance of Low Density Parity Check Codes. Electronic Lett. 1996, 32(18):1645-1646.
[37] M. Sipser, D. Spilelman. Expander Codes. IEEE Trans on Information Theory. 1981, 42(6):1710-1722.
[38] R. G. Gallager. Low Density Parity Check Codes. MIT Press, Cambridge, 1963.
[39] Logliger H. A. Probablity Propagation and Decoding in Analog VLSI. IEEE Trans on Information Theory. 2001, 47(2):937-843.
[40]王文君,朱晓暄,康桂霞,张平.结构化LDPC码的高速编译码器FPGA实现.数据采集和处理.2008,23(S):113-118.