基于SystemC的RS编码器设计
摘要
论文针对新型SOC设计语言SystemC及其平台提出了基于SystemC的设计方法及
设计流程,并以RS(15,9) 编码器作为设计对象,采用基于SystemC的设计方法对
其进行了设计。
首先,论文通过对目前集成电路开发的发展现状和发展趋势的分析,论证了使
用系统级设计语言进行设计的必要性,说明了采用目前作为这个方向研究热点的
SystemC进行设计的意义。
其次,对设计对象RS(15,9) 编码器的工作原理和实现方式进行了扼要的介绍。
在此基础上,使用systemC具体实现了RS(15,9) 编码器。主要包括:对系统划分模
块和对各个模块进行基于SystemC的建模,然后把所有模块整合并加入测试模块后
进行了编译和仿真,并与手工计算结果和采用Verilog的设计仿真所得结果进行了
比较,初步验证了基于SystemC设计的RS(15,9) 编码器的合理性和正确性。同时,
在这部分还对在设计过程中的一些关于SystemC编程的体会做了总结。
最后,对SystemC代码进行了可综合代码修改,使用SystemC Compiler进行了
综合,同时对SystemC中不可综合子集进行了总结。然后,用FPGA进行了功能验证,
验证结果表明本设计完全达到了设计要求。
By means of the new SOC design language SystemC and it's flat roof, the idea and design flow of the design based on SystemC are presented, at the same time, a RS encoder was designed by using SystemC in the paper.Firstly, the paper discusses the necessity of using the system language in design by analyzing and the requirement and actual development of designing the IC. So design by using SystemC which is as the hotspot of the SOC design is meaningful.Secondly, the theory and realization of RS encoder is introduced compendiously in the paper, and then the RS (15, 9) encoder is realized by using SystemC. The main process includes following: divide the system into several modules and model them by using SystemC. Then, after the code of each module is assembled to form the code of whole system and the code of testbench is added into the project, the project is compiled and simulated. The rationality and correctness about the design of RS (15, 9) based on SystemC is validated by comparing the result with the result of handwork and the result of simulation. Together, in this part the experience in the process of this project about coding SystemC code is summed up.Lastly, the SystemC code is amended for synthesis and synthesised by
using the SystemC Compiler. Together, the unsynthesizable subset is summarized. Then, FPGA is used to test the function of the project. The result of FPGA test shows that the design fully has accomplished the requirements.
设计流程,并以RS(15,9) 编码器作为设计对象,采用基于SystemC的设计方法对
其进行了设计。
首先,论文通过对目前集成电路开发的发展现状和发展趋势的分析,论证了使
用系统级设计语言进行设计的必要性,说明了采用目前作为这个方向研究热点的
SystemC进行设计的意义。
其次,对设计对象RS(15,9) 编码器的工作原理和实现方式进行了扼要的介绍。
在此基础上,使用systemC具体实现了RS(15,9) 编码器。主要包括:对系统划分模
块和对各个模块进行基于SystemC的建模,然后把所有模块整合并加入测试模块后
进行了编译和仿真,并与手工计算结果和采用Verilog的设计仿真所得结果进行了
比较,初步验证了基于SystemC设计的RS(15,9) 编码器的合理性和正确性。同时,
在这部分还对在设计过程中的一些关于SystemC编程的体会做了总结。
最后,对SystemC代码进行了可综合代码修改,使用SystemC Compiler进行了
综合,同时对SystemC中不可综合子集进行了总结。然后,用FPGA进行了功能验证,
验证结果表明本设计完全达到了设计要求。
By means of the new SOC design language SystemC and it's flat roof, the idea and design flow of the design based on SystemC are presented, at the same time, a RS encoder was designed by using SystemC in the paper.Firstly, the paper discusses the necessity of using the system language in design by analyzing and the requirement and actual development of designing the IC. So design by using SystemC which is as the hotspot of the SOC design is meaningful.Secondly, the theory and realization of RS encoder is introduced compendiously in the paper, and then the RS (15, 9) encoder is realized by using SystemC. The main process includes following: divide the system into several modules and model them by using SystemC. Then, after the code of each module is assembled to form the code of whole system and the code of testbench is added into the project, the project is compiled and simulated. The rationality and correctness about the design of RS (15, 9) based on SystemC is validated by comparing the result with the result of handwork and the result of simulation. Together, in this part the experience in the process of this project about coding SystemC code is summed up.Lastly, the SystemC code is amended for synthesis and synthesised by
using the SystemC Compiler. Together, the unsynthesizable subset is summarized. Then, FPGA is used to test the function of the project. The result of FPGA test shows that the design fully has accomplished the requirements.
引文
[1] 陈曦,徐宁仪,SystemC片上系统设计.北京:科学出版社。2004
[2] SystemC version2. 01 User's Guide.Synopsys.Inc,2002
[3] FUNCTIONAL SPECIFICATION FOR SYSTEMC 2. 0, Synopsys, 2002
[4] Bartleson K.A new standard for system-level design.synopsys Inc,1999
[5] Ghosh A,Kunkel J,Liao S.Hardware synthesis from C/C++.Proceeding of the DATE'99 Conference, 1999,382-383
[6] 刘珂,郑学仁,李斌.软硬件协同设计语言SystemC在SOC设计中的应用. 半 导体技术.27(4) .2002:22-25
[7] 肖有军,赵虹,李智.SystemC:一种新的系统建模语言.微电子学与计算 机.11. 2002:58-60
[8] 陈咏恩.SystemC一种软/硬件协同设计语言.电路与系统学报.6(1) .2001
[9] 石柯.基于SystemC的嵌入式系统设计.小型微型计算机系 统.24(4) .2003:763-765
[10] 欧阳坚,沈海斌,严晓浪.系统级芯片设计与SystemC.微电子学 32 (6) .2002:453-456
[11] 赵川,徐涛,孙晓光.软硬件协同设计方法的研究.计算机工程与设 计.24(7) :7-9
[12] 罗琨,曹阳,尹建华,黄天赐,赵磊.数字专用集成电路设计中的SystemC 建模验证方法.武汉大学学报.48(3) .2002:306-310
[13] (美)S.林 著;陈太一 译.《纠错码入门》.北京:人民邮电出版社,1976
[14] 王新梅,肖国镇著. 《纠错码-原理与方法》.西安:西安电子科技大学 出版社,2001
[15] 樊昌信,张甫翊,徐炳祥,吴成柯著. 《通信原理》.北京:国防工业 出版社,2001
[16] Lee M H,Choi S B, Chang J S. A high speed Reed-Solomon encoder[J].IEEE Trans Consumer Electronics. 41(4) . 1995:1142-1149
[17] BERLEKAMP ELWNR. Bit-serial Reed-Solomon encoders [J].IEEE Trans on Information Theory. IT-28(6) :869-873
[18] TJFenn S,Benaissa M, David Taylor. GF(2(?)) multiplication and division over the dual basis[J]. IEEE Trans Computer.45(3) . 1995:319-327
[19] 王进祥,毛志刚,叶以正.GF(28) 上快速乘法器及求逆器的设计.微电子 学.28(5) .1998:321-324
[20] 陶德元,何小海,吴志华.RS码编译码算法的实现,四川大学学 报.37. 2000. 12
[21] 柳平,郭毅杰.RS(255,239) 码编码器的设计与实现.汕头大学学报(自然 科学版).17(1) .2002:58-63
[22] 董怀玉,余宁梅,高勇,刘高辉,牛兰奇,陈静瑾.变参数RS编码器IP 核的设计与实现.24(2) .2004:186-190
[23] (美)J.Bhasker著;徐振林等 译. 《Verilog HDL 硬件描述语言》. 北京:机械工业出版社,2000
[24] 张明 著.《Verilog HDL 实用教程》.成都:电子科技大学出版社,1999
[25] 复宇闻.Verilog数字系统设计教程.北京:北京航空航天大学出版 社.2003:4-15
[26] 曾繁泰,李冰,李晓林,EDA 工程概论,清华大学出版社,2002:61-68
[27] Nigel Horspool Peter Gorman,The ASIC Handbook(ASIC完备指南) 清 华大学出版社2002. 11
[28] SystemC Compiler Release Not,synopsys,2000
[29] CoCentricTM SystemC Compiler Behavioral Modeling Guide, synopsys,2001
[30] CoCentricTM SystemC Compiler Quick Reference,synopsys,2001
[31] CoCentricTM SystemC Compiler Behaviora User Guide,synopsys,2001
[32] CoCentricTM SystemC Compiler RTL User and Modeling Guide,synopsys,2001
[2] SystemC version2. 01 User's Guide.Synopsys.Inc,2002
[3] FUNCTIONAL SPECIFICATION FOR SYSTEMC 2. 0, Synopsys, 2002
[4] Bartleson K.A new standard for system-level design.synopsys Inc,1999
[5] Ghosh A,Kunkel J,Liao S.Hardware synthesis from C/C++.Proceeding of the DATE'99 Conference, 1999,382-383
[6] 刘珂,郑学仁,李斌.软硬件协同设计语言SystemC在SOC设计中的应用. 半 导体技术.27(4) .2002:22-25
[7] 肖有军,赵虹,李智.SystemC:一种新的系统建模语言.微电子学与计算 机.11. 2002:58-60
[8] 陈咏恩.SystemC一种软/硬件协同设计语言.电路与系统学报.6(1) .2001
[9] 石柯.基于SystemC的嵌入式系统设计.小型微型计算机系 统.24(4) .2003:763-765
[10] 欧阳坚,沈海斌,严晓浪.系统级芯片设计与SystemC.微电子学 32 (6) .2002:453-456
[11] 赵川,徐涛,孙晓光.软硬件协同设计方法的研究.计算机工程与设 计.24(7) :7-9
[12] 罗琨,曹阳,尹建华,黄天赐,赵磊.数字专用集成电路设计中的SystemC 建模验证方法.武汉大学学报.48(3) .2002:306-310
[13] (美)S.林 著;陈太一 译.《纠错码入门》.北京:人民邮电出版社,1976
[14] 王新梅,肖国镇著. 《纠错码-原理与方法》.西安:西安电子科技大学 出版社,2001
[15] 樊昌信,张甫翊,徐炳祥,吴成柯著. 《通信原理》.北京:国防工业 出版社,2001
[16] Lee M H,Choi S B, Chang J S. A high speed Reed-Solomon encoder[J].IEEE Trans Consumer Electronics. 41(4) . 1995:1142-1149
[17] BERLEKAMP ELWNR. Bit-serial Reed-Solomon encoders [J].IEEE Trans on Information Theory. IT-28(6) :869-873
[18] TJFenn S,Benaissa M, David Taylor. GF(2(?)) multiplication and division over the dual basis[J]. IEEE Trans Computer.45(3) . 1995:319-327
[19] 王进祥,毛志刚,叶以正.GF(28) 上快速乘法器及求逆器的设计.微电子 学.28(5) .1998:321-324
[20] 陶德元,何小海,吴志华.RS码编译码算法的实现,四川大学学 报.37. 2000. 12
[21] 柳平,郭毅杰.RS(255,239) 码编码器的设计与实现.汕头大学学报(自然 科学版).17(1) .2002:58-63
[22] 董怀玉,余宁梅,高勇,刘高辉,牛兰奇,陈静瑾.变参数RS编码器IP 核的设计与实现.24(2) .2004:186-190
[23] (美)J.Bhasker著;徐振林等 译. 《Verilog HDL 硬件描述语言》. 北京:机械工业出版社,2000
[24] 张明 著.《Verilog HDL 实用教程》.成都:电子科技大学出版社,1999
[25] 复宇闻.Verilog数字系统设计教程.北京:北京航空航天大学出版 社.2003:4-15
[26] 曾繁泰,李冰,李晓林,EDA 工程概论,清华大学出版社,2002:61-68
[27] Nigel Horspool Peter Gorman,The ASIC Handbook(ASIC完备指南) 清 华大学出版社2002. 11
[28] SystemC Compiler Release Not,synopsys,2000
[29] CoCentricTM SystemC Compiler Behavioral Modeling Guide, synopsys,2001
[30] CoCentricTM SystemC Compiler Quick Reference,synopsys,2001
[31] CoCentricTM SystemC Compiler Behaviora User Guide,synopsys,2001
[32] CoCentricTM SystemC Compiler RTL User and Modeling Guide,synopsys,2001