片上网络演算模型及性能分析
详细信息    本馆镜像全文|  推荐本文 |  |   获取CNKI官网全文
摘要
随着半导体技术的迅猛发展,集成芯片中处理器核的数量日益增长,全局互连将导致严重的片上同步错误、不可预知的通信延迟和巨大的功耗开销。为了缓和这些矛盾,片上网络(Network-on-Chip,NoC)应运而生,替代传统的总线或点到点互连成为片上新的通信架构。NoC除具有更好的可预测性和更低的功耗开销,而且能提供更好的可扩展性以应对成百个处理器核的互连。性能分析是NoC一个重要的研究方向,对于构建性能可预测的系统、提供端到端的QoS保证和加速设计空间搜索意义重大。本文基于网络演算对片上网络进行系统建模和性能分析,重点推导业务流的端到端延迟上界,研究提供尽力服务的分组交换NoC中,网络冲突、拓扑结构、流量控制、交换策略及缓冲区大小对通信性能的影响。主要研究内容包括以下四个方面:
     (1)NoC中多业务流竞争网络资源的冲突模型
     在分组交换NoC中,业务流的冲突情形复杂多样,冲突情形可被划分为三种基本模式:嵌套、平行和交叉。分析了这三种基本冲突模式并分别得到了它们的分析模型。对于多条冲突流流经节点串的复杂情形,可以分解成基本模型并使用冲突树进行描述。冲突树模型不仅能描述目标流在其传输路径上与其他冲突流的冲突,而且能刻画多条冲突流所经历的间接冲突。通过遍历冲突树计算所有冲突流流经冲突树树枝后的输出曲线,进而推导出树干提供给目标流的等价服务曲线,并计算目标流的延迟上界。整个分析过程可归纳为两个主要算法:冲突树生成算法和等价服务曲线推导算法。研究了并行处理中重要的集合操作–多对一聚合通信,并推导了聚合通信的延迟上界计算公式。模拟实验验证了模拟和分析结果的一致性。比较了Bakhouya模型、Fidler模型和冲突树模型的延迟结果。
     (2)NoC二维和三维拓扑通信性能的对比分析
     芯片集成技术的迅猛发展,使得片上网络从二维向三维扩展成为一个重要的发展方向。三维NoC因拓扑维度的增加而缩短了通信距离,极大的提升了网络的平均通信性能。对比分析了规则的k-ary-2-mesh网络及其对应的三维网络在最差情形下的通信性能,得出一个重要结论:将二维NoC转换成三维NoC,虽然能提高网络的平均性能,但最差情形下的性能不一定能得到提升。最差情形下的通信延迟对垂直链路带宽、网络规模和流量突发这些网络参数的取值更为敏感。在垂直链路带宽较窄、网络规模较小和流量突发较大的情况下,三维网络最差情形下的通信性能明显劣于二维网络。这表明在优化NoC设计,将网络拓扑从二维扩展到三维时,需要全面考虑和衡量通信性能,不仅平均延迟要得到保证,最差情形下的延迟也不容忽视。
     (3)NoC基于信约的链路级流量控制机制的性能分析
     基于信约的路由器到路由器流量控制机制是NoC主要采用的链路级流量控制机制。基于网络演算分析了基于信约的流量控制机制的性能和最优缓冲区大小。为了对信约的反馈控制行为进行建模,提出了一个抽象的网络服务元素–流量控制器,以定理形式推导了流量控制器和整个系统的服务曲线。另外,给出并证明了保证系统最大服务曲线的最优缓冲区分配定理。假设路由器提供延迟-速率服务,给出了微包延迟上界和最优缓冲区大小的计算公式。片上多媒体流的模拟实验验证了模拟和分析结果的一致性及最优缓冲区大小的准确性。
     (4)NoC虚通道虫孔交换策略的性能分析
     基于网络演算分析了无死锁的虚通道虫孔交换NoC中业务流最差情形下的微包延迟上界。在虫孔交换NoC中,报文的传输可能因为信约短缺、交换机或虚通道分配失败而阻塞。构建了业务流在这些阻塞条件下的资源共享分析模型。分别利用流量控制和链路共享分析模型消去初始模型中的反馈控制和链路共享,保留初始模型的缓冲区共享和网络结构,得到一个简化的分析模型–缓冲区共享分析网络。从而将问题转化到冲突树模型中,推导路由器节点串提供给业务流的端到端等价服务曲线。给出了缓冲区共享分析网络的构建算法,并总结了虫孔交换NoC的延迟上界分析方法。假设仿射到达曲线和延迟-速率服务曲线,推导了延迟上界的计算公式。
     综上所述,本文紧紧围绕“分析业务流端到端的延迟上界”这一目标,基于网络演算提出了NoC的冲突树演算模型、拓扑性能对比分析模型、流量控制演算模型和虫孔交换演算模型,为NoC建立了一套完备的确定性性能分析方法,为网络演算这一新兴的数学理论开辟了一个新的应用领域。
With the rapid development of semiconductor technology, the number of cores ona single chip continues to increase, the global interconnects would cause severe on-chipsynchronization errors, unpredictable delays, and high power consumption. To mitigatethese effects, the Network-on-Chip (NoC) approach emerged recently as a promising al-ternative to classical bus-based and point-to-point (P2P) communication architectures.Aside from better predictability and lower power consumption, the NoC approach offersgreater scalability compared to previous solutions for on-chip communication. Perfor-mance analysis has been a major concern for NoC and plays an increasingly importantroleinbuildingpredictablecommunicationsystem, providingend-to-endQoSguaranteesand speeding up the design space exploring. This thesis employs network calculus to per-form systematic modeling and performance analysis on NoCs with focusing on per-flowend-to-end delay bound. The effects of network contentions, topologies, flow control,switching strategies and buffer size are analyzed on the communication performance inpacket-switching NoCs with best-effort services. The main contributions are:
     (1) Contention model for multiple flows sharing resources in NoCs
     In packet-switching NoCs, network flow contention scenarios are diverse and com-plicated. The contention scenarios the tagged flow may experience can be classified intothree patterns, Nested, Parallel and Crossed. Based on these patterns, any complex con-tentionscenariocanbedecomposedintothebasicpatternsandexpressedwithacontentiontree. This contention tree model captures not only the tagged flow’s contention with otherinterfering flows along its routing path but also the indirect contention experienced bythe interfering flows. We scan the tree to compute the output arrival curves of the flowstraversing each branch in the contention tree. Then we derive the equivalent service curvefor the tagged flow traversing the trunk of tree and calculate its delay bound. We proposeananalysisprocedurewhichcontainstwo mainalgorithms: 1)constructacontentiontree;2) scan the tree and compute the equivalent service curve for the tagged flow. We derivea closed-form formula to calculate the delay bound for all-to-one gather communication,which is an important collective operation for parallel processing. Experimental resultsvalidate the consistency of simulated maximum delays and our analytical bounds. Wealso perform comparative analysis on Bakhouya’s model, Fidler’s model and ours.
     (2) Comparative analysis of communication performance for 2D and 3D NoCs
     Advanced integration technologies enable the construction of NoC from two dimen-sions to three dimensions. 3D NoCs can improve average communication performancebecause of the possibility of using the additional dimension to shorten communicationdistance. We study the worst-case communication performance in regular k-ary-2-meshnetworks and their 3D counterparts. Through both analysis and simulation, we show that,while the average performance in 3D NoCs is better than that of their 2D counterparts,the worst-case communication performance in 3D NoCs may be worse than that of their2D counterparts. The worst-case delay is more sensitive to the vertical link bandwidth,the network size and traffic burstiness. The 3D worst-case delay bound becomes worsethan the 2D worst-case delay bound for lower vertical link bandwidth, smaller topologysize and larger traffic burstiness. This suggests that a thorough investigation on not onlyaverage but also worst-case performance is necessary when dimensioning the networktopology from 2D to 3D.
     (3) Analyzing credit-based link-level flow control for on-chip networks
     Credit-based router-to-router flow control is one main link-level flow control mech-anism proposed for NoCs. Based on network calculus, we analyze its performance andoptimal buffer size. To model the feedback control behavior due to credits, we introducean abstract network service element called flow controller. Then we derive its servicecurve, and further the system service curve with theorematic forms. In addition, we giveand prove a theorem that determines the optimal buffer size guaranteeing the maximumsystem service curve. Moreover, assuming the latency-rate server model for routers, wegive closed-form formulas to calculate the flit delay bound and optimal buffer size. Ourexperiments with real on-chip traffic traces validate that our analysis is consistent and theoptimal buffer size is exact.
     (4) Analyzing wormhole switching with virtual channels in NoCs
     Based on network calculus, we derive per-flow worst-case flit delay bounds fordeadlock-free virtual-channel (VC) wormhole networks. In such networks, packet trans-mission may be stalled due to lack of credits, failure of switch allocation and VC alloca-tion. Webuildanalyticalmodelsforflowsunderthesestallingconditions. Bysequentiallyapplyingtheanalyticalmodelsforflowcontrolandlinksharing,wecanobtainasimplifiedanalysis model, which eliminates the feedback control and link contention. As keeping only the buffer sharing and network structure of initial model, this model is called buffer-sharing analysis network. The problem is transformed into the contention tree model, toderive per-flow end-to-end equivalent service curve which the tandem of routers provide.We propose an algorithm to construct the buffer-sharing analysis network and summarizea general analysis procedure to derive the delay bound. The derivation of delay boundand closed-form formulas are presented by supposing that the arrival curve conforms tothe affine function and the service curve follows the latency-rate function.
     In summary, we aim to drive per-flow end-to-end delay bound. Based on networkcalculus, we have proposed four calculus models of contention tree, comparative analysisof 2D and 3D topologies, flow control and wormhole switching, which establish a set ofcomplete deterministic approaches for NoCs’performance analysis, and develop a newapplication field for this emerging mathematical theory of network calculus.
引文
[1] Semiconductor Industry Association. The International Tech-nology Roadmap for Semiconductors (ITRS) 2009 Edition.http://www.itrs.net/Links/2009ITRS/Home2009.htm.
    [2] Lu Z, Jantsch A. Trends of terascale computing chips in the next ten years [C].In Proceedings of IEEE 8th International Conference on ASIC. Changsha, Hunan,China, Oct. 2009: 62–66.
    [3] BorkarS.Thousandcorechips:atechnologyperspective[C].InProceedingsofthe44th annual Design Automation Conference. San Diego, CA, Jun. 2007: 746–749.
    [4] Horowitz M, Ho R, Mai K. The future of wires [J]. Proceedings of the IEEE. 2001,89 (4): 490–504.
    [5] Dally W J, Towles B. Route packets, not wires: On-Chip Interconnection Net-works [C]. In Proceedings of the 38th Design Automation Conference. Jun. 2001:684–689.
    [6] Jantsch A, Tenhunen H. Networks on Chip [M]. Kluwer Academic Publishers,2003.
    [7] Micheli G D, Benini L. Networks on Chips: Technology and Tools [M]. MorganKaufmann, 2006.
    [8] OwensJD,DallyWJ,HoR,etal.Researchchallengesforon-chipinterconnectionnetworks [J]. IEEE Micro. 2007, 27 (5): 96–108.
    [9] Guerrier P, Greiner A. A generic architecture for on-chip packet-switched inter-connections [C]. In Proceedings of the Design, Automation and Test in EuropeConference. Mar. 2000: 250–256.
    [10] Hemani A, Jantsch A, Kumar S, et al. Network on chip: An architecture for billiontransistor era [C]. In Proceedings of the IEEE NorChip Conference. Nov. 2000.
    [11] Benini L, Micheli G D. Powering networks on chips: energy-efficient and reliableinterconnect design for SoCs [C]. In Proceedings of the 14th international sympo-sium on Systems synthesis. 2001: 33–38.
    [12] Bjerregaard T, Mahadevan S. A survey of research and practices of Network-on-chip [J]. ACM Computing Survey. 2006, 38 (1): 1–51.
    [13] Henkel J, Wolf W, Chakradhar S. On-chip networks: a scalable, communication-centric embedded system design paradigm [C]. In Proceedings of the 17th Inter-national Conference on VLSI Design. Jan. 2004: 845–851.
    [14] Ogras U Y, Hu J, Marculescu R. Key research problems in NoC design: a holisticperspective [C]. In Proceedings of the 3rd IEEE/ACM/IFIP international confer-ence on Hardware/software codesign and system synthesis. Sep. 2005: 69–74.
    [15] Marculescu R, Ogras U Y, Peh L S, et al. Outstanding Research Problems in NoCDesign: System, Microarchitecture, and Circuit Perspectives [J]. IEEE Transac-tions on Computer-Aided Design of Integrated Circuits and Systems. 2009, 28 (1):3–21.
    [16] Lieverse P, Wolf P V D, Vissers K, et al. A Methodology for Architecture Explo-ration of Heterogeneous Signal Processing Systems [J]. Journal of VLSI SignalProcessing Systems. 2001, 29 (3): 197–207.
    [17] Park K, Willinger W. Self-Similar Network Traffic and Performance Evalua-tion [M]. 1st ed. John Wiley & Sons, 2000.
    [18] Varatkar G V, Marculescu R. On-chip traffic modeling and synthesis for MPEG-2video applications [J]. IEEE Transactions on Very Large Scale Integration (VLSI)Systems. 2004, 12 (1): 108–119.
    [19] Soteriou V, Wang H, Peh L S. A Statistical Traffic Model for On-Chip Intercon-nection Networks [C]. In Proceedings of the 14th IEEE International Symposiumon Modeling, Analysis, and Simulation. Sep. 2006: 104–116.
    [20] Scherrer A, Fraboulet A, Risset T. Long-range dependence and on-chip processortraffic [J]. Microprocessors & Microsystems. 2009, 33 (1): 72–80.
    [21] Adriahantenaina A, Charlery H, Greiner A, et al. SPIN: A Scalable, PacketSwitched, On-Chip Micro-Network [C]. In Proceedings of the conference on De-sign, Automation and Test in Europe: Designers’Forum. 2003.
    [22] Louhenper¨a R, Nilsson O. Evaluation of the EXSITE Programme [R]. TechnologyProgramme Report 21/2003 Evaluation Report, 2003.
    [23] Benini L, De Micheli G. Networks on chips: A new SoC paradigm [J]. IEEE Com-puter. 2002, 35 (1): 70–78.
    [24] Sankaralingam K, Nagarajan R, Liu H, et al. Exploiting ILP, TLP, and DLP withthe polymorphous TRIPS architecture [J]. ACM SIGARCH Computer Architec-ture News. 2003, 31 (2): 422–433.
    [25] SankaralingamK,NagarajanR,GratzP,etal.TheDistributedMicroarchitectureoftheTRIPSPrototypeProcessor[C].InProceedingsofthe39thAnnualIEEE/ACMInternational Symposium on Microarchitecture. Dec. 2006: 480–491.
    [26] Liang J, Swaminathan S, Tessier R. aSOC: A Scalable, Single-Chip Communi-cations Architecture [C]. In Proceedings of the 2000 International Conference onParallel Architectures and Compilation Techniques. 2000: 37–46.
    [27] Liang J, Laffely A, Srinivasan S, et al. An architecture and compiler for scalableon-chip communication [J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems. 2004, 12 (7): 711–726.
    [28] Millberg M, Nilsson E, Thid R, et al. The Nostrum backbone - a communicationprotocol stack for networks on chip [C]. In Proceedings of the 17th VLSI DesignConference. Jan. 2004.
    [29] Kumar S, Jantsch A, Soininen J P, et al. A network on chip architecture and designmethodology [C]. In Proceedings of IEEE Computer Society Annual Symposiumon VLSI. 2002: 105–112.
    [30] Dall’Osso M, Biccari G, Giovannini L, et al. Xpipes: a latency insensitive parame-terized network-on-chip architecture for multiprocessor SoCs [C]. In Proceedingsof the 21st International Conference on Computer Design. 2003: 536–539.
    [31] Bolotin E, Cidon I, Ginosar R, et al. QNoC: QoS architecture and design processfor network on chip [J]. Journal of Systems Architecture, Special Issue on Net-works on Chip. 2004, 50 (2-3): 105–128.
    [32] Bjerregaard T, Sparso J. A Router Architecture for Connection-Oriented ServiceGuaranteesintheMANGOClocklessNetwork-on-Chip[C].InProceedingsoftheDesign, Automation and Test in Europe Conference. 2005: 1226–1231.
    [33] Rijpkema E, Goossens K, Wielage P. A Router Architecture for Networks on Sil-icon [C]. In Proceedings of Progress 2001, 2nd Workshop on Embedded Systems.Oct. 2001.
    [34] Goossens K, Dielissen J, R?adulescu A. The ?thereal Network on Chip: Concepts,Architectures, and Implementations [J]. IEEE Design & Test of Computers. 2005,22 (5): 414–421.
    [35] Steenhof F, Duque H, Nilsson B, et al. Networks on chips for high-end consumer-electronics TV system architectures [C]. In Proceedings of the conference on De-sign, automation and test in Europe: Designers’forum. 2006: 148–153.
    [36] Hofstee H P. Power efficient processor architecture and the cell processor [C].In Proceedings of the International Symposium on High Performance ComputerArchitecture. Feb. 2005: 258–262.
    [37] Gschwind M, D’Amora B, O’Brien K, et al. Cell broadband engine - enablingdensity computing for data-rich environment [C]. In Tutorial held in conjunctionwith the International Symposium on Computer Architecture. Jun. 2006.
    [38] Coppola M, Locatelli R, Maruccio G, et al. Spidergon: a novel on chip communi-cation network [C]. In Proceedings of 2004 International Symposium on Systemon Chip. Nov. 2004.
    [39] Coppola M, Grammtikakis M D, Locatelli R, et al. Design of Cost-Efficient Inter-connect Processing Units: Spidergon STNoC [M]. CRC Press, 2008.
    [40] iNoCs. http://www.inocs.com/.
    [41] Arteris. http://www.arteris.com/.
    [42] Silistix. http://www.silistix.com/.
    [43] Vangal S, Howard J, Ruhl G, et al. An 80-tile 1.28 TFLOPS network-on-chip in65nm CMOS [C]. In International Solid-State Circuits Conference. Feb. 2007:98–99.
    [44] Hoskote Y, Vangal S, Singh A, et al. A 5-GHz mesh interconnect for a Teraflopsprocessor [J]. IEEE MICRO. 2007, 27 (5): 51–61.
    [45] Vangal S R, Howard J, Ruhl G, et al. An 80-tile sub-100-w TeraFLOPS processorin 65-nm CMOS [J]. IEEE Journal of Solid State Circuits. 2008, 43 (1): 29–41.
    [46] BellS,EdwardsB,AmannJ,etal.TILE64processor:A64-coreSoCwithmeshin-terconnect [C]. In International IEEE Solid-State Circuits Conference. Feb. 2008:88–89.
    [47] Agarwal A, Bao L, Brown J, et al. Tile Processor: Embedded Multicore for Net-working and Multimedia [C]. In Proceedings of Hot Chips: Symposium on HighPerformance Chips. Aug. 2007.
    [48] Wentzlaff D, Griffin P, Hoffman H, et al. On-chip interconnection architecture ofthe Tile processor [J]. IEEE Micro. 2007, 27 (5): 15–31.
    [49] The 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS2010). http://www.minatec.org/nocs2010/index.htm.
    [50] Pande P P, Grecu C, Ivanov A, et al. Design, Synthesis, and Test of Networks onChips [J]. IEEE Design & Test of Computers. 2005, 22 (5): 404–413.
    [51] GoossensK,DielissenJ,GangwalOP,etal.Adesignflowforapplication-specificnetworks on chip with guaranteed performance to accelerate SoC design and ver-ification [C]. In Proceedings of the conference on Design, Automation and Test inEurope. Mar. 2005: 1182–1187.
    [52] Leung L F, Tsui C Y. Optimal link scheduling on improving best-effort and guar-anteed services performance in network-on-chip systems [C]. In Proceedings ofthe 43rd annual Design Automation Conference. Jul. 2006: 833–838.
    [53] Millberg M, Nilsson E, Thid R, et al. Guaranteed bandwidth using looped con-tainers in temporally disjoint networks within the Nostrum network on chip [C].In Proceedings of the conference on Design, Automation and Test in Europe. Feb.2004: 890–895.
    [54] BeigneE,ClermidyF,VivetP,etal.AnasynchronousNOCarchitectureprovidinglow latency service and its multi-level design framework [C]. In Proceedings ofthe 11th IEEE International Symposium on Asynchronous Circuits and Systems.May 2005: 54–63.
    [55] Harmanci M, Escudero N, Leblebici Y, et al. Quantitative modelling and compar-ison of communication schemes to guarantee quality-of-service in networks-on-chip [C]. In Proceedings of 2005 IEEE International Symposium on Circuits andSystems. May 2005: 1782–1785.
    [56] Marescaux T, Corporaal H. Introducing the SuperGT network-on-chip: SuperGTQoS:morethanjustGT[C].InProceedingsofthe44thannualDesignAutomationConference. San Diego, CA, Jun. 2007: 116–121.
    [57] van den Brand J W, Ciordas C, Goossens K, et al. Congestion-controlled best-effort communication for networks-on-chip [C]. In Proceedings of the conferenceon Design, automation and test in Europe. Nice, France, Apr. 2007: 948–953.
    [58] Duato J, Johnson I, Flich J, et al. A New Scalable and Cost-Effective CongestionManagement Strategy for Lossless Multistage Interconnection Networks [C]. InProceedingsofthe11thInternationalSymposiumonHigh-PerformanceComputerArchitecture. Feb. 2005: 108–119.
    [59] Nilsson E, Millberg M, Oberg J, et al. Load Distribution with the Proximity Con-gestion Awareness in a Network on Chip [C]. In Proceedings of the conference onDesign, Automation and Test in Europe. Mar. 2003: 1126–1127.
    [60] Ogras U Y, Marculescu R. Analysis and optimization of prediction-based flowcontrolinnetworks-on-chip[J].ACMTransactionsonDesignAutomationofElec-tronic Systems. 2008, 13 (1): 1–28.
    [61] Dielissen J, Radulescu A, Goossens K, et al. Concepts and implementation of thePhilips network-on-chip [J]. IP-Based SoC Design. 2003.
    [62] Murali S, Micheli G D. Bandwidth-Constrained Mapping of Cores onto NoC Ar-chitectures [C]. In Proceedings of the conference on Design, automation and testin Europe. Feb. 2004: 896–901.
    [63] SrinivasanK,ChathaKS,KonjevodG.Linear-programming-basedtechniquesforsynthesis of network-on-chip architectures [J]. IEEE Transactions on Very LargeScale Integration (VLSI) Systems. 2006, 14 (4): 407–420.
    [64] OgrasUY,MarculescuR.AnalyticalRouterModelingforNetworks-on-ChipPer-formance Analysis [C]. In Proceedings of the conference on Design, Automationand Test in Europe. Nice, France, 2007: 1096–1101.
    [65] Banerjee N, Vellanki P, Chatha K S. A power and performance model for network-on-chip architectures [C]. In Proceedings of the conference on Design, automationand test in Europe. Feb. 2004: 1250–1255.
    [66] Chan J, Parameswaran S. NoCEE: energy macro-model extraction methodologyfor network on chip routers [C]. In Proceedings of the 2005 IEEE/ACM Interna-tional Conference on Computer-Aided Design. Nov. 2005: 254–259.
    [67] Chen X, Peh L S. Leakage power modeling and optimization in interconnectionnetworks [C]. In Proceedings of the 2003 international symposium on Low powerelectronics and design. Seoul, Korea, Aug. 2003: 90–95.
    [68] EisleyN,PehLS.High-levelpoweranalysisforon-chipnetworks[C].InProceed-ingsofthe2004internationalconferenceonCompilers,architecture,andsynthesisfor embedded systems. 2004: 104–115.
    [69] Kim J S, Taylor M B, Miller J, et al. Energy characterization of a tiled archi-tecture processor with on-chip networks [C]. In Proceedings of the 2003 interna-tional symposium on low power electronics and design. Seoul, Korea, Aug. 2003:424–427.
    [70] Shang L, Peh L S, Kumar A, et al. Thermal modeling, characterization and man-agement of on-chip networks [C]. In Proceedings of the 37th annual IEEE/ACMInternational Symposium on Microarchitecture. 2004: 67–78.
    [71] Kogel T, Doerper M, Wieferink A, et al. A modular simulation framework for ar-chitectural exploration of on-chip interconnection networks [C]. In Proceedings ofthe 1st IEEE/ACM/IFIP international conference on Hardware/software codesignand system synthesis. Newport Beach, CA, Oct. 2003: 7–12.
    [72] Madsen J, Mahadevan S, Virk K, et al. Network-on-Chip Modeling for System-Level Multiprocessor Simulation [C]. In Proceedings of the 24th IEEE Interna-tional Real-Time Systems Symposium. Dec. 2003: 265–274.
    [73] Palermo G, Silvano C. PIRATE: A Framework for Power/Performance Explo-ration of Network-On-Chip Architectures [C]. In Proceedings of InternationalWorkshop on Power And Timing Modeling, Optimization and Simulation. San-torini, Greece, Sep. 2004: 521–531.
    [74] Wang H S, Zhu X, Peh L S, et al. Orion: a power-performance simulator for inter-connection networks [C]. In Proceedings of the 35th annual ACM/IEEE interna-tional symposium on Microarchitecture. Istanbul, Turkey, Nov. 2002: 294–305.
    [75] Pande P P, Grecu C, Jones M, et al. Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures [J]. IEEE Transactions onComputers. 2005, 54 (8): 1025–1040.
    [76] GenkoN,MicheliGD,AtienzaD,etal.ACompleteNetwork-On-ChipEmulationFramework [C]. In Proceedings of the conference on Design, Automation and Testin Europe. Mar. 2005: 246–251.
    [77] MahadevanS,AngioliniF,StorgaardM,etal.ANetworkTrafficGeneratorModelfor Fast Network-on-Chip Simulation [C]. In Proceedings of the conference onDesign, Automation and Test in Europe. Mar. 2005: 780–785.
    [78] Carloni L P, Pande P, Xie Y. Networks-on-Chip in Emerging InterconnectParadigms:AdvantagesAndChallenges[C].InProceedingsofthe3rdACM/IEEEInternational Symposium on Networks-on-Chip. San Diego, CA, May 2009.
    [79] Jose A P, Patounakis G, Shepard K L. Pulsed current-mode signaling for nearlyspeed-of-lightintrachipcommunication[J].ProceedingsoftheIEEE.2006,41(4):772–780.
    [80] Kim B, Stojanovi′c V. Equalized interconnects for on-chip networks: modeling andoptimization framework [C]. In Proceedings of the 2007 IEEE/ACM InternationalConference on Computer-Aided Design. San Jose, CA, Nov. 2007: 552–559.
    [81] Kirman N, Kirman M, Dokania R K, et al. Leveraging optical technology in futurebus-basedchipmultiprocessors[C].InProceedingsofthe39thAnnualIEEE/ACMInternational Symposium on Microarchitecture. Dec. 2006: 492–503.
    [82] Shacham A, Bergman K, Carloni L P. The case for low-power photonic networkson chip [C]. In Proceedings of the 44th annual Design Automation Conference.San Diego, CA, Jun. 2007: 132–135.
    [83] Chang M F, Cong J, Kaplan A, et al. CMP network-on-chip overlaid with multi-band RF-interconnect [C]. In IEEE 14th International Symposium on High Perfor-mance Computer Architecture. Feb. 2008: 191–202.
    [84] Snoeckx K, Beyne E, Swinnen B. Copper-nail TSV technology for 3D-stacked ICIntegration [J]. Solid State Technology. 2007, 50 (5): 53–55.
    [85] HopkinsD,ChowA,BosnyakR,etal.Circuittechniquestoenable430GB/s/mm2proximity communication [C]. In International Solid-State Circuits Conference.2007.
    [86]林世俊,张凡,金德鹏,等.分布式同步的GALS片上网络及其接口设计[J].清华大学学报.2008,1.
    [87]马立伟,孙义和.片上网络拓朴优化:在离散平面上布局与布线[J].电子学报.2007,35(5).
    [88]王宏伟,陆俊林,佟冬,等.层次化片上网络结构的簇生成算法[J].电子学报.2007,35(5).
    [89]朱晓静,胡伟武,马可,等. Xmesh:一个mesh-like片上网络拓扑结构[J].软件学报.2007,18(9).
    [90]朱晓静.片上网络的结构设计与性能分析[D].合肥:中国科学技术大学,2008.
    [91]张磊,李华伟,李晓维.用于片上网络的容错通信算法[J].计算机辅助设计与图形学学报.2007,4.
    [92]黄琨,马可,曾洪博,等.一种分片式多核处理器的用户级模拟器[J].软件学报.2008,19(4).
    [93]付方发,张庆利,王进祥,等.支持多种流量分布的片上网络性能评估技术研究[J].哈尔滨工业大学学报.2007,39(5).
    [94]李磊.片上网络NoC的通信研究[D].杭州:浙江大学,2007.
    [95]武畅.片上网络体系结构和关键通信技术研究[D].西安:电子科技大学,2008.
    [96]常政威.网络化MPSoC高能效设计技术研究[D].西安:电子科技大学,2009.
    [97]荆元利.基于片上网络的系统芯片研究[D].西安:西北工业大学,2005.
    [98]肖翔,董渭清,文敏华.网环步进码片上网络自适应路由算法设计[J].西安交通大学学报.2009,43(12).
    [99]唐杉.基于片上网络互联的SoC调试技术研究[D].北京:北京邮电大学,2007.
    [100]赵宏智.片上网络中交换机服务性能及其影响的研究[D].北京:北京科技大学,2007.
    [101]杨盛光,李丽,高明伦,等.面向能耗和延时的NoC映射方法[J].电子学报.2008,36(5).
    [102]段新明.面向NoC的无死锁路由算法的研究[D].天津:南开大学,2007.
    [103]陶海洋.片上网络低能耗和低延迟研究[D].长沙:湖南大学,2009.
    [104]朱兵.基于片上网络的通信路由方法研究[D].合肥:合肥工业大学,2009.
    [105]刘祥远.多核SoC片上网络关键技术研究[D].长沙:国防科学技术大学,2007.
    [106]国家自然科学基金委员会.http://isis.nsfc.gov.cn/.
    [107] Le Boudec J Y, Thiran P. Network Calculus: A Theory of Deterministic QueuingSystems for the Internet [M]. Number 2050 in LNCS, Springer-Verlag, 2004.
    [108] Chang C S. Performance Guarantees in Communication Networks [M]. Springer-Verlag, 2000.
    [109] Cruz R L. A calculus for network delay, Part I: Network elements in isolation [J].IEEE Transactions on Information Theory. 1991, 37 (1): 114–131.
    [110] Cruz R L. A calculus for network delay, Part II: Network analysis [J]. IEEE Trans-actions on Information Theory. 1991, 37 (1): 132–141.
    [111] Parekh A K, Gallager R G. A generalized processor sharing approach to flow con-trol in integrated services networks: the single-node case [J]. IEEE/ACM Trans-actions on Networking. 1993, 1 (3): 344–357.
    [112] Parekh A K, Gallager R G. A generalized processor sharing approach to flow con-trol in integrated services networks: the multiple node case [J]. IEEE/ACM Trans-actions on Networking. 1994, 2 (2): 137–150.
    [113] Zhang H. Service disciplines for guaranteed performance service in packet-switching networks [J]. Proceedings of the IEEE. 1995, 83 (10).
    [114] Cruz R L. Quality of service guarantees in virtual circuit switched networks [J].IEEE Journal on Selected Areas in Communications. 1995, 13 (6): 1048–1056.
    [115] Sariowan H. A service curve approach to performance guarantees in integratedservice networks [D]. USA: University of California, San Diego, 1996.
    [116] Le Boudec J Y. Network Calculus Made Easy [R]. Technical Report DI96/218,Ecole Polytechnique Federale, Lausanne (EPFL), 1996.
    [117] Agrawal R, Rajan R. Performance bounds for guaranteed and adaptive ser-vices [R]. Technical Report RC 20649, IBM Research Division, 1996.
    [118] CruzRL,OkinoCM.Serviceguaranteesforwindowflowcontrol[C].InProceed-ings of Allerton Ccnference on Communication, Control, and Computing. Monti-cello, IL, Oct. 1996.
    [119] LeBoudecJY.Applicationofnetworkcalculustoguaranteedservicenetworks[J].IEEE Transactions on Information Theory. 1998, 44 (3): 1087–1096.
    [120] ChangCS.Ondeterministictrafficregulationandserviceguarantee:Asystematicapproach by filtering [J]. IEEE Transactions on Information Theory. 1998, 44 (3):1097–1110.
    [121] Chang C S. Stability, queue length, and delay of deterministic and stochasticqueueing networks [J]. IEEE Transactions on Automatic Control. 1994, 39 (5):913–931.
    [122] Cruz R L. Quality of Service Management in Integrated Services Networks [C].In Proceedings of the 1st Semi-Annual Research Review, CWC, UCSD. 1996.
    [123] Ciucu F, Burchard A, Liebeherr J. A network service curve approach for thestochastic analysis of networks [C]. In Proceedings of the 2005 ACM SIGMET-RICS. 2005: 279–290.
    [124] Fidler M. An End-to-End Probabilistic Network Calculus with Moment Generat-ingFunctions[C].InProceedingsof14thIEEEInternationalWorkshoponQualityof Service. Jun. 2006: 261–270.
    [125] Jiang Y, Emstad P J. Analysis of Stochastic Service Guarantees in CommunicationNetworks: A Server Model [C]. In Proceedings of 13th International Workshop onQuality of Service. Jun. 2005.
    [126] Jiang Y, Emstad P J. Analysis of stochastic service guarantees in communica-tion networks: A traffic model [C]. In Proceedings of 19th International TeletrafficCongress. Aug. 2005.
    [127] Jiang Y. A basic stochastic network calculus [J]. ACM SIGCOMM ComputerCommunication Review. 2006, 36 (4): 123–134.
    [128] Jiang Y, Liu Y. Stochastic Network Calculus [M]. Springer, 2008.
    [129] Charny A, Le Boudec J Y. Delay bounds in a network with aggregate schedul-ing [C]. In Proceedings of the First COST 263 International Workshop on Qualityof Future Internet Services. 2000: 1–13.
    [130] BaccelliF,HongD.TCPismax-pluslinearandwhatittellsusonitsthroughput[J].ACM SIGCOMM Computer Communication Review. 2000, 30 (4): 219–230.
    [131]蔡研,赵千川.基于极大代数的TCP协议分析[J].计算机学报.2002,25 (11).
    [132] Altman E, Avrachenkov K, Barakat C. TCP Network Calculus: The Case ofLarge Delay-bandwidth Product [C]. In Proceedings of IEEE INFOCOM. 2002:417–426.
    [133] Godskesen J C. A Calculus for Mobile Ad Hoc Networks [C]. In Proceedings ofthe 9th International Conference on Coordination Models and Languages. Paphos,Cyprus, Jun. 2007: 132–150.
    [134] Schmitt J, Roedig U. Sensor Network Calculus - a Framework for Worst CaseAnalysis [C]. In Proceedings of the International Conference on Distributed Com-puting in Sensor Systems. 2005: 141–154.
    [135] Agharebparast F, Leung V C M. Modeling wireless link layer by network for ef-ficient evaluations of multimedia QoS [C]. In Proceedings of IEEE InternationalConference on Communications. May 2005: 1256–1260.
    [136] Xu H, Gao Y, Tian H, et al. Network Calculus Modeling and Qos Analysis forWirelessPacketNetworks[C].InProceedingsofIEEE65thVehicularTechnologyConference. 2007.
    [137] Brahimi B, Aubrun C, Rondeau E. Network Calculus Based FDI Approach forSwitched Ethernet Architecture [C]. In Proceedings of the 6th IFAC SymposiumonFaultDetection,SupervisionandSafetyofTechnicalProcesses.Beijing,China,2006.
    [138] Thiele L, Chakraborty S, Naedele M. Real-time Calculus for Scheduling HardReal-Time Systems [C]. In Proceedings of The 2000 IEEE International Sympo-sium on Circuits and Systems. Geneva, Switzerland, Mar. 2000: 101–104.
    [139] Qian Y, Lu Z, Dou W. Analysis of Worst-case Delay Bounds for Best-effort Com-munication in Wormhole Networks on Chip [C]. In Proceedings of the 2009 3rdACM/IEEEInternationalSymposiumonNetworks-on-Chip.SanDiego,CA,May2009: 44–53.
    [140] Bakhouya M, Suboh S, Gaber J, et al. Analytical Modeling and Evaluation ofOn-Chip Interconnects Using Network Calculus [C]. In Proceedings of the 3rdACM/IEEEInternationalSymposiumonNetworks-on-Chip.SanDiego,CA,May2009.
    [141] Coenen M, Murali S, Radulescu A, et al. A buffer-sizing Algorithm for Networkson Chip using TDMA and credit-based end-to-end Flow Control [C]. In Proceed-ingsofthe4thinternationalconferenceonHardware/softwarecodesignandsystemsynthesis. Seoul, Korea, 2006: 130–135.
    [142]张信明,陈国良,顾钧.基于网络演算计算保证服务端到端延迟上界[J].软件学报.2001,12 (6): 889–893.
    [143]张信明,陈国良,顾钧.基于网络演算的流量整形模型[J].软件学报.2002,13 (12): 225–230.
    [144]张信明.基于网络演算的Internet QoS控制模型[D].合肥:中国科学技术大学,2001.
    [145]张连明,陈志刚,赵明,等.基于分形整形器的GPS系统性能确定上界研究[J].通信学报.2007,2.
    [146]张连明,黄大足,陈志刚.基于分形漏桶的长程相关业务端到端延迟上界模型[J].通信学报.2008,7.
    [147]李庆华,陈志刚,张连明,等.基于网络演算的无线自组网QoS性能确定上界研究[J].通信学报.2008,9.
    [148]漆华妹,陈志刚.基于统计网络演算的无线mesh网络流量模型[J].通信学报.2009,7.
    [149]张连明.基于网络演算的自相似网络性能上界模型研究[D].长沙:中南大学,2006.
    [150]辛建波.基于以太网的变电站自动化系统时延不确定性研究[D].武汉:华中科技大学,2005.
    [151]陈京文.基于统计型演算论的网络服务性能分析[D].武汉:华中科技大学,2007.
    [152]胡晓娅.基于交换式以太网的网络控制系统研究[D].武汉:华中科技大学,2006.
    [153]王子君,许维胜,王中杰,等.控制网络的确定性延迟演算理论研究[J].电子学报.2006,1.
    [154]高岭,李增智,王峥,等.缓冲区有限流量整形器性能参数的最小加代数表示[J].西安交通大学学报.2005,10.
    [155]谭献海,李明辉,金炜东.IntServ网络资源优化分配方法[J].西南交通大学学报.2008,2.
    [156]李明辉.基于网络演算的网络建模方法研究[D].成都:西南交通大学,2007.
    [157]武珊珊,于戈,吕雁飞,等.数据流处理中确定性QoS的保证方法[J].软件学报.2008,8.
    [158]周立,赵然,于航,等.航空电子WDM网络的实时性能分析[J].北京航空航天大学学报.2009,11.
    [159]樊葆华,窦强,张鹤颖.网络演算的矩阵解释[J].计算机学报.2009,12.
    [160]巩艳蓉,曾烈光.弹性分组环网络中最大接入延时[J].清华大学学报(自然科学版). 2007,1.
    [161]王峥.IP网络下的自适应区分服务体系研究[D].西安:西北大学,2005.
    [162]马克刚.工业以太网在网络控制系统中的应用研究[D].合肥:合肥工业大学,2005.
    [163]邱春荣.端到端QoS控制策略研究及其在SHM中的应用[D].长沙:湖南大学,2005.
    [164]钟伟胜.基于网络的实时调度策略研究[D].长沙:湖南师范大学,2009.
    [165]张原,石改辉.全双工交换式以太网实时通信研究[J].西北工业大学学报.2008,4.
    [166]赵欣.基于网络演算的延迟计算方法与应用[D].武汉:武汉大学,2003.
    [167]唐宇波,段金蓉,刘玉嘉.基于网络演算的测控局域网时延性能分析方法研究[J].飞行器测控学报.2006,6.
    [168]张奇智,张彬,张卫东.基于网络演算计算交换式工业以太网中的最大时延[J].控制与决策.2005,1.
    [169]樊葆华.基于网络演算的计算机网络性能分析模型研究[D].长沙:国防科学技术大学,2009.
    [170] Henriksson T, van der Wolf P, Jantsch A, et al. Network Calculus Applied to Veri-fication of Memory Access Performance in SoCs [C]. In Proceedings of the 5thIEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia.2007: 21–26.
    [171] Lu Z, Millberg M, Jantsch A, et al. Flow Regulation for On-Chip Communica-tion [C]. In Proceedings of the 2009 Design, Automation and Test in Europe Con-ference. Nice, France, Apr. 2009.
    [172] Keckler S, Olukotun K, Hofstee P. Multicore Processors and Systems [M].Springer, 2009.
    [173] Dally W J, Towles B. Principles and Practices of Interconnection Networks [M].Morgan Kaufman Publishers, 2004.
    [174] Duato J, Yalamanchili S, Ni L M. Interconnection Networks: An Engineering Ap-proach [M]. San Francisco, CA: Morgan Kaufmann Publishers, 2003.
    [175] DallyWJ,SeitzCL.Thetorusroutingchip[J].JournalofDistributedComputing.1986, 1: 187–196.
    [176] KimJ,BalfourJ,DallyWJ.Flattenedbutterflytopologyforon-chipnetworks[C].In Proceedings of the 40th Annual IEEE/ACM International Symposium on Mi-croarchitecture. Dec. 2007: 172–182.
    [177] Butts M. Synchronization through communication in a massively parallel proces-sor array [J]. IEEE MICRO. 2007, 27 (5): 32–40.
    [178] Kim J, Nicopoulos C, Park D, et al. A Novel Dimensionally-Decomposed Routerfor On-Chip Communication in 3D Architectures [C]. In Proceedings of the Inter-national Symposium on Computer Architecture. Jun. 2007.
    [179] SunC,ShangL,DickRP.Three-dimensionalmultiprocessorsystem-on-chipther-mal optimization [C]. In Proceedings of the 5th IEEE/ACM international confer-ence on Hardware/software codesign and system synthesis. 2007: 117–122.
    [180] Yan S, Lin B. Design of application-specific 3D Networks-on-Chip architec-tures [C]. In Proceedings of IEEE International Conference on Computer Design.2008: 142–149.
    [181] Singh A, Dally W J, Gupta A K, et al. Goal: a load-balanced adaptive routingalgorithm for torus networks [C]. In Proceedings of the 30th annual internationalsymposium on Computer architecture. San Diego, CA, June 2003: 194–205.
    [182] Gratz P, Grot B, Keckler S. Regional congestion awareness for load balance innetworks-on-chip [C]. In IEEE 14th International Symposium on High Perfor-mance Computer Architecture. Feb. 2008: 203–214.
    [183] Kermani P, Kleinrock L. Virtual cut-through: A new computer communicationswitching technique [J]. Computer Networks. 1979, 3: 267–286.
    [184] Dally W J. Virtual-Channel Flow Control [J]. IEEE Transactions on Parallel andDistributed Systems. 1992, 3 (2): 194–204.
    [185] KumarA,PehLS,KunduP,etal.Expressvirtualchannels:towardstheidealinter-connection fabric [C]. In Proceedings of the 34th annual international symposiumon Computer architecture. San Diego, CA, Jun. 2007: 150–161.
    [186] Enright Jerger N D, Peh L S, Lipasti M H. Circuit-Switched Coherence [C]. InProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip. April 2008: 193–202.
    [187] Kim J, Nicopoulos C, Park D. A Gracefully Degrading and Energy-Efficient Mod-ular Router Architecture for On-Chip Networks [C]. In Proceedings of the 33rdannual international symposium on Computer Architecture. Jun. 2006: 4–15.
    [188] NicopoulosCA,ParkD,KimJ,etal.ViChaR:Adynamicvirtualchannelregulatorfor network-on-chip routers [C]. In Proceedings of the 39th Annual IEEE/ACMInternational Symposium on Microarchitecture. Dec. 2006: 333–346.
    [189] Wang H, Peh L S, Malik S. Power-driven design of router microarchitectures inon-chip networks [C]. In Proceedings of the 36th annual IEEE/ACM InternationalSymposium on Microarchitecture. Nov. 2003: 105–116.
    [190] Fidler M, Sander V. A parameter based admission control for differentiated ser-vices networks [J]. Elsevier Computer Networks. 2004, 44 (4): 463–479.
    [191] Ostermann J, Bormans J, List P, et al. Video coding with H.264/AVC: tools, per-formance, and complexity [J]. IEEE Circuits and Systems Magazine. 2004, 4 (1):7–28.
    [192] Lu Z, Jantsch A. TDM Virtual-Circuit Configuration for Network-on-Chip [J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008, 16 (8):1021–1034.
    [193] Bouras C, Garofalakis J. Queueing delays in buffered multistage interconnectionnetworks [C]. In Proceedings of the 1987 ACM SIGMETRICS conference onMeasurement and modeling of computer systems. 1987: 111–121.
    [194] Agarwal A. Limits on Interconnection Network Performance [J]. IEEE Transac-tions on Parallel and Distributed Systems. 1991, 2 (4): 398–412.
    [195] Guz Z, Walter I, Bolotin E, et al. Efficient link capacity and QoS design fornetwork-on-chip [C]. In Proceedings of the conference on Design, Automationand Test in Europe. Mar. 2006.
    [196] Alzeidi N, Ould-Khaoua M, Mackenzie L M, et al. Performance Analysis ofAdaptively-RoutedWormhole-SwitchedNetworkswithFiniteBuffers[C].InPro-ceedings of IEEE International Conference on Communications. 2007: 38–43.
    [197] GrossD,ShortleJF,ThompsonJM,etal.FundamentalsofQueueingTheory[M].4th ed. John Wiley & Sons, 2008.
    [198] Lenzini L, Martorini L, Mingozzi E, et al. Tight End-to-End Per-Flow DelayBoundsinFIFOMultiplexingSink-TreeNetworks[J].ElsevierPerformanceEval-uation. 2006, 63 (9-10): 956–987.
    [199] SchmittJB,ZdarskyFA.TheDISCOnetworkcalculator:atoolboxforworstcaseanalysis [C]. In Proceedings of the 1st International Conference on PerformanceEvaluation Methodologies and Tools. Pisa, Italy, 2006.
    [200] Stiliadis D, Varma A. Latency-Rate Servers: A General Model for Analysis ofTrafficSchedulingAlgorithms[J].IEEE/ACMTransactionsonNetworking.1998,6 (5): 611–624.
    [201] OMNeT++ Discrete Event Simualtion System. http://www.omnetpp.org/.
    [202] Pavlidis V F, Friedman E G. 3-D Topologies for Networks-on-Chip [J]. IEEETransactions on Very Large Scale Integration (VLSI) Systems. 2007, 15 (10):1081–1090.
    [203] Garrou P, Bower C, Ramm P. Handbook of 3D Integration: Technology and Ap-plications of 3D Integrated Circuits [M]. Wiley-VCH, 2008.
    [204] Knickerbocker J U. 3D Chip Technology [J]. IBM Journal of Research and Devel-opment. 2008, 52 (6).
    [205] Weerasekera R, Zheng L R, Pamunuwa D, et al. Extending systems-on-chip tothe third dimension: performance, cost and technological tradeoffs [C]. In Pro-ceedings of the 2007 IEEE/ACM International Conference on Computer-AidedDesign. 2007: 212–219.
    [206] Emma P G, Kursun E. Is 3D chip technology the next growth engine for per-formance improvement? [J]. IBM Journal for Research and Development. 2008,52 (6): 541–552.
    [207] Swinnen B, Ruythooren W, Moor P D, et al. 3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10μm pitchthrough-Si vias [C]. In International Electron Devices Meeting. Dec. 2006: 1–4.
    [208] Miyakawa N, Hashimoto E, Maebashi T, et al. Multilayer stacking technology us-ing wafer-to-wafer stacked method [J]. ACM Journal on Emerging Technologiesin Computing Systems. 2008, 4 (4): 1–15.
    [209] Patti R S. Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs [J]. Proceedings of the IEEE. 2006, 94 (6): 1214–1224.
    [210] Weldezion A Y, Grange M, Pamunuwa D, et al. Scalability of Network-on-Chip Communication Architecture for 3D Meshes [C]. In Proceedings of the 3rdACM/IEEEInternationalSymposiumonNetworks-on-Chip.SanDiego,CA,May2009.
    [211] Feero B S, Pande P P. Networks-on-Chip in a Three-Dimensional Environment:A Performance Evaluation [J]. IEEE Transactions on Computers. 2009, 58 (1):32–45.
    [212] ParkD,EachempatiS,DasR,etal.MIRA:AMulti-LayeredOn-ChipInterconnectRouter Architecture [C]. In Proceedings of the 35th International Symposium onComputer Architecture. Jun. 2008: 251–261.
    [213] PamunuwaD, O¨bergJ,ZhengLR,etal.Astudyontheimplementationof2Dmeshbased networks on chip in the nanoregime [J]. Integration - The VLSI Journal.2004, 38 (2): 3–17.
    [214] Loi I, Mitra S, Lee T H, et al. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links [C]. In Proceedings of the 2008 IEEE/ACM In-ternational Conference on Computer-Aided Design. San Jose, CA, Nov. 2008:598–602.
    [215] Loi I, Angiolini F, Benini L. Supporting vertical links for 3D networks-on-chip:toward an automated design and analysis flow [C]. In Proceedings of the 2nd In-ternational Conference on Nano-Networks. Catania, Italy, 2007: 1–5.
    [216] Dally W J. Performance analysis of k-ary n-cube interconnection networks [J].IEEE Transactions on Computers. 1990, 39 (6): 775–785.
    [217] Li F, Nicopoulos C, Richardson T, et al. Design and Management of 3D ChipMultiprocessors Using Network-in-Memory [J]. ACM SIGARCH Computer Ar-chitecture News. 2006, 34 (2): 130–141.
    [218] GlassCJ,NiLM.TheTurnModelforAdaptiveRouting[C].InProceedingsofthe19th annual international symposium on Computer architecture. 1992: 278–287.
    [219] Murali S, Seiculescu C, Benini L, et al. Synthesis of networks on chips for 3Dsystems on chips [C]. In Proceedings of the 14th Asia and South Pacific DesignAutomation Conference. Yokohama, Japan, Jan. 2009.
    [220] Lu Z, Liu M, Jantsch A. Layered Switching for Networks on Chip [C]. In Pro-ceedings of the 44th annual Design Automation Conference. San Diego, CA, Jun.2007: 122–127.
    [221] Agrawal R, Cruz R L, Okino C, et al. Performance Bounds for Flow Control Pro-tocols [J]. IEEE/ACM Transactions on Networking. 1999, 7 (3): 310–323.
    [222] Geilen M, Basten T, Stuijk S. Minimising buffer requirements of synchronousdataflow graphs with model checking [C]. In Proceedings of the 42th Annual Con-ference on Design Automation. 2005: 819–824.
    [223] Hansson A, Wiggers M, Moonen A, et al. Applying Dataflow Analysis to Dimen-sionBuffersforGuaranteedPerformanceinNetworksonChip[C].InProceedingsof the Second ACM/IEEE International Symposium on Networks-on-Chip. 2008:211–212.
    [224] SoCLib Simulation Environment. https://www.soclib.fr/.
    [225] Qian Y, Lu Z, Dou W. Applying Network Calculus for Performance Analysis ofSelf-Similar Traffic in On-Chip Networks [C]. In Proceedings of IEEE/ACM/I-FIP 2009 International Conference on Hardware-Software Codesign and SystemSynthesis. Grenoble, France, Oct. 2009.
    [226] Norros I. On the Use of Fractal Brownian Motion in the Theory of Connection-less Networks [J]. IEEE Journal on Selected Areas Communication. 1995, 13 (6):953–962.
    [227] Bjerregaard T, Sparso J. A Scheduling Discipline for Latency and BandwidthGuarantees in Asynchronous Network-on-Chip [C]. In Proceedings of the 11thIEEE International Symposium on Asynchronous Circuits and Systems. Mar.2005: 34–43.
    [228] LiJP,MutkaMW.Real-TimeVirtualChannelFlowControl[J].JournalofParalleland Distributed Computing. 1996, 32 (1): 49–65.
    [229] Dally W J, Seitz C L. Deadlock free message routing in multiprocessor intercon-nection networks [J]. IEEE Transactions on Computers. 1987, 36 (5): 547–553.
    [230] Balakrishnan S, O¨zgu¨ner F. A Priority-Driven Flow Control Mechanism for Real-Time Traffic in Multiprocessor Networks [J]. IEEE Transactions on Parallel andDistributed Systems. 1998, 9 (7): 664–678.
    [231] Lu Z, Jantsch A, Sander I. Feasibility analysis of messages for on-chip networksusing wormhole routing [C]. In Proceedings of the Asia and South Pacific DesignAutomation Conference. Shanghai, China, Jan. 2005: 960–964.
    [232] Shi Z, Burns A. Real-Time Communication Analysis for On-Chip Networks withWormhole Switching [C]. In Proceedings of the Second ACM/IEEE InternationalSymposium on Networks-on-Chip. 2008: 161–170.
    [233] Brassil J T, Cruz R L. Bounds on Maximum Delay in Networks with DeflectionRouting [J]. IEEE Transactions on Parallel and Distributed Systems. 1995, 6 (7):724–732.
    [234] Moadeli M, Shahrabi A, Vanderbauwhede W, et al. An Analytical PerformanceModelfortheSpidergonNoC[C].InProceedingsofthe21stInternationalConfer-ence on Advanced Networking and Applications. Niagara Falls, Ontario, Canada,May 2007: 1014–1021.
    [235] Kim J, Park D, Nicopoulos C, et al. Design and analysis of an NoC architecturefrom performance, reliability and energy perspective [C]. In Proceedings of the2005 ACM symposium on Architecture for networking and communications sys-tems. 2005: 173–182.
    [236] Peh L S, Dally W J. A delay model and speculative architecture for pipelinedrouters [C]. In Proceedings of the 7th International Symposium on High-Performance Computer Architecture. 2001: 255–266.
    [237] Le Boudec J Y. Some Properties Of Variable Length Packet Shapers [J].IEEE/ACM Transactions on Networking. 2002, 10 (3): 329–337.
    [238] VermaD,ZhangH,FerrariD.Guaranteeingdelayjitterboundsinpacketswitchingnetworks [C]. In Proceedings of the IEEE Conference on Communication Soft-ware: Communications for Distributed Applications and Systems. Chapel Hill,North Carolina, Apr. 1991: 35–46.

© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号

地址:北京市海淀区学院路29号 邮编:100083

电话:办公室:(+86 10)66554848;文献借阅、咨询服务、科技查新:66554700